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OMAP2/3: UART: add omap_hwmod data for UARTs 1-4
[deliverable/linux.git] / arch / arm / mach-omap2 / serial.c
CommitLineData
1dbae815 1/*
f30c2269 2 * arch/arm/mach-omap2/serial.c
1dbae815
TL		 3 *
4 * OMAP2 serial support.
5 *
6e81176d 6 * Copyright (C) 2005-2008 Nokia Corporation
1dbae815
TL		 7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
4af4016c
KH		 9 * Major rework for PM support by Kevin Hilman
10 *
1dbae815
TL		 11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
44169075
SS		 13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15 *
1dbae815
TL		 16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/serial_8250.h>
23#include <linux/serial_reg.h>
f8ce2547 24#include <linux/clk.h>
fced80c7 25#include <linux/io.h>
e03d37d8 26#include <linux/delay.h>
1dbae815 27
ce491cf8
TL		 28#include <plat/common.h>
29#include <plat/board.h>
30#include <plat/clock.h>
31#include <plat/control.h>
4af4016c
KH		 32
33#include "prm.h"
34#include "pm.h"
35#include "prm-regbits-34xx.h"
36
ce13d471 37#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
4af4016c
KH		 38#define UART_OMAP_WER 0x17 /* Wake-up enable register */
39
5a927b36 40#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
00034509 41#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
5a927b36 42
301fe8ee
TL		 43/*
44 * NOTE: By default the serial timeout is disabled as it causes lost characters
45 * over the serial ports. This means that the UART clocks will stay on until
46 * disabled via sysfs. This also causes that any deeper omap sleep states are
47 * blocked.
48 */
49#define DEFAULT_TIMEOUT 0
4af4016c
KH		 50
51struct omap_uart_state {
52 int num;
53 int can_sleep;
54 struct timer_list timer;
55 u32 timeout;
56
57 void __iomem *wk_st;
58 void __iomem *wk_en;
59 u32 wk_mask;
60 u32 padconf;
61
62 struct clk *ick;
63 struct clk *fck;
64 int clocked;
65
66 struct plat_serial8250_port *p;
67 struct list_head node;
fd455ea8 68 struct platform_device pdev;
1dbae815 69
5a927b36 70 u32 errata;
4af4016c
KH		 71#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
72 int context_valid;
73
74 /* Registers to be saved/restored for OFF-mode */
75 u16 dll;
76 u16 dlh;
77 u16 ier;
78 u16 sysc;
79 u16 scr;
80 u16 wer;
5ade4ff5 81 u16 mcr;
4af4016c
KH		 82#endif
83};
84
4af4016c 85static LIST_HEAD(uart_list);
1dbae815 86
fd455ea8 87static struct plat_serial8250_port serial_platform_data0[] = {
1dbae815 88 {
1dbae815
TL		 89 .irq = 72,
90 .flags = UPF_BOOT_AUTOCONF,
91 .iotype = UPIO_MEM,
92 .regshift = 2,
6e81176d 93 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815 94 }, {
fd455ea8
KH		 95 .flags = 0
96 }
97};
98
99static struct plat_serial8250_port serial_platform_data1[] = {
100 {
1dbae815
TL		 101 .irq = 73,
102 .flags = UPF_BOOT_AUTOCONF,
103 .iotype = UPIO_MEM,
104 .regshift = 2,
6e81176d 105 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815 106 }, {
fd455ea8
KH		 107 .flags = 0
108 }
109};
110
111static struct plat_serial8250_port serial_platform_data2[] = {
112 {
1dbae815
TL		 113 .irq = 74,
114 .flags = UPF_BOOT_AUTOCONF,
115 .iotype = UPIO_MEM,
116 .regshift = 2,
6e81176d 117 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815
TL		 118 }, {
119 .flags = 0
120 }
121};
122
0e3eaadf
SS		 123static struct plat_serial8250_port serial_platform_data3[] = {
124 {
0e3eaadf
SS		 125 .irq = 70,
126 .flags = UPF_BOOT_AUTOCONF,
127 .iotype = UPIO_MEM,
128 .regshift = 2,
129 .uartclk = OMAP24XX_BASE_BAUD * 16,
130 }, {
131 .flags = 0
132 }
133};
a3a9b36e 134
4f2c49fe
TL		 135void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
136{
137 serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
138 serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
139 serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
4b1bbd3f 140 serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
4f2c49fe
TL		 141}
142
9230372a
AS		 143static inline unsigned int __serial_read_reg(struct uart_port *up,
144 int offset)
145{
146 offset <<= up->regshift;
147 return (unsigned int)__raw_readb(up->membase + offset);
148}
149
1dbae815
TL		 150static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
151 int offset)
152{
153 offset <<= up->regshift;
154 return (unsigned int)__raw_readb(up->membase + offset);
155}
156
e03d37d8
SS		 157static inline void __serial_write_reg(struct uart_port *up, int offset,
158 int value)
159{
160 offset <<= up->regshift;
161 __raw_writeb(value, up->membase + offset);
162}
163
1dbae815
TL		 164static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
165 int value)
166{
167 offset <<= p->regshift;
e8a91c95 168 __raw_writeb(value, p->membase + offset);
1dbae815
TL		 169}
170
171/*
172 * Internal UARTs need to be initialized for the 8250 autoconfig to work
173 * properly. Note that the TX watermark initialization may not be needed
174 * once the 8250.c watermark handling code is merged.
175 */
4af4016c 176static inline void __init omap_uart_reset(struct omap_uart_state *uart)
1dbae815 177{
4af4016c
KH		 178 struct plat_serial8250_port *p = uart->p;
179
1dbae815
TL		 180 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
181 serial_write_reg(p, UART_OMAP_SCR, 0x08);
182 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
671c7235 183 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
1dbae815
TL		 184}
185
4af4016c
KH		 186#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
187
00034509
D		 188/*
189 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
190 * The access to uart register after MDR1 Access
191 * causes UART to corrupt data.
192 *
193 * Need a delay =
194 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
195 * give 10 times as much
196 */
197static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
198 u8 fcr_val)
199{
200 struct plat_serial8250_port *p = uart->p;
201 u8 timeout = 255;
202
203 serial_write_reg(p, UART_OMAP_MDR1, mdr1_val);
204 udelay(2);
205 serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
206 UART_FCR_CLEAR_RCVR);
207 /*
208 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
209 * TX_FIFO_E bit is 1.
210 */
211 while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) &
212 (UART_LSR_THRE | UART_LSR_DR))) {
213 timeout--;
214 if (!timeout) {
215 /* Should *never* happen. we warn and carry on */
216 dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n",
217 serial_read_reg(p, UART_LSR));
218 break;
219 }
220 udelay(1);
221 }
222}
223
4af4016c 224static void omap_uart_save_context(struct omap_uart_state *uart)
6e81176d 225{
4af4016c
KH		 226 u16 lcr = 0;
227 struct plat_serial8250_port *p = uart->p;
228
229 if (!enable_off_mode)
230 return;
231
232 lcr = serial_read_reg(p, UART_LCR);
233 serial_write_reg(p, UART_LCR, 0xBF);
234 uart->dll = serial_read_reg(p, UART_DLL);
235 uart->dlh = serial_read_reg(p, UART_DLM);
236 serial_write_reg(p, UART_LCR, lcr);
237 uart->ier = serial_read_reg(p, UART_IER);
238 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
239 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
240 uart->wer = serial_read_reg(p, UART_OMAP_WER);
5ade4ff5
G		 241 serial_write_reg(p, UART_LCR, 0x80);
242 uart->mcr = serial_read_reg(p, UART_MCR);
243 serial_write_reg(p, UART_LCR, lcr);
4af4016c
KH		 244
245 uart->context_valid = 1;
246}
247
248static void omap_uart_restore_context(struct omap_uart_state *uart)
249{
250 u16 efr = 0;
251 struct plat_serial8250_port *p = uart->p;
252
253 if (!enable_off_mode)
254 return;
255
256 if (!uart->context_valid)
257 return;
258
259 uart->context_valid = 0;
260
00034509
D		 261 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
262 omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
263 else
264 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
4af4016c
KH		 265 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
266 efr = serial_read_reg(p, UART_EFR);
267 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
268 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
269 serial_write_reg(p, UART_IER, 0x0);
270 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
271 serial_write_reg(p, UART_DLL, uart->dll);
272 serial_write_reg(p, UART_DLM, uart->dlh);
273 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
274 serial_write_reg(p, UART_IER, uart->ier);
5ade4ff5
G		 275 serial_write_reg(p, UART_LCR, 0x80);
276 serial_write_reg(p, UART_MCR, uart->mcr);
4af4016c
KH		 277 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
278 serial_write_reg(p, UART_EFR, efr);
279 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
280 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
281 serial_write_reg(p, UART_OMAP_WER, uart->wer);
282 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
00034509
D		 283 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
284 omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
285 else
286 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
4af4016c
KH		 287}
288#else
289static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
290static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
291#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
292
293static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
294{
295 if (uart->clocked)
296 return;
297
298 clk_enable(uart->ick);
299 clk_enable(uart->fck);
300 uart->clocked = 1;
301 omap_uart_restore_context(uart);
302}
303
304#ifdef CONFIG_PM
305
306static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
307{
308 if (!uart->clocked)
309 return;
310
311 omap_uart_save_context(uart);
312 uart->clocked = 0;
313 clk_disable(uart->ick);
314 clk_disable(uart->fck);
315}
316
fd455ea8
KH		 317static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
318{
319 /* Set wake-enable bit */
320 if (uart->wk_en && uart->wk_mask) {
321 u32 v = __raw_readl(uart->wk_en);
322 v |= uart->wk_mask;
323 __raw_writel(v, uart->wk_en);
324 }
325
326 /* Ensure IOPAD wake-enables are set */
327 if (cpu_is_omap34xx() && uart->padconf) {
328 u16 v = omap_ctrl_readw(uart->padconf);
329 v |= OMAP3_PADCONF_WAKEUPENABLE0;
330 omap_ctrl_writew(v, uart->padconf);
331 }
332}
333
334static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
335{
336 /* Clear wake-enable bit */
337 if (uart->wk_en && uart->wk_mask) {
338 u32 v = __raw_readl(uart->wk_en);
339 v &= ~uart->wk_mask;
340 __raw_writel(v, uart->wk_en);
341 }
342
343 /* Ensure IOPAD wake-enables are cleared */
344 if (cpu_is_omap34xx() && uart->padconf) {
345 u16 v = omap_ctrl_readw(uart->padconf);
346 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
347 omap_ctrl_writew(v, uart->padconf);
348 }
349}
350
4af4016c
KH		 351static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
352 int enable)
353{
354 struct plat_serial8250_port *p = uart->p;
355 u16 sysc;
356
357 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
358 if (enable)
359 sysc |= 0x2 << 3;
360 else
361 sysc |= 0x1 << 3;
362
363 serial_write_reg(p, UART_OMAP_SYSC, sysc);
364}
365
366static void omap_uart_block_sleep(struct omap_uart_state *uart)
367{
368 omap_uart_enable_clocks(uart);
369
370 omap_uart_smart_idle_enable(uart, 0);
371 uart->can_sleep = 0;
ba87a9be
JH		 372 if (uart->timeout)
373 mod_timer(&uart->timer, jiffies + uart->timeout);
374 else
375 del_timer(&uart->timer);
4af4016c
KH		 376}
377
378static void omap_uart_allow_sleep(struct omap_uart_state *uart)
379{
fd455ea8
KH		 380 if (device_may_wakeup(&uart->pdev.dev))
381 omap_uart_enable_wakeup(uart);
382 else
383 omap_uart_disable_wakeup(uart);
384
4af4016c
KH		 385 if (!uart->clocked)
386 return;
387
388 omap_uart_smart_idle_enable(uart, 1);
389 uart->can_sleep = 1;
390 del_timer(&uart->timer);
391}
392
393static void omap_uart_idle_timer(unsigned long data)
394{
395 struct omap_uart_state *uart = (struct omap_uart_state *)data;
396
397 omap_uart_allow_sleep(uart);
398}
399
400void omap_uart_prepare_idle(int num)
401{
402 struct omap_uart_state *uart;
403
404 list_for_each_entry(uart, &uart_list, node) {
405 if (num == uart->num && uart->can_sleep) {
406 omap_uart_disable_clocks(uart);
407 return;
408 }
409 }
410}
411
412void omap_uart_resume_idle(int num)
413{
414 struct omap_uart_state *uart;
415
416 list_for_each_entry(uart, &uart_list, node) {
417 if (num == uart->num) {
418 omap_uart_enable_clocks(uart);
419
420 /* Check for IO pad wakeup */
421 if (cpu_is_omap34xx() && uart->padconf) {
422 u16 p = omap_ctrl_readw(uart->padconf);
423
424 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
425 omap_uart_block_sleep(uart);
6e81176d 426 }
4af4016c
KH		 427
428 /* Check for normal UART wakeup */
429 if (__raw_readl(uart->wk_st) & uart->wk_mask)
430 omap_uart_block_sleep(uart);
4af4016c
KH		 431 return;
432 }
433 }
434}
435
436void omap_uart_prepare_suspend(void)
437{
438 struct omap_uart_state *uart;
439
440 list_for_each_entry(uart, &uart_list, node) {
441 omap_uart_allow_sleep(uart);
442 }
443}
444
445int omap_uart_can_sleep(void)
446{
447 struct omap_uart_state *uart;
448 int can_sleep = 1;
449
450 list_for_each_entry(uart, &uart_list, node) {
451 if (!uart->clocked)
452 continue;
453
454 if (!uart->can_sleep) {
455 can_sleep = 0;
456 continue;
6e81176d 457 }
4af4016c
KH		 458
459 /* This UART can now safely sleep. */
460 omap_uart_allow_sleep(uart);
6e81176d 461 }
4af4016c
KH		 462
463 return can_sleep;
6e81176d
JH		 464}
465
4af4016c
KH		 466/**
467 * omap_uart_interrupt()
468 *
469 * This handler is used only to detect that *any* UART interrupt has
470 * occurred. It does _nothing_ to handle the interrupt. Rather,
471 * any UART interrupt will trigger the inactivity timer so the
472 * UART will not idle or sleep for its timeout period.
473 *
474 **/
475static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
476{
477 struct omap_uart_state *uart = dev_id;
478
479 omap_uart_block_sleep(uart);
480
481 return IRQ_NONE;
482}
483
484static void omap_uart_idle_init(struct omap_uart_state *uart)
485{
4af4016c
KH		 486 struct plat_serial8250_port *p = uart->p;
487 int ret;
488
489 uart->can_sleep = 0;
fd455ea8 490 uart->timeout = DEFAULT_TIMEOUT;
4af4016c
KH		 491 setup_timer(&uart->timer, omap_uart_idle_timer,
492 (unsigned long) uart);
301fe8ee
TL		 493 if (uart->timeout)
494 mod_timer(&uart->timer, jiffies + uart->timeout);
4af4016c
KH		 495 omap_uart_smart_idle_enable(uart, 0);
496
497 if (cpu_is_omap34xx()) {
498 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
499 u32 wk_mask = 0;
500 u32 padconf = 0;
501
502 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
503 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
504 switch (uart->num) {
505 case 0:
506 wk_mask = OMAP3430_ST_UART1_MASK;
507 padconf = 0x182;
508 break;
509 case 1:
510 wk_mask = OMAP3430_ST_UART2_MASK;
511 padconf = 0x17a;
512 break;
513 case 2:
514 wk_mask = OMAP3430_ST_UART3_MASK;
515 padconf = 0x19e;
516 break;
517 }
518 uart->wk_mask = wk_mask;
519 uart->padconf = padconf;
520 } else if (cpu_is_omap24xx()) {
521 u32 wk_mask = 0;
522
523 if (cpu_is_omap2430()) {
524 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
525 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
526 } else if (cpu_is_omap2420()) {
527 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
528 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
529 }
530 switch (uart->num) {
531 case 0:
532 wk_mask = OMAP24XX_ST_UART1_MASK;
533 break;
534 case 1:
535 wk_mask = OMAP24XX_ST_UART2_MASK;
536 break;
537 case 2:
538 wk_mask = OMAP24XX_ST_UART3_MASK;
539 break;
540 }
541 uart->wk_mask = wk_mask;
542 } else {
c54bae1f
NM		 543 uart->wk_en = NULL;
544 uart->wk_st = NULL;
4af4016c
KH		 545 uart->wk_mask = 0;
546 uart->padconf = 0;
547 }
548
c426df87 549 p->irqflags |= IRQF_SHARED;
4af4016c
KH		 550 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
551 "serial idle", (void *)uart);
552 WARN_ON(ret);
553}
554
2466211e
TK		 555void omap_uart_enable_irqs(int enable)
556{
557 int ret;
558 struct omap_uart_state *uart;
559
560 list_for_each_entry(uart, &uart_list, node) {
561 if (enable)
562 ret = request_irq(uart->p->irq, omap_uart_interrupt,
563 IRQF_SHARED, "serial idle", (void *)uart);
564 else
565 free_irq(uart->p->irq, (void *)uart);
566 }
567}
568
fd455ea8
KH		 569static ssize_t sleep_timeout_show(struct device *dev,
570 struct device_attribute *attr,
ba87a9be
JH		 571 char *buf)
572{
fd455ea8
KH		 573 struct platform_device *pdev = container_of(dev,
574 struct platform_device, dev);
575 struct omap_uart_state *uart = container_of(pdev,
576 struct omap_uart_state, pdev);
577
578 return sprintf(buf, "%u\n", uart->timeout / HZ);
ba87a9be
JH		 579}
580
fd455ea8
KH		 581static ssize_t sleep_timeout_store(struct device *dev,
582 struct device_attribute *attr,
ba87a9be
JH		 583 const char *buf, size_t n)
584{
fd455ea8
KH		 585 struct platform_device *pdev = container_of(dev,
586 struct platform_device, dev);
587 struct omap_uart_state *uart = container_of(pdev,
588 struct omap_uart_state, pdev);
ba87a9be
JH		 589 unsigned int value;
590
591 if (sscanf(buf, "%u", &value) != 1) {
10c805eb 592 dev_err(dev, "sleep_timeout_store: Invalid value\n");
ba87a9be
JH		 593 return -EINVAL;
594 }
fd455ea8
KH		 595
596 uart->timeout = value * HZ;
597 if (uart->timeout)
598 mod_timer(&uart->timer, jiffies + uart->timeout);
599 else
600 /* A zero value means disable timeout feature */
601 omap_uart_block_sleep(uart);
602
ba87a9be
JH		 603 return n;
604}
605
bfe6977a
NM		 606static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
607 sleep_timeout_store);
fd455ea8 608#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
4af4016c
KH		 609#else
610static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
fd455ea8 611#define DEV_CREATE_FILE(dev, attr)
4af4016c
KH		 612#endif /* CONFIG_PM */
613
9d30b99f 614static struct omap_uart_state omap_uart[] = {
fd455ea8
KH		 615 {
616 .pdev = {
617 .name = "serial8250",
618 .id = PLAT8250_DEV_PLATFORM,
619 .dev = {
620 .platform_data = serial_platform_data0,
621 },
622 },
623 }, {
624 .pdev = {
625 .name = "serial8250",
626 .id = PLAT8250_DEV_PLATFORM1,
627 .dev = {
628 .platform_data = serial_platform_data1,
629 },
630 },
631 }, {
632 .pdev = {
633 .name = "serial8250",
634 .id = PLAT8250_DEV_PLATFORM2,
635 .dev = {
636 .platform_data = serial_platform_data2,
637 },
638 },
2aa57be2 639 },
a3a9b36e 640#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
0e3eaadf
SS		 641 {
642 .pdev = {
643 .name = "serial8250",
61f04ee8 644 .id = 3,
0e3eaadf
SS		 645 .dev = {
646 .platform_data = serial_platform_data3,
647 },
648 },
649 },
650#endif
2aa57be2
VP		 651};
652
ce13d471 653/*
654 * Override the default 8250 read handler: mem_serial_in()
655 * Empty RX fifo read causes an abort on omap3630 and omap4
656 * This function makes sure that an empty rx fifo is not read on these silicons
657 * (OMAP1/2/3430 are not affected)
658 */
659static unsigned int serial_in_override(struct uart_port *up, int offset)
660{
661 if (UART_RX == offset) {
662 unsigned int lsr;
9230372a 663 lsr = __serial_read_reg(up, UART_LSR);
ce13d471 664 if (!(lsr & UART_LSR_DR))
665 return -EPERM;
666 }
9230372a
AS		 667
668 return __serial_read_reg(up, offset);
ce13d471 669}
670
e03d37d8
SS		 671static void serial_out_override(struct uart_port *up, int offset, int value)
672{
673 unsigned int status, tmout = 10000;
674
675 status = __serial_read_reg(up, UART_LSR);
676 while (!(status & UART_LSR_THRE)) {
677 /* Wait up to 10ms for the character(s) to be sent. */
678 if (--tmout == 0)
679 break;
680 udelay(1);
681 status = __serial_read_reg(up, UART_LSR);
682 }
683 __serial_write_reg(up, offset, value);
684}
b3c6df3a 685void __init omap_serial_early_init(void)
1dbae815 686{
21b90340 687 int i, nr_ports;
6e81176d 688 char name[16];
1dbae815 689
21b90340
TW		 690 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
691 nr_ports = 3;
692 else
693 nr_ports = ARRAY_SIZE(omap_uart);
694
1dbae815
TL		 695 /*
696 * Make sure the serial ports are muxed on at this point.
697 * You have to mux them off in device drivers later on
698 * if not needed.
699 */
700
21b90340 701 for (i = 0; i < nr_ports; i++) {
4af4016c 702 struct omap_uart_state *uart = &omap_uart[i];
fd455ea8
KH		 703 struct platform_device *pdev = &uart->pdev;
704 struct device *dev = &pdev->dev;
705 struct plat_serial8250_port *p = dev->platform_data;
1dbae815 706
e88d556d
SA		 707 /* Don't map zero-based physical address */
708 if (p->mapbase == 0) {
10c805eb
SA		 709 dev_warn(dev, "no physical address for uart#%d,"
710 " so skipping early_init...\n", i);
e88d556d
SA		 711 continue;
712 }
84f90c9c
TL		 713 /*
714 * Module 4KB + L4 interconnect 4KB
715 * Static mapping, never released
716 */
717 p->membase = ioremap(p->mapbase, SZ_8K);
718 if (!p->membase) {
10c805eb 719 dev_err(dev, "ioremap failed for uart%i\n", i + 1);
84f90c9c
TL		 720 continue;
721 }
722
21b90340 723 sprintf(name, "uart%d_ick", i + 1);
4af4016c
KH		 724 uart->ick = clk_get(NULL, name);
725 if (IS_ERR(uart->ick)) {
10c805eb 726 dev_err(dev, "Could not get uart%d_ick\n", i + 1);
4af4016c
KH		 727 uart->ick = NULL;
728 }
6e81176d
JH		 729
730 sprintf(name, "uart%d_fck", i+1);
4af4016c
KH		 731 uart->fck = clk_get(NULL, name);
732 if (IS_ERR(uart->fck)) {
10c805eb 733 dev_err(dev, "Could not get uart%d_fck\n", i + 1);
4af4016c
KH		 734 uart->fck = NULL;
735 }
736
aae290fb
SS		 737 /* FIXME: Remove this once the clkdev is ready */
738 if (!cpu_is_omap44xx()) {
739 if (!uart->ick || !uart->fck)
740 continue;
741 }
4af4016c
KH		 742
743 uart->num = i;
744 p->private_data = uart;
745 uart->p = p;
1dbae815 746
4789998a
KH		 747 if (cpu_is_omap44xx())
748 p->irq += 32;
b3c6df3a
PW		 749 }
750}
751
f62349ee
MW		 752/**
753 * omap_serial_init_port() - initialize single serial port
754 * @port: serial port number (0-3)
755 *
756 * This function initialies serial driver for given @port only.
757 * Platforms can call this function instead of omap_serial_init()
758 * if they don't plan to use all available UARTs as serial ports.
759 *
760 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
761 * use only one of the two.
762 */
763void __init omap_serial_init_port(int port)
b3c6df3a 764{
f62349ee
MW		 765 struct omap_uart_state *uart;
766 struct platform_device *pdev;
767 struct device *dev;
b3c6df3a 768
f62349ee
MW		 769 BUG_ON(port < 0);
770 BUG_ON(port >= ARRAY_SIZE(omap_uart));
b3c6df3a 771
f62349ee
MW		 772 uart = &omap_uart[port];
773 pdev = &uart->pdev;
774 dev = &pdev->dev;
970a724d 775
e88d556d
SA		 776 /* Don't proceed if there's no clocks available */
777 if (unlikely(!uart->ick || !uart->fck)) {
778 WARN(1, "%s: can't init uart%d, no clocks available\n",
779 kobject_name(&dev->kobj), port);
780 return;
781 }
782
f2eeeae0
MW		 783 omap_uart_enable_clocks(uart);
784
f62349ee
MW		 785 omap_uart_reset(uart);
786 omap_uart_idle_init(uart);
787
f2eeeae0
MW		 788 list_add_tail(&uart->node, &uart_list);
789
f62349ee
MW		 790 if (WARN_ON(platform_device_register(pdev)))
791 return;
792
793 if ((cpu_is_omap34xx() && uart->padconf) ||
794 (uart->wk_en && uart->wk_mask)) {
795 device_init_wakeup(dev, true);
796 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
fd455ea8 797 }
f62349ee 798
30e53bcc 799 /*
800 * omap44xx: Never read empty UART fifo
801 * omap3xxx: Never read empty UART fifo on UARTs
802 * with IP rev >=0x52
803 */
5a927b36
NM		 804 if (cpu_is_omap44xx())
805 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
806 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
807 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
808 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
809
810 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
30e53bcc 811 uart->p->serial_in = serial_in_override;
e03d37d8
SS		 812 uart->p->serial_out = serial_out_override;
813 }
00034509
D		 814
815 /* Enable the MDR1 errata for OMAP3 */
816 if (cpu_is_omap34xx())
817 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
f62349ee
MW		 818}
819
820/**
821 * omap_serial_init() - intialize all supported serial ports
822 *
823 * Initializes all available UARTs as serial ports. Platforms
824 * can call this function when they want to have default behaviour
825 * for serial ports (e.g initialize them all as serial ports).
826 */
827void __init omap_serial_init(void)
828{
a3a9b36e
TL		 829 int i, nr_ports;
830
831 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
832 nr_ports = 3;
833 else
834 nr_ports = ARRAY_SIZE(omap_uart);
f62349ee 835
a3a9b36e 836 for (i = 0; i < nr_ports; i++)
f62349ee 837 omap_serial_init_port(i);
1dbae815 838}
Linux kernel - Deliverables
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