[deliverable/linux.git] / arch / arm / mach-omap2 / serial.c

/*
 * arch/arm/mach-omap2/serial.c
 *
 * OMAP2 serial support.
 *
 * Copyright (C) 2005-2008 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * Major rework for PM support by Kevin Hilman
 *
 * Based off of arch/arm/mach-omap/omap1/serial.c
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/console.h>

#include <plat/omap-serial.h>
#include "common.h"
#include <plat/board.h>
#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>

#include "prm2xxx_3xxx.h"
#include "pm.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "control.h"
#include "mux.h"

#define UART_OMAP_WER		0x17	/* Wake-up enable register */

#define UART_ERRATA_i202_MDR1_ACCESS	(0x1 << 1)

/*
 * NOTE: By default the serial timeout is disabled as it causes lost characters
 * over the serial ports. This means that the UART clocks will stay on until
 * disabled via sysfs. This also causes that any deeper omap sleep states are
 * blocked. 
 */
#define DEFAULT_TIMEOUT 0

#define MAX_UART_HWMOD_NAME_LEN		16

struct omap_uart_state {
	int num;
	int can_sleep;

	void __iomem *wk_st;
	void __iomem *wk_en;
	u32 wk_mask;
	u32 padconf;
	u32 dma_enabled;

	int clocked;

	int regshift;
	void __iomem *membase;
	resource_size_t mapbase;

	struct list_head node;
	struct omap_hwmod *oh;
	struct platform_device *pdev;

	u32 errata;
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
	int context_valid;

	/* Registers to be saved/restored for OFF-mode */
	u16 dll;
	u16 dlh;
	u16 ier;
	u16 sysc;
	u16 scr;
	u16 wer;
	u16 mcr;
#endif
};

static LIST_HEAD(uart_list);
static u8 num_uarts;

static inline unsigned int __serial_read_reg(struct uart_port *up,
					     int offset)
{
	offset <<= up->regshift;
	return (unsigned int)__raw_readb(up->membase + offset);
}

static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
					   int offset)
{
	offset <<= uart->regshift;
	return (unsigned int)__raw_readb(uart->membase + offset);
}

static inline void __serial_write_reg(struct uart_port *up, int offset,
		int value)
{
	offset <<= up->regshift;
	__raw_writeb(value, up->membase + offset);
}

static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
				    int value)
{
	offset <<= uart->regshift;
	__raw_writeb(value, uart->membase + offset);
}

/*
 * Internal UARTs need to be initialized for the 8250 autoconfig to work
 * properly. Note that the TX watermark initialization may not be needed
 * once the 8250.c watermark handling code is merged.
 */

static inline void __init omap_uart_reset(struct omap_uart_state *uart)
{
	serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
	serial_write_reg(uart, UART_OMAP_SCR, 0x08);
	serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
}

#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)

/*
 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
 * The access to uart register after MDR1 Access
 * causes UART to corrupt data.
 *
 * Need a delay =
 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 * give 10 times as much
 */
static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
		u8 fcr_val)
{
	u8 timeout = 255;

	serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
	udelay(2);
	serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
			UART_FCR_CLEAR_RCVR);
	/*
	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
	 * TX_FIFO_E bit is 1.
	 */
	while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
				(UART_LSR_THRE | UART_LSR_DR))) {
		timeout--;
		if (!timeout) {
			/* Should *never* happen. we warn and carry on */
			dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
			serial_read_reg(uart, UART_LSR));
			break;
		}
		udelay(1);
	}
}

static void omap_uart_save_context(struct omap_uart_state *uart)
{
	u16 lcr = 0;

	if (!enable_off_mode)
		return;

	lcr = serial_read_reg(uart, UART_LCR);
	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
	uart->dll = serial_read_reg(uart, UART_DLL);
	uart->dlh = serial_read_reg(uart, UART_DLM);
	serial_write_reg(uart, UART_LCR, lcr);
	uart->ier = serial_read_reg(uart, UART_IER);
	uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
	uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
	uart->wer = serial_read_reg(uart, UART_OMAP_WER);
	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
	uart->mcr = serial_read_reg(uart, UART_MCR);
	serial_write_reg(uart, UART_LCR, lcr);

	uart->context_valid = 1;
}

static void omap_uart_restore_context(struct omap_uart_state *uart)
{
	u16 efr = 0;

	if (!enable_off_mode)
		return;

	if (!uart->context_valid)
		return;

	uart->context_valid = 0;

	if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
		omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
	else
		serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);

	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
	efr = serial_read_reg(uart, UART_EFR);
	serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
	serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
	serial_write_reg(uart, UART_IER, 0x0);
	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
	serial_write_reg(uart, UART_DLL, uart->dll);
	serial_write_reg(uart, UART_DLM, uart->dlh);
	serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
	serial_write_reg(uart, UART_IER, uart->ier);
	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
	serial_write_reg(uart, UART_MCR, uart->mcr);
	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
	serial_write_reg(uart, UART_EFR, efr);
	serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
	serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
	serial_write_reg(uart, UART_OMAP_WER, uart->wer);
	serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);

	if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
		omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
	else
		/* UART 16x mode */
		serial_write_reg(uart, UART_OMAP_MDR1,
				UART_OMAP_MDR1_16X_MODE);
}
#else
static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */

static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
{
	if (uart->clocked)
		return;

	omap_device_enable(uart->pdev);
	uart->clocked = 1;
	omap_uart_restore_context(uart);
}

#ifdef CONFIG_PM

static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
{
	if (!uart->clocked)
		return;

	omap_uart_save_context(uart);
	uart->clocked = 0;
	omap_device_idle(uart->pdev);
}

static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
{
	/* Set wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v |= uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}

	/* Ensure IOPAD wake-enables are set */
	if (cpu_is_omap34xx() && uart->padconf) {
		u16 v = omap_ctrl_readw(uart->padconf);
		v |= OMAP3_PADCONF_WAKEUPENABLE0;
		omap_ctrl_writew(v, uart->padconf);
	}
}

static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
{
	/* Clear wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v &= ~uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}

	/* Ensure IOPAD wake-enables are cleared */
	if (cpu_is_omap34xx() && uart->padconf) {
		u16 v = omap_ctrl_readw(uart->padconf);
		v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
		omap_ctrl_writew(v, uart->padconf);
	}
}

static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
					       int enable)
{
	u8 idlemode;

	if (enable) {
		/**
		 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
		 * in Smartidle Mode When Configured for DMA Operations.
		 */
		if (uart->dma_enabled)
			idlemode = HWMOD_IDLEMODE_FORCE;
		else
			idlemode = HWMOD_IDLEMODE_SMART;
	} else {
		idlemode = HWMOD_IDLEMODE_NO;
	}

	omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
}

static void omap_uart_block_sleep(struct omap_uart_state *uart)
{
	omap_uart_enable_clocks(uart);

	omap_uart_smart_idle_enable(uart, 0);
	uart->can_sleep = 0;
}

int omap_uart_can_sleep(void)
{
	struct omap_uart_state *uart;
	int can_sleep = 1;

	list_for_each_entry(uart, &uart_list, node) {
		if (!uart->clocked)
			continue;

		if (!uart->can_sleep) {
			can_sleep = 0;
			continue;
		}

		/* This UART can now safely sleep. */
		omap_uart_allow_sleep(uart);
	}

	return can_sleep;
}

static void omap_uart_idle_init(struct omap_uart_state *uart)
{
	int ret;

	uart->can_sleep = 0;
	omap_uart_smart_idle_enable(uart, 0);

	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) {
		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
		u32 wk_mask = 0;
		u32 padconf = 0;

		/* XXX These PRM accesses do not belong here */
		uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
		uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
		switch (uart->num) {
		case 0:
			wk_mask = OMAP3430_ST_UART1_MASK;
			padconf = 0x182;
			break;
		case 1:
			wk_mask = OMAP3430_ST_UART2_MASK;
			padconf = 0x17a;
			break;
		case 2:
			wk_mask = OMAP3430_ST_UART3_MASK;
			padconf = 0x19e;
			break;
		case 3:
			wk_mask = OMAP3630_ST_UART4_MASK;
			padconf = 0x0d2;
			break;
		}
		uart->wk_mask = wk_mask;
		uart->padconf = padconf;
	} else if (cpu_is_omap24xx()) {
		u32 wk_mask = 0;
		u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;

		switch (uart->num) {
		case 0:
			wk_mask = OMAP24XX_ST_UART1_MASK;
			break;
		case 1:
			wk_mask = OMAP24XX_ST_UART2_MASK;
			break;
		case 2:
			wk_en = OMAP24XX_PM_WKEN2;
			wk_st = OMAP24XX_PM_WKST2;
			wk_mask = OMAP24XX_ST_UART3_MASK;
			break;
		}
		uart->wk_mask = wk_mask;
		if (cpu_is_omap2430()) {
			uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
			uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
		} else if (cpu_is_omap2420()) {
			uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
			uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
		}
	} else {
		uart->wk_en = NULL;
		uart->wk_st = NULL;
		uart->wk_mask = 0;
		uart->padconf = 0;
	}
}

#else
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
static void omap_uart_block_sleep(struct omap_uart_state *uart)
{
	/* Needed to enable UART clocks when built without CONFIG_PM */
	omap_uart_enable_clocks(uart);
}
#endif /* CONFIG_PM */

static int __init omap_serial_early_init(void)
{
	int i = 0;

	do {
		char oh_name[MAX_UART_HWMOD_NAME_LEN];
		struct omap_hwmod *oh;
		struct omap_uart_state *uart;

		snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
			 "uart%d", i + 1);
		oh = omap_hwmod_lookup(oh_name);
		if (!oh)
			break;

		uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
		if (WARN_ON(!uart))
			return -ENODEV;

		uart->oh = oh;
		uart->num = i++;
		list_add_tail(&uart->node, &uart_list);
		num_uarts++;

		/*
		 * NOTE: omap_hwmod_setup*() has not yet been called,
		 *       so no hwmod functions will work yet.
		 */

		/*
		 * During UART early init, device need to be probed
		 * to determine SoC specific init before omap_device
		 * is ready.  Therefore, don't allow idle here
		 */
		uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
	} while (1);

	return 0;
}
core_initcall(omap_serial_early_init);

/**
 * omap_serial_init_port() - initialize single serial port
 * @bdata: port specific board data pointer
 *
 * This function initialies serial driver for given port only.
 * Platforms can call this function instead of omap_serial_init()
 * if they don't plan to use all available UARTs as serial ports.
 *
 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 * use only one of the two.
 */
void __init omap_serial_init_port(struct omap_board_data *bdata)
{
	struct omap_uart_state *uart;
	struct omap_hwmod *oh;
	struct platform_device *pdev;
	void *pdata = NULL;
	u32 pdata_size = 0;
	char *name;
	struct omap_uart_port_info omap_up;

	if (WARN_ON(!bdata))
		return;
	if (WARN_ON(bdata->id < 0))
		return;
	if (WARN_ON(bdata->id >= num_uarts))
		return;

	list_for_each_entry(uart, &uart_list, node)
		if (bdata->id == uart->num)
			break;

	oh = uart->oh;
	uart->dma_enabled = 0;
	name = DRIVER_NAME;

	omap_up.dma_enabled = uart->dma_enabled;
	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
	omap_up.mapbase = oh->slaves[0]->addr->pa_start;
	omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
	omap_up.flags = UPF_BOOT_AUTOCONF;

	pdata = &omap_up;
	pdata_size = sizeof(struct omap_uart_port_info);

	if (WARN_ON(!oh))
		return;

	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
				 NULL, 0, false);
	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
	     name, oh->name);

	omap_device_disable_idle_on_suspend(pdev);
	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);

	uart->regshift = 2;
	uart->mapbase = oh->slaves[0]->addr->pa_start;
	uart->membase = omap_hwmod_get_mpu_rt_va(oh);
	uart->pdev = pdev;

	oh->dev_attr = uart;

	console_lock(); /* in case the earlycon is on the UART */

	/*
	 * Because of early UART probing, UART did not get idled
	 * on init.  Now that omap_device is ready, ensure full idle
	 * before doing omap_device_enable().
	 */
	omap_hwmod_idle(uart->oh);

	omap_device_enable(uart->pdev);
	omap_uart_idle_init(uart);
	omap_uart_reset(uart);
	omap_hwmod_enable_wakeup(uart->oh);
	omap_device_idle(uart->pdev);

	omap_uart_block_sleep(uart);
	console_unlock();

	if ((cpu_is_omap34xx() && uart->padconf) ||
	    (uart->wk_en && uart->wk_mask))
		device_init_wakeup(&pdev->dev, true);

	/* Enable the MDR1 errata for OMAP3 */
	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx()))
		uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
}

/**
 * omap_serial_init() - initialize all supported serial ports
 *
 * Initializes all available UARTs as serial ports. Platforms
 * can call this function when they want to have default behaviour
 * for serial ports (e.g initialize them all as serial ports).
 */
void __init omap_serial_init(void)
{
	struct omap_uart_state *uart;
	struct omap_board_data bdata;

	list_for_each_entry(uart, &uart_list, node) {
		bdata.id = uart->num;
		bdata.flags = 0;
		bdata.pads = NULL;
		bdata.pads_cnt = 0;
		omap_serial_init_port(&bdata);

	}
}
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* arch/arm/mach-omap2/serial.c
1dbae815 TL	3	*
	4	* OMAP2 serial support.
	5	*
6e81176d	6	* Copyright (C) 2005-2008 Nokia Corporation
1dbae815 TL	7	* Author: Paul Mundt <paul.mundt@nokia.com>
1dbae815 TL	8	*
4af4016c KH	9	* Major rework for PM support by Kevin Hilman
4af4016c KH	10	*
1dbae815 TL	11	* Based off of arch/arm/mach-omap/omap1/serial.c
1dbae815 TL	12	*
44169075 SS	13	* Copyright (C) 2009 Texas Instruments
	14	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
	15	*
1dbae815 TL	16	* This file is subject to the terms and conditions of the GNU General Public
	17	* License. See the file "COPYING" in the main directory of this archive
	18	* for more details.
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
f8ce2547	22	#include <linux/clk.h>
fced80c7	23	#include <linux/io.h>
e03d37d8	24	#include <linux/delay.h>
6f251e9d KH	25	#include <linux/platform_device.h>
6f251e9d KH	26	#include <linux/slab.h>
3244fcd2	27	#include <linux/pm_runtime.h>
0d8e2d0d	28	#include <linux/console.h>
6f251e9d	29
6f251e9d	30	#include <plat/omap-serial.h>
4e65331c	31	#include "common.h"
ce491cf8	32	#include <plat/board.h>
6f251e9d KH	33	#include <plat/dma.h>
	34	#include <plat/omap_hwmod.h>
	35	#include <plat/omap_device.h>
4af4016c	36
59fb659b	37	#include "prm2xxx_3xxx.h"
4af4016c	38	#include "pm.h"
59fb659b	39	#include "cm2xxx_3xxx.h"
4af4016c	40	#include "prm-regbits-34xx.h"
4814ced5	41	#include "control.h"
40e44399	42	#include "mux.h"
4af4016c KH	43
	44	#define UART_OMAP_WER 0x17 /* Wake-up enable register */
	45
00034509	46	#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
5a927b36	47
301fe8ee TL	48	/*
	49	* NOTE: By default the serial timeout is disabled as it causes lost characters
	50	* over the serial ports. This means that the UART clocks will stay on until
	51	* disabled via sysfs. This also causes that any deeper omap sleep states are
	52	* blocked.
	53	*/
	54	#define DEFAULT_TIMEOUT 0
4af4016c	55
6f251e9d KH	56	#define MAX_UART_HWMOD_NAME_LEN 16
6f251e9d KH	57
4af4016c KH	58	struct omap_uart_state {
	59	int num;
	60	int can_sleep;
4af4016c KH	61
	62	void __iomem *wk_st;
	63	void __iomem *wk_en;
	64	u32 wk_mask;
	65	u32 padconf;
6f251e9d	66	u32 dma_enabled;
4af4016c	67
4af4016c KH	68	int clocked;
4af4016c KH	69
6f251e9d	70	int regshift;
6f251e9d KH	71	void __iomem *membase;
	72	resource_size_t mapbase;
	73
4af4016c	74	struct list_head node;
6f251e9d KH	75	struct omap_hwmod *oh;
6f251e9d KH	76	struct platform_device *pdev;
1dbae815	77
5a927b36	78	u32 errata;
4af4016c KH	79	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
	80	int context_valid;
	81
	82	/* Registers to be saved/restored for OFF-mode */
	83	u16 dll;
	84	u16 dlh;
	85	u16 ier;
	86	u16 sysc;
	87	u16 scr;
	88	u16 wer;
5ade4ff5	89	u16 mcr;
4af4016c KH	90	#endif
	91	};
	92
4af4016c	93	static LIST_HEAD(uart_list);
6f251e9d	94	static u8 num_uarts;
1dbae815	95
9230372a	96	static inline unsigned int __serial_read_reg(struct uart_port *up,
6f251e9d	97	int offset)
9230372a AS	98	{
	99	offset <<= up->regshift;
	100	return (unsigned int)__raw_readb(up->membase + offset);
	101	}
	102
6f251e9d	103	static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
1dbae815 TL	104	int offset)
1dbae815 TL	105	{
6f251e9d KH	106	offset <<= uart->regshift;
6f251e9d KH	107	return (unsigned int)__raw_readb(uart->membase + offset);
1dbae815 TL	108	}
1dbae815 TL	109
e03d37d8 SS	110	static inline void __serial_write_reg(struct uart_port *up, int offset,
	111	int value)
	112	{
	113	offset <<= up->regshift;
	114	__raw_writeb(value, up->membase + offset);
	115	}
	116
6f251e9d	117	static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
1dbae815 TL	118	int value)
1dbae815 TL	119	{
6f251e9d KH	120	offset <<= uart->regshift;
6f251e9d KH	121	__raw_writeb(value, uart->membase + offset);
1dbae815 TL	122	}
	123
	124	/*
	125	* Internal UARTs need to be initialized for the 8250 autoconfig to work
	126	* properly. Note that the TX watermark initialization may not be needed
	127	* once the 8250.c watermark handling code is merged.
	128	*/
6f251e9d	129
4af4016c	130	static inline void __init omap_uart_reset(struct omap_uart_state *uart)
1dbae815	131	{
498cb951	132	serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
6f251e9d	133	serial_write_reg(uart, UART_OMAP_SCR, 0x08);
498cb951	134	serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
1dbae815 TL	135	}
1dbae815 TL	136
4af4016c KH	137	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
4af4016c KH	138
00034509 D	139	/*
	140	* Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
	141	* The access to uart register after MDR1 Access
	142	* causes UART to corrupt data.
	143	*
	144	* Need a delay =
	145	* 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
	146	* give 10 times as much
	147	*/
	148	static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
	149	u8 fcr_val)
	150	{
00034509 D	151	u8 timeout = 255;
00034509 D	152
6f251e9d	153	serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
00034509	154	udelay(2);
6f251e9d	155	serial_write_reg(uart, UART_FCR, fcr_val \| UART_FCR_CLEAR_XMIT \|
00034509 D	156	UART_FCR_CLEAR_RCVR);
	157	/*
	158	* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
	159	* TX_FIFO_E bit is 1.
	160	*/
6f251e9d	161	while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
00034509 D	162	(UART_LSR_THRE \| UART_LSR_DR))) {
	163	timeout--;
	164	if (!timeout) {
	165	/* Should never happen. we warn and carry on */
6f251e9d KH	166	dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
6f251e9d KH	167	serial_read_reg(uart, UART_LSR));
00034509 D	168	break;
	169	}
	170	udelay(1);
	171	}
	172	}
	173
4af4016c	174	static void omap_uart_save_context(struct omap_uart_state *uart)
6e81176d	175	{
4af4016c	176	u16 lcr = 0;
4af4016c KH	177
	178	if (!enable_off_mode)
	179	return;
	180
6f251e9d	181	lcr = serial_read_reg(uart, UART_LCR);
662b083a	182	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
6f251e9d KH	183	uart->dll = serial_read_reg(uart, UART_DLL);
	184	uart->dlh = serial_read_reg(uart, UART_DLM);
	185	serial_write_reg(uart, UART_LCR, lcr);
	186	uart->ier = serial_read_reg(uart, UART_IER);
	187	uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
	188	uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
	189	uart->wer = serial_read_reg(uart, UART_OMAP_WER);
662b083a	190	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
6f251e9d KH	191	uart->mcr = serial_read_reg(uart, UART_MCR);
6f251e9d KH	192	serial_write_reg(uart, UART_LCR, lcr);
4af4016c KH	193
	194	uart->context_valid = 1;
	195	}
	196
	197	static void omap_uart_restore_context(struct omap_uart_state *uart)
	198	{
	199	u16 efr = 0;
4af4016c KH	200
	201	if (!enable_off_mode)
	202	return;
	203
	204	if (!uart->context_valid)
	205	return;
	206
	207	uart->context_valid = 0;
	208
00034509	209	if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
498cb951	210	omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
00034509	211	else
498cb951 AE	212	serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
498cb951 AE	213
662b083a	214	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
6f251e9d KH	215	efr = serial_read_reg(uart, UART_EFR);
	216	serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
	217	serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
	218	serial_write_reg(uart, UART_IER, 0x0);
662b083a	219	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
6f251e9d KH	220	serial_write_reg(uart, UART_DLL, uart->dll);
	221	serial_write_reg(uart, UART_DLM, uart->dlh);
	222	serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
	223	serial_write_reg(uart, UART_IER, uart->ier);
662b083a	224	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
6f251e9d	225	serial_write_reg(uart, UART_MCR, uart->mcr);
662b083a	226	serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
6f251e9d KH	227	serial_write_reg(uart, UART_EFR, efr);
	228	serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
	229	serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
	230	serial_write_reg(uart, UART_OMAP_WER, uart->wer);
	231	serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
498cb951	232
00034509	233	if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
498cb951	234	omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
00034509	235	else
6f251e9d	236	/* UART 16x mode */
498cb951 AE	237	serial_write_reg(uart, UART_OMAP_MDR1,
498cb951 AE	238	UART_OMAP_MDR1_16X_MODE);
4af4016c KH	239	}
	240	#else
	241	static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
	242	static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
	243	#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
	244
	245	static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
	246	{
	247	if (uart->clocked)
	248	return;
	249
6f251e9d	250	omap_device_enable(uart->pdev);
4af4016c KH	251	uart->clocked = 1;
	252	omap_uart_restore_context(uart);
	253	}
	254
	255	#ifdef CONFIG_PM
	256
	257	static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
	258	{
	259	if (!uart->clocked)
	260	return;
	261
	262	omap_uart_save_context(uart);
	263	uart->clocked = 0;
6f251e9d	264	omap_device_idle(uart->pdev);
4af4016c KH	265	}
4af4016c KH	266
fd455ea8 KH	267	static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
	268	{
	269	/* Set wake-enable bit */
	270	if (uart->wk_en && uart->wk_mask) {
	271	u32 v = __raw_readl(uart->wk_en);
	272	v \|= uart->wk_mask;
	273	__raw_writel(v, uart->wk_en);
	274	}
	275
	276	/* Ensure IOPAD wake-enables are set */
	277	if (cpu_is_omap34xx() && uart->padconf) {
	278	u16 v = omap_ctrl_readw(uart->padconf);
	279	v \|= OMAP3_PADCONF_WAKEUPENABLE0;
	280	omap_ctrl_writew(v, uart->padconf);
	281	}
	282	}
	283
	284	static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
	285	{
	286	/* Clear wake-enable bit */
	287	if (uart->wk_en && uart->wk_mask) {
	288	u32 v = __raw_readl(uart->wk_en);
	289	v &= ~uart->wk_mask;
	290	__raw_writel(v, uart->wk_en);
	291	}
	292
	293	/* Ensure IOPAD wake-enables are cleared */
	294	if (cpu_is_omap34xx() && uart->padconf) {
	295	u16 v = omap_ctrl_readw(uart->padconf);
	296	v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
	297	omap_ctrl_writew(v, uart->padconf);
	298	}
	299	}
	300
4af4016c	301	static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
6f251e9d	302	int enable)
4af4016c	303	{
6f251e9d	304	u8 idlemode;
4af4016c	305
6f251e9d KH	306	if (enable) {
	307	/**
	308	* Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
	309	* in Smartidle Mode When Configured for DMA Operations.
	310	*/
	311	if (uart->dma_enabled)
	312	idlemode = HWMOD_IDLEMODE_FORCE;
	313	else
	314	idlemode = HWMOD_IDLEMODE_SMART;
	315	} else {
	316	idlemode = HWMOD_IDLEMODE_NO;
	317	}
4af4016c	318
6f251e9d	319	omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
4af4016c KH	320	}
	321
	322	static void omap_uart_block_sleep(struct omap_uart_state *uart)
	323	{
	324	omap_uart_enable_clocks(uart);
	325
	326	omap_uart_smart_idle_enable(uart, 0);
	327	uart->can_sleep = 0;
4af4016c KH	328	}
4af4016c KH	329
4af4016c KH	330	int omap_uart_can_sleep(void)
	331	{
	332	struct omap_uart_state *uart;
	333	int can_sleep = 1;
	334
	335	list_for_each_entry(uart, &uart_list, node) {
	336	if (!uart->clocked)
	337	continue;
	338
	339	if (!uart->can_sleep) {
	340	can_sleep = 0;
	341	continue;
6e81176d	342	}
4af4016c KH	343
	344	/* This UART can now safely sleep. */
	345	omap_uart_allow_sleep(uart);
6e81176d	346	}
4af4016c KH	347
4af4016c KH	348	return can_sleep;
6e81176d JH	349	}
6e81176d JH	350
4af4016c KH	351	static void omap_uart_idle_init(struct omap_uart_state *uart)
4af4016c KH	352	{
4af4016c KH	353	int ret;
	354
	355	uart->can_sleep = 0;
4af4016c KH	356	omap_uart_smart_idle_enable(uart, 0);
4af4016c KH	357
a920360f	358	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() \|\| cpu_is_am33xx())) {
52663aea	359	u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
4af4016c KH	360	u32 wk_mask = 0;
	361	u32 padconf = 0;
	362
c4d7e58f	363	/* XXX These PRM accesses do not belong here */
4af4016c KH	364	uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
	365	uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
	366	switch (uart->num) {
	367	case 0:
	368	wk_mask = OMAP3430_ST_UART1_MASK;
	369	padconf = 0x182;
	370	break;
	371	case 1:
	372	wk_mask = OMAP3430_ST_UART2_MASK;
	373	padconf = 0x17a;
	374	break;
	375	case 2:
	376	wk_mask = OMAP3430_ST_UART3_MASK;
	377	padconf = 0x19e;
	378	break;
52663aea G	379	case 3:
	380	wk_mask = OMAP3630_ST_UART4_MASK;
	381	padconf = 0x0d2;
	382	break;
4af4016c KH	383	}
	384	uart->wk_mask = wk_mask;
	385	uart->padconf = padconf;
	386	} else if (cpu_is_omap24xx()) {
	387	u32 wk_mask = 0;
cb74f022	388	u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
4af4016c	389
4af4016c KH	390	switch (uart->num) {
	391	case 0:
	392	wk_mask = OMAP24XX_ST_UART1_MASK;
	393	break;
	394	case 1:
	395	wk_mask = OMAP24XX_ST_UART2_MASK;
	396	break;
	397	case 2:
cb74f022 KH	398	wk_en = OMAP24XX_PM_WKEN2;
cb74f022 KH	399	wk_st = OMAP24XX_PM_WKST2;
4af4016c KH	400	wk_mask = OMAP24XX_ST_UART3_MASK;
	401	break;
	402	}
	403	uart->wk_mask = wk_mask;
cb74f022 KH	404	if (cpu_is_omap2430()) {
	405	uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
	406	uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
	407	} else if (cpu_is_omap2420()) {
	408	uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
	409	uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
	410	}
4af4016c	411	} else {
c54bae1f NM	412	uart->wk_en = NULL;
c54bae1f NM	413	uart->wk_st = NULL;
4af4016c KH	414	uart->wk_mask = 0;
	415	uart->padconf = 0;
	416	}
ba87a9be JH	417	}
ba87a9be JH	418
4af4016c KH	419	#else
4af4016c KH	420	static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
a1b04cc1 SS	421	static void omap_uart_block_sleep(struct omap_uart_state *uart)
	422	{
	423	/* Needed to enable UART clocks when built without CONFIG_PM */
	424	omap_uart_enable_clocks(uart);
	425	}
4af4016c KH	426	#endif /* CONFIG_PM */
4af4016c KH	427
3e16f925	428	static int __init omap_serial_early_init(void)
1dbae815	429	{
6f251e9d	430	int i = 0;
1dbae815	431
6f251e9d KH	432	do {
	433	char oh_name[MAX_UART_HWMOD_NAME_LEN];
	434	struct omap_hwmod *oh;
	435	struct omap_uart_state *uart;
21b90340	436
6f251e9d KH	437	snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
	438	"uart%d", i + 1);
	439	oh = omap_hwmod_lookup(oh_name);
	440	if (!oh)
	441	break;
	442
	443	uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
	444	if (WARN_ON(!uart))
3e16f925	445	return -ENODEV;
1dbae815	446
6f251e9d KH	447	uart->oh = oh;
	448	uart->num = i++;
	449	list_add_tail(&uart->node, &uart_list);
	450	num_uarts++;
1dbae815	451
84f90c9c	452	/*
550c8092	453	* NOTE: omap_hwmod_setup*() has not yet been called,
6f251e9d	454	* so no hwmod functions will work yet.
84f90c9c	455	*/
6e81176d	456
6f251e9d KH	457	/*
	458	* During UART early init, device need to be probed
	459	* to determine SoC specific init before omap_device
	460	* is ready. Therefore, don't allow idle here
	461	*/
	462	uart->oh->flags \|= HWMOD_INIT_NO_IDLE \| HWMOD_INIT_NO_RESET;
	463	} while (1);
3e16f925 TL	464
3e16f925 TL	465	return 0;
b3c6df3a	466	}
3e16f925	467	core_initcall(omap_serial_early_init);
b3c6df3a	468
f62349ee MW	469	/**
f62349ee MW	470	* omap_serial_init_port() - initialize single serial port
40e44399	471	* @bdata: port specific board data pointer
f62349ee	472	*
40e44399	473	* This function initialies serial driver for given port only.
f62349ee MW	474	* Platforms can call this function instead of omap_serial_init()
	475	* if they don't plan to use all available UARTs as serial ports.
	476	*
	477	* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
	478	* use only one of the two.
	479	*/
40e44399	480	void __init omap_serial_init_port(struct omap_board_data *bdata)
b3c6df3a	481	{
f62349ee	482	struct omap_uart_state *uart;
6f251e9d	483	struct omap_hwmod *oh;
3528c58e	484	struct platform_device *pdev;
6f251e9d KH	485	void *pdata = NULL;
	486	u32 pdata_size = 0;
	487	char *name;
6f251e9d	488	struct omap_uart_port_info omap_up;
970a724d	489
40e44399	490	if (WARN_ON(!bdata))
6f251e9d	491	return;
40e44399 TL	492	if (WARN_ON(bdata->id < 0))
	493	return;
	494	if (WARN_ON(bdata->id >= num_uarts))
e88d556d	495	return;
f62349ee	496
6f251e9d	497	list_for_each_entry(uart, &uart_list, node)
40e44399	498	if (bdata->id == uart->num)
6f251e9d	499	break;
f2eeeae0	500
6f251e9d KH	501	oh = uart->oh;
6f251e9d KH	502	uart->dma_enabled = 0;
6f251e9d KH	503	name = DRIVER_NAME;
	504
	505	omap_up.dma_enabled = uart->dma_enabled;
	506	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
	507	omap_up.mapbase = oh->slaves[0]->addr->pa_start;
	508	omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
273558b3	509	omap_up.flags = UPF_BOOT_AUTOCONF;
6f251e9d KH	510
	511	pdata = &omap_up;
	512	pdata_size = sizeof(struct omap_uart_port_info);
6f251e9d KH	513
	514	if (WARN_ON(!oh))
	515	return;
	516
3528c58e	517	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
f718e2c0	518	NULL, 0, false);
3528c58e	519	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
6f251e9d KH	520	name, oh->name);
6f251e9d KH	521
9f8b6949	522	omap_device_disable_idle_on_suspend(pdev);
40e44399 TL	523	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
40e44399 TL	524
6f251e9d KH	525	uart->regshift = 2;
	526	uart->mapbase = oh->slaves[0]->addr->pa_start;
	527	uart->membase = omap_hwmod_get_mpu_rt_va(oh);
3528c58e	528	uart->pdev = pdev;
6f251e9d KH	529
	530	oh->dev_attr = uart;
	531
ac751efa	532	console_lock(); /* in case the earlycon is on the UART */
0d8e2d0d	533
6f251e9d KH	534	/*
	535	* Because of early UART probing, UART did not get idled
	536	* on init. Now that omap_device is ready, ensure full idle
	537	* before doing omap_device_enable().
	538	*/
	539	omap_hwmod_idle(uart->oh);
	540
	541	omap_device_enable(uart->pdev);
	542	omap_uart_idle_init(uart);
	543	omap_uart_reset(uart);
	544	omap_hwmod_enable_wakeup(uart->oh);
	545	omap_device_idle(uart->pdev);
	546
6f251e9d	547	omap_uart_block_sleep(uart);
ac751efa	548	console_unlock();
0d8e2d0d	549
6f251e9d	550	if ((cpu_is_omap34xx() && uart->padconf) \|\|
273558b3	551	(uart->wk_en && uart->wk_mask))
3528c58e	552	device_init_wakeup(&pdev->dev, true);
00034509 D	553
00034509 D	554	/* Enable the MDR1 errata for OMAP3 */
a920360f	555	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() \|\| cpu_is_am33xx()))
00034509	556	uart->errata \|= UART_ERRATA_i202_MDR1_ACCESS;
f62349ee MW	557	}
	558
	559	/**
b595076a	560	* omap_serial_init() - initialize all supported serial ports
f62349ee MW	561	*
	562	* Initializes all available UARTs as serial ports. Platforms
	563	* can call this function when they want to have default behaviour
	564	* for serial ports (e.g initialize them all as serial ports).
	565	*/
	566	void __init omap_serial_init(void)
	567	{
6f251e9d	568	struct omap_uart_state *uart;
40e44399	569	struct omap_board_data bdata;
f62349ee	570
40e44399 TL	571	list_for_each_entry(uart, &uart_list, node) {
	572	bdata.id = uart->num;
	573	bdata.flags = 0;
	574	bdata.pads = NULL;
	575	bdata.pads_cnt = 0;
	576	omap_serial_init_port(&bdata);
	577
	578	}
1dbae815	579	}