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Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs
[deliverable/linux.git] / arch / arm / mach-omap2 / serial.c
CommitLineData
1dbae815 1/*
f30c2269 2 * arch/arm/mach-omap2/serial.c
1dbae815
TL		 3 *
4 * OMAP2 serial support.
5 *
6e81176d 6 * Copyright (C) 2005-2008 Nokia Corporation
1dbae815
TL		 7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
4af4016c
KH		 9 * Major rework for PM support by Kevin Hilman
10 *
1dbae815
TL		 11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
44169075
SS		 13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15 *
1dbae815
TL		 16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/serial_8250.h>
23#include <linux/serial_reg.h>
f8ce2547 24#include <linux/clk.h>
fced80c7 25#include <linux/io.h>
e03d37d8 26#include <linux/delay.h>
1dbae815 27
ce491cf8
TL		 28#include <plat/common.h>
29#include <plat/board.h>
30#include <plat/clock.h>
31#include <plat/control.h>
4af4016c
KH		 32
33#include "prm.h"
34#include "pm.h"
35#include "prm-regbits-34xx.h"
36
ce13d471 37#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
4af4016c
KH		 38#define UART_OMAP_WER 0x17 /* Wake-up enable register */
39
301fe8ee
TL		 40/*
41 * NOTE: By default the serial timeout is disabled as it causes lost characters
42 * over the serial ports. This means that the UART clocks will stay on until
43 * disabled via sysfs. This also causes that any deeper omap sleep states are
44 * blocked.
45 */
46#define DEFAULT_TIMEOUT 0
4af4016c
KH		 47
48struct omap_uart_state {
49 int num;
50 int can_sleep;
51 struct timer_list timer;
52 u32 timeout;
53
54 void __iomem *wk_st;
55 void __iomem *wk_en;
56 u32 wk_mask;
57 u32 padconf;
58
59 struct clk *ick;
60 struct clk *fck;
61 int clocked;
62
63 struct plat_serial8250_port *p;
64 struct list_head node;
fd455ea8 65 struct platform_device pdev;
1dbae815 66
4af4016c
KH		 67#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
68 int context_valid;
69
70 /* Registers to be saved/restored for OFF-mode */
71 u16 dll;
72 u16 dlh;
73 u16 ier;
74 u16 sysc;
75 u16 scr;
76 u16 wer;
77#endif
78};
79
4af4016c 80static LIST_HEAD(uart_list);
1dbae815 81
fd455ea8 82static struct plat_serial8250_port serial_platform_data0[] = {
1dbae815 83 {
1dbae815
TL		 84 .irq = 72,
85 .flags = UPF_BOOT_AUTOCONF,
86 .iotype = UPIO_MEM,
87 .regshift = 2,
6e81176d 88 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815 89 }, {
fd455ea8
KH		 90 .flags = 0
91 }
92};
93
94static struct plat_serial8250_port serial_platform_data1[] = {
95 {
1dbae815
TL		 96 .irq = 73,
97 .flags = UPF_BOOT_AUTOCONF,
98 .iotype = UPIO_MEM,
99 .regshift = 2,
6e81176d 100 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815 101 }, {
fd455ea8
KH		 102 .flags = 0
103 }
104};
105
106static struct plat_serial8250_port serial_platform_data2[] = {
107 {
1dbae815
TL		 108 .irq = 74,
109 .flags = UPF_BOOT_AUTOCONF,
110 .iotype = UPIO_MEM,
111 .regshift = 2,
6e81176d 112 .uartclk = OMAP24XX_BASE_BAUD * 16,
1dbae815
TL		 113 }, {
114 .flags = 0
115 }
116};
117
0e3eaadf
SS		 118static struct plat_serial8250_port serial_platform_data3[] = {
119 {
0e3eaadf
SS		 120 .irq = 70,
121 .flags = UPF_BOOT_AUTOCONF,
122 .iotype = UPIO_MEM,
123 .regshift = 2,
124 .uartclk = OMAP24XX_BASE_BAUD * 16,
125 }, {
126 .flags = 0
127 }
128};
a3a9b36e 129
4f2c49fe
TL		 130void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
131{
132 serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
133 serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
134 serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
4b1bbd3f 135 serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
4f2c49fe
TL		 136}
137
9230372a
AS		 138static inline unsigned int __serial_read_reg(struct uart_port *up,
139 int offset)
140{
141 offset <<= up->regshift;
142 return (unsigned int)__raw_readb(up->membase + offset);
143}
144
1dbae815
TL		 145static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
146 int offset)
147{
148 offset <<= up->regshift;
149 return (unsigned int)__raw_readb(up->membase + offset);
150}
151
e03d37d8
SS		 152static inline void __serial_write_reg(struct uart_port *up, int offset,
153 int value)
154{
155 offset <<= up->regshift;
156 __raw_writeb(value, up->membase + offset);
157}
158
1dbae815
TL		 159static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
160 int value)
161{
162 offset <<= p->regshift;
e8a91c95 163 __raw_writeb(value, p->membase + offset);
1dbae815
TL		 164}
165
166/*
167 * Internal UARTs need to be initialized for the 8250 autoconfig to work
168 * properly. Note that the TX watermark initialization may not be needed
169 * once the 8250.c watermark handling code is merged.
170 */
4af4016c 171static inline void __init omap_uart_reset(struct omap_uart_state *uart)
1dbae815 172{
4af4016c
KH		 173 struct plat_serial8250_port *p = uart->p;
174
1dbae815
TL		 175 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
176 serial_write_reg(p, UART_OMAP_SCR, 0x08);
177 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
671c7235 178 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
1dbae815
TL		 179}
180
4af4016c
KH		 181#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
182
4af4016c 183static void omap_uart_save_context(struct omap_uart_state *uart)
6e81176d 184{
4af4016c
KH		 185 u16 lcr = 0;
186 struct plat_serial8250_port *p = uart->p;
187
188 if (!enable_off_mode)
189 return;
190
191 lcr = serial_read_reg(p, UART_LCR);
192 serial_write_reg(p, UART_LCR, 0xBF);
193 uart->dll = serial_read_reg(p, UART_DLL);
194 uart->dlh = serial_read_reg(p, UART_DLM);
195 serial_write_reg(p, UART_LCR, lcr);
196 uart->ier = serial_read_reg(p, UART_IER);
197 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
198 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
199 uart->wer = serial_read_reg(p, UART_OMAP_WER);
200
201 uart->context_valid = 1;
202}
203
204static void omap_uart_restore_context(struct omap_uart_state *uart)
205{
206 u16 efr = 0;
207 struct plat_serial8250_port *p = uart->p;
208
209 if (!enable_off_mode)
210 return;
211
212 if (!uart->context_valid)
213 return;
214
215 uart->context_valid = 0;
216
217 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
218 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
219 efr = serial_read_reg(p, UART_EFR);
220 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
221 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
222 serial_write_reg(p, UART_IER, 0x0);
223 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
224 serial_write_reg(p, UART_DLL, uart->dll);
225 serial_write_reg(p, UART_DLM, uart->dlh);
226 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
227 serial_write_reg(p, UART_IER, uart->ier);
228 serial_write_reg(p, UART_FCR, 0xA1);
229 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
230 serial_write_reg(p, UART_EFR, efr);
231 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
232 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
233 serial_write_reg(p, UART_OMAP_WER, uart->wer);
234 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
235 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
236}
237#else
238static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
239static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
240#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
241
242static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
243{
244 if (uart->clocked)
245 return;
246
247 clk_enable(uart->ick);
248 clk_enable(uart->fck);
249 uart->clocked = 1;
250 omap_uart_restore_context(uart);
251}
252
253#ifdef CONFIG_PM
254
255static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
256{
257 if (!uart->clocked)
258 return;
259
260 omap_uart_save_context(uart);
261 uart->clocked = 0;
262 clk_disable(uart->ick);
263 clk_disable(uart->fck);
264}
265
fd455ea8
KH		 266static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
267{
268 /* Set wake-enable bit */
269 if (uart->wk_en && uart->wk_mask) {
270 u32 v = __raw_readl(uart->wk_en);
271 v |= uart->wk_mask;
272 __raw_writel(v, uart->wk_en);
273 }
274
275 /* Ensure IOPAD wake-enables are set */
276 if (cpu_is_omap34xx() && uart->padconf) {
277 u16 v = omap_ctrl_readw(uart->padconf);
278 v |= OMAP3_PADCONF_WAKEUPENABLE0;
279 omap_ctrl_writew(v, uart->padconf);
280 }
281}
282
283static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
284{
285 /* Clear wake-enable bit */
286 if (uart->wk_en && uart->wk_mask) {
287 u32 v = __raw_readl(uart->wk_en);
288 v &= ~uart->wk_mask;
289 __raw_writel(v, uart->wk_en);
290 }
291
292 /* Ensure IOPAD wake-enables are cleared */
293 if (cpu_is_omap34xx() && uart->padconf) {
294 u16 v = omap_ctrl_readw(uart->padconf);
295 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
296 omap_ctrl_writew(v, uart->padconf);
297 }
298}
299
4af4016c
KH		 300static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
301 int enable)
302{
303 struct plat_serial8250_port *p = uart->p;
304 u16 sysc;
305
306 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
307 if (enable)
308 sysc |= 0x2 << 3;
309 else
310 sysc |= 0x1 << 3;
311
312 serial_write_reg(p, UART_OMAP_SYSC, sysc);
313}
314
315static void omap_uart_block_sleep(struct omap_uart_state *uart)
316{
317 omap_uart_enable_clocks(uart);
318
319 omap_uart_smart_idle_enable(uart, 0);
320 uart->can_sleep = 0;
ba87a9be
JH		 321 if (uart->timeout)
322 mod_timer(&uart->timer, jiffies + uart->timeout);
323 else
324 del_timer(&uart->timer);
4af4016c
KH		 325}
326
327static void omap_uart_allow_sleep(struct omap_uart_state *uart)
328{
fd455ea8
KH		 329 if (device_may_wakeup(&uart->pdev.dev))
330 omap_uart_enable_wakeup(uart);
331 else
332 omap_uart_disable_wakeup(uart);
333
4af4016c
KH		 334 if (!uart->clocked)
335 return;
336
337 omap_uart_smart_idle_enable(uart, 1);
338 uart->can_sleep = 1;
339 del_timer(&uart->timer);
340}
341
342static void omap_uart_idle_timer(unsigned long data)
343{
344 struct omap_uart_state *uart = (struct omap_uart_state *)data;
345
346 omap_uart_allow_sleep(uart);
347}
348
349void omap_uart_prepare_idle(int num)
350{
351 struct omap_uart_state *uart;
352
353 list_for_each_entry(uart, &uart_list, node) {
354 if (num == uart->num && uart->can_sleep) {
355 omap_uart_disable_clocks(uart);
356 return;
357 }
358 }
359}
360
361void omap_uart_resume_idle(int num)
362{
363 struct omap_uart_state *uart;
364
365 list_for_each_entry(uart, &uart_list, node) {
366 if (num == uart->num) {
367 omap_uart_enable_clocks(uart);
368
369 /* Check for IO pad wakeup */
370 if (cpu_is_omap34xx() && uart->padconf) {
371 u16 p = omap_ctrl_readw(uart->padconf);
372
373 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
374 omap_uart_block_sleep(uart);
6e81176d 375 }
4af4016c
KH		 376
377 /* Check for normal UART wakeup */
378 if (__raw_readl(uart->wk_st) & uart->wk_mask)
379 omap_uart_block_sleep(uart);
4af4016c
KH		 380 return;
381 }
382 }
383}
384
385void omap_uart_prepare_suspend(void)
386{
387 struct omap_uart_state *uart;
388
389 list_for_each_entry(uart, &uart_list, node) {
390 omap_uart_allow_sleep(uart);
391 }
392}
393
394int omap_uart_can_sleep(void)
395{
396 struct omap_uart_state *uart;
397 int can_sleep = 1;
398
399 list_for_each_entry(uart, &uart_list, node) {
400 if (!uart->clocked)
401 continue;
402
403 if (!uart->can_sleep) {
404 can_sleep = 0;
405 continue;
6e81176d 406 }
4af4016c
KH		 407
408 /* This UART can now safely sleep. */
409 omap_uart_allow_sleep(uart);
6e81176d 410 }
4af4016c
KH		 411
412 return can_sleep;
6e81176d
JH		 413}
414
4af4016c
KH		 415/**
416 * omap_uart_interrupt()
417 *
418 * This handler is used only to detect that *any* UART interrupt has
419 * occurred. It does _nothing_ to handle the interrupt. Rather,
420 * any UART interrupt will trigger the inactivity timer so the
421 * UART will not idle or sleep for its timeout period.
422 *
423 **/
424static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
425{
426 struct omap_uart_state *uart = dev_id;
427
428 omap_uart_block_sleep(uart);
429
430 return IRQ_NONE;
431}
432
433static void omap_uart_idle_init(struct omap_uart_state *uart)
434{
4af4016c
KH		 435 struct plat_serial8250_port *p = uart->p;
436 int ret;
437
438 uart->can_sleep = 0;
fd455ea8 439 uart->timeout = DEFAULT_TIMEOUT;
4af4016c
KH		 440 setup_timer(&uart->timer, omap_uart_idle_timer,
441 (unsigned long) uart);
301fe8ee
TL		 442 if (uart->timeout)
443 mod_timer(&uart->timer, jiffies + uart->timeout);
4af4016c
KH		 444 omap_uart_smart_idle_enable(uart, 0);
445
446 if (cpu_is_omap34xx()) {
447 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
448 u32 wk_mask = 0;
449 u32 padconf = 0;
450
451 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
452 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
453 switch (uart->num) {
454 case 0:
455 wk_mask = OMAP3430_ST_UART1_MASK;
456 padconf = 0x182;
457 break;
458 case 1:
459 wk_mask = OMAP3430_ST_UART2_MASK;
460 padconf = 0x17a;
461 break;
462 case 2:
463 wk_mask = OMAP3430_ST_UART3_MASK;
464 padconf = 0x19e;
465 break;
466 }
467 uart->wk_mask = wk_mask;
468 uart->padconf = padconf;
469 } else if (cpu_is_omap24xx()) {
470 u32 wk_mask = 0;
471
472 if (cpu_is_omap2430()) {
473 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
474 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
475 } else if (cpu_is_omap2420()) {
476 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
477 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
478 }
479 switch (uart->num) {
480 case 0:
481 wk_mask = OMAP24XX_ST_UART1_MASK;
482 break;
483 case 1:
484 wk_mask = OMAP24XX_ST_UART2_MASK;
485 break;
486 case 2:
487 wk_mask = OMAP24XX_ST_UART3_MASK;
488 break;
489 }
490 uart->wk_mask = wk_mask;
491 } else {
492 uart->wk_en = 0;
493 uart->wk_st = 0;
494 uart->wk_mask = 0;
495 uart->padconf = 0;
496 }
497
c426df87 498 p->irqflags |= IRQF_SHARED;
4af4016c
KH		 499 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
500 "serial idle", (void *)uart);
501 WARN_ON(ret);
502}
503
2466211e
TK		 504void omap_uart_enable_irqs(int enable)
505{
506 int ret;
507 struct omap_uart_state *uart;
508
509 list_for_each_entry(uart, &uart_list, node) {
510 if (enable)
511 ret = request_irq(uart->p->irq, omap_uart_interrupt,
512 IRQF_SHARED, "serial idle", (void *)uart);
513 else
514 free_irq(uart->p->irq, (void *)uart);
515 }
516}
517
fd455ea8
KH		 518static ssize_t sleep_timeout_show(struct device *dev,
519 struct device_attribute *attr,
ba87a9be
JH		 520 char *buf)
521{
fd455ea8
KH		 522 struct platform_device *pdev = container_of(dev,
523 struct platform_device, dev);
524 struct omap_uart_state *uart = container_of(pdev,
525 struct omap_uart_state, pdev);
526
527 return sprintf(buf, "%u\n", uart->timeout / HZ);
ba87a9be
JH		 528}
529
fd455ea8
KH		 530static ssize_t sleep_timeout_store(struct device *dev,
531 struct device_attribute *attr,
ba87a9be
JH		 532 const char *buf, size_t n)
533{
fd455ea8
KH		 534 struct platform_device *pdev = container_of(dev,
535 struct platform_device, dev);
536 struct omap_uart_state *uart = container_of(pdev,
537 struct omap_uart_state, pdev);
ba87a9be
JH		 538 unsigned int value;
539
540 if (sscanf(buf, "%u", &value) != 1) {
10c805eb 541 dev_err(dev, "sleep_timeout_store: Invalid value\n");
ba87a9be
JH		 542 return -EINVAL;
543 }
fd455ea8
KH		 544
545 uart->timeout = value * HZ;
546 if (uart->timeout)
547 mod_timer(&uart->timer, jiffies + uart->timeout);
548 else
549 /* A zero value means disable timeout feature */
550 omap_uart_block_sleep(uart);
551
ba87a9be
JH		 552 return n;
553}
554
fd455ea8
KH		 555DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
556#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
4af4016c
KH		 557#else
558static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
fd455ea8 559#define DEV_CREATE_FILE(dev, attr)
4af4016c
KH		 560#endif /* CONFIG_PM */
561
9d30b99f 562static struct omap_uart_state omap_uart[] = {
fd455ea8
KH		 563 {
564 .pdev = {
565 .name = "serial8250",
566 .id = PLAT8250_DEV_PLATFORM,
567 .dev = {
568 .platform_data = serial_platform_data0,
569 },
570 },
571 }, {
572 .pdev = {
573 .name = "serial8250",
574 .id = PLAT8250_DEV_PLATFORM1,
575 .dev = {
576 .platform_data = serial_platform_data1,
577 },
578 },
579 }, {
580 .pdev = {
581 .name = "serial8250",
582 .id = PLAT8250_DEV_PLATFORM2,
583 .dev = {
584 .platform_data = serial_platform_data2,
585 },
586 },
2aa57be2 587 },
a3a9b36e 588#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
0e3eaadf
SS		 589 {
590 .pdev = {
591 .name = "serial8250",
61f04ee8 592 .id = 3,
0e3eaadf
SS		 593 .dev = {
594 .platform_data = serial_platform_data3,
595 },
596 },
597 },
598#endif
2aa57be2
VP		 599};
600
ce13d471 601/*
602 * Override the default 8250 read handler: mem_serial_in()
603 * Empty RX fifo read causes an abort on omap3630 and omap4
604 * This function makes sure that an empty rx fifo is not read on these silicons
605 * (OMAP1/2/3430 are not affected)
606 */
607static unsigned int serial_in_override(struct uart_port *up, int offset)
608{
609 if (UART_RX == offset) {
610 unsigned int lsr;
9230372a 611 lsr = __serial_read_reg(up, UART_LSR);
ce13d471 612 if (!(lsr & UART_LSR_DR))
613 return -EPERM;
614 }
9230372a
AS		 615
616 return __serial_read_reg(up, offset);
ce13d471 617}
618
e03d37d8
SS		 619static void serial_out_override(struct uart_port *up, int offset, int value)
620{
621 unsigned int status, tmout = 10000;
622
623 status = __serial_read_reg(up, UART_LSR);
624 while (!(status & UART_LSR_THRE)) {
625 /* Wait up to 10ms for the character(s) to be sent. */
626 if (--tmout == 0)
627 break;
628 udelay(1);
629 status = __serial_read_reg(up, UART_LSR);
630 }
631 __serial_write_reg(up, offset, value);
632}
b3c6df3a 633void __init omap_serial_early_init(void)
1dbae815 634{
21b90340 635 int i, nr_ports;
6e81176d 636 char name[16];
1dbae815 637
21b90340
TW		 638 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
639 nr_ports = 3;
640 else
641 nr_ports = ARRAY_SIZE(omap_uart);
642
1dbae815
TL		 643 /*
644 * Make sure the serial ports are muxed on at this point.
645 * You have to mux them off in device drivers later on
646 * if not needed.
647 */
648
21b90340 649 for (i = 0; i < nr_ports; i++) {
4af4016c 650 struct omap_uart_state *uart = &omap_uart[i];
fd455ea8
KH		 651 struct platform_device *pdev = &uart->pdev;
652 struct device *dev = &pdev->dev;
653 struct plat_serial8250_port *p = dev->platform_data;
1dbae815 654
e88d556d
SA		 655 /* Don't map zero-based physical address */
656 if (p->mapbase == 0) {
10c805eb
SA		 657 dev_warn(dev, "no physical address for uart#%d,"
658 " so skipping early_init...\n", i);
e88d556d
SA		 659 continue;
660 }
84f90c9c
TL		 661 /*
662 * Module 4KB + L4 interconnect 4KB
663 * Static mapping, never released
664 */
665 p->membase = ioremap(p->mapbase, SZ_8K);
666 if (!p->membase) {
10c805eb 667 dev_err(dev, "ioremap failed for uart%i\n", i + 1);
84f90c9c
TL		 668 continue;
669 }
670
21b90340 671 sprintf(name, "uart%d_ick", i + 1);
4af4016c
KH		 672 uart->ick = clk_get(NULL, name);
673 if (IS_ERR(uart->ick)) {
10c805eb 674 dev_err(dev, "Could not get uart%d_ick\n", i + 1);
4af4016c
KH		 675 uart->ick = NULL;
676 }
6e81176d
JH		 677
678 sprintf(name, "uart%d_fck", i+1);
4af4016c
KH		 679 uart->fck = clk_get(NULL, name);
680 if (IS_ERR(uart->fck)) {
10c805eb 681 dev_err(dev, "Could not get uart%d_fck\n", i + 1);
4af4016c
KH		 682 uart->fck = NULL;
683 }
684
aae290fb
SS		 685 /* FIXME: Remove this once the clkdev is ready */
686 if (!cpu_is_omap44xx()) {
687 if (!uart->ick || !uart->fck)
688 continue;
689 }
4af4016c
KH		 690
691 uart->num = i;
692 p->private_data = uart;
693 uart->p = p;
1dbae815 694
4789998a
KH		 695 if (cpu_is_omap44xx())
696 p->irq += 32;
b3c6df3a
PW		 697 }
698}
699
f62349ee
MW		 700/**
701 * omap_serial_init_port() - initialize single serial port
702 * @port: serial port number (0-3)
703 *
704 * This function initialies serial driver for given @port only.
705 * Platforms can call this function instead of omap_serial_init()
706 * if they don't plan to use all available UARTs as serial ports.
707 *
708 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
709 * use only one of the two.
710 */
711void __init omap_serial_init_port(int port)
b3c6df3a 712{
f62349ee
MW		 713 struct omap_uart_state *uart;
714 struct platform_device *pdev;
715 struct device *dev;
b3c6df3a 716
f62349ee
MW		 717 BUG_ON(port < 0);
718 BUG_ON(port >= ARRAY_SIZE(omap_uart));
b3c6df3a 719
f62349ee
MW		 720 uart = &omap_uart[port];
721 pdev = &uart->pdev;
722 dev = &pdev->dev;
970a724d 723
e88d556d
SA		 724 /* Don't proceed if there's no clocks available */
725 if (unlikely(!uart->ick || !uart->fck)) {
726 WARN(1, "%s: can't init uart%d, no clocks available\n",
727 kobject_name(&dev->kobj), port);
728 return;
729 }
730
f2eeeae0
MW		 731 omap_uart_enable_clocks(uart);
732
f62349ee
MW		 733 omap_uart_reset(uart);
734 omap_uart_idle_init(uart);
735
f2eeeae0
MW		 736 list_add_tail(&uart->node, &uart_list);
737
f62349ee
MW		 738 if (WARN_ON(platform_device_register(pdev)))
739 return;
740
741 if ((cpu_is_omap34xx() && uart->padconf) ||
742 (uart->wk_en && uart->wk_mask)) {
743 device_init_wakeup(dev, true);
744 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
fd455ea8 745 }
f62349ee 746
30e53bcc 747 /*
748 * omap44xx: Never read empty UART fifo
749 * omap3xxx: Never read empty UART fifo on UARTs
750 * with IP rev >=0x52
751 */
e03d37d8 752 if (cpu_is_omap44xx()) {
30e53bcc 753 uart->p->serial_in = serial_in_override;
e03d37d8
SS		 754 uart->p->serial_out = serial_out_override;
755 } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
756 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
30e53bcc 757 uart->p->serial_in = serial_in_override;
e03d37d8
SS		 758 uart->p->serial_out = serial_out_override;
759 }
f62349ee
MW		 760}
761
762/**
763 * omap_serial_init() - intialize all supported serial ports
764 *
765 * Initializes all available UARTs as serial ports. Platforms
766 * can call this function when they want to have default behaviour
767 * for serial ports (e.g initialize them all as serial ports).
768 */
769void __init omap_serial_init(void)
770{
a3a9b36e
TL		 771 int i, nr_ports;
772
773 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
774 nr_ports = 3;
775 else
776 nr_ports = ARRAY_SIZE(omap_uart);
f62349ee 777
a3a9b36e 778 for (i = 0; i < nr_ports; i++)
f62349ee 779 omap_serial_init_port(i);
1dbae815 780}
Linux kernel - Deliverables
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