[deliverable/linux.git] / arch / arm / mach-omap2 / sleep24xx.S

/*
 * linux/arch/arm/mach-omap2/sleep.S
 *
 * (C) Copyright 2004
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * (C) Copyright 2006 Nokia Corporation
 * Fixed idle loop sleep
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/io.h>

#include <plat/omap24xx.h>

#include "sdrc.h"

/* First address of reserved address space?  apparently valid for OMAP2 & 3 */
#define A_SDRC0_V		(0xC0000000)

	.text

/*
 * Forces OMAP into idle state
 *
 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
 * for normal idles.
 *
 * Note: This code get's copied to internal SRAM at boot. When the OMAP
 *	 wakes up it continues execution at the point it went to sleep.
 */
ENTRY(omap24xx_idle_loop_suspend)
	stmfd	sp!, {r0, lr}		@ save registers on stack
	mov	r0, #0			@ clear for mcr setup
	mcr	p15, 0, r0, c7, c0, 4	@ wait for interrupt
	ldmfd	sp!, {r0, pc}		@ restore regs and return

ENTRY(omap24xx_idle_loop_suspend_sz)
	.word	. - omap24xx_idle_loop_suspend

/*
 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
 * SDRC shutdown then ARM shutdown.  Upon wake MPU is back on so just restore
 * SDRC.
 *
 * Input:
 * R0 :	DLL ctrl value pre-Sleep
 * R1 : SDRC_DLLA_CTRL
 * R2 : SDRC_POWER
 *
 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
 * when we get called, but the DLL probably isn't.  We will wait a bit more in
 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
 * if in unlocked mode.
 *
 * For less than 242x-ES2.2 upon wake from a sleep mode where the external
 * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
 * clock can pass into the PRCM can cause problems at DSP and IVA.
 * To work around this the code will switch to the 32kHz source prior to sleep.
 * Post sleep we will shift back to using the DPLL.  Apparently,
 * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
 * 3x12MHz + 3x32kHz clocks for a full switch.
 *
 * The DLL load value is not kept in RETENTION or OFF.	It needs to be restored
 * at wake
 */
ENTRY(omap24xx_cpu_suspend)
	stmfd	sp!, {r0 - r12, lr}	@ save registers on stack
	mov	r3, #0x0		@ clear for mcr call
	mcr	p15, 0, r3, c7, c10, 4	@ memory barrier, hope SDR/DDR finished
	nop
	nop
	ldr	r4, [r2]		@ read SDRC_POWER
	orr	r4, r4, #0x40		@ enable self refresh on idle req
	mov	r5, #0x2000		@ set delay (DPLL relock + DLL relock)
	str	r4, [r2]		@ make it so
	nop
	mcr	p15, 0, r3, c7, c0, 4	@ wait for interrupt
	nop
loop:
	subs	r5, r5, #0x1		@ awake, wait just a bit
	bne	loop

	/* The DPLL has to be on before we take the DDR out of self refresh */
	bic	r4, r4, #0x40		@ now clear self refresh bit.
	str	r4, [r2]		@ write to SDRC_POWER
	ldr	r4, A_SDRC0		@ make a clock happen
	ldr	r4, [r4]		@ read A_SDRC0
	nop				@ start auto refresh only after clk ok
	movs	r0, r0			@ see if DDR or SDR
	strne	r0, [r1]		@ rewrite DLLA to force DLL reload
	addne	r1, r1, #0x8		@ move to DLLB
	strne	r0, [r1]		@ rewrite DLLB to force DLL reload

	mov	r5, #0x1000
loop2:
	subs	r5, r5, #0x1
	bne	loop2
	/* resume*/
	ldmfd	sp!, {r0 - r12, pc}	@ restore regs and return

A_SDRC0:
	.word A_SDRC0_V

ENTRY(omap24xx_cpu_suspend_sz)
	.word	. - omap24xx_cpu_suspend
Commit	Line	Data
670c104a TL	1	/*
	2	* linux/arch/arm/mach-omap2/sleep.S
	3	*
	4	* (C) Copyright 2004
	5	* Texas Instruments, <www.ti.com>
	6	* Richard Woodruff <r-woodruff2@ti.com>
	7	*
1835f1d7 TL	8	* (C) Copyright 2006 Nokia Corporation
	9	* Fixed idle loop sleep
	10	* Igor Stoppa <igor.stoppa@nokia.com>
	11	*
670c104a TL	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
670c104a TL	28	#include <linux/linkage.h>
670c104a TL	29	#include <asm/assembler.h>
a09e64fb	30	#include <mach/io.h>
670c104a	31
ce491cf8	32	#include <plat/omap24xx.h>
1835f1d7	33
44595982	34	#include "sdrc.h"
670c104a	35
44595982	36	/* First address of reserved address space? apparently valid for OMAP2 & 3 */
670c104a	37	#define A_SDRC0_V (0xC0000000)
670c104a TL	38
	39	.text
	40
	41	/*
	42	* Forces OMAP into idle state
	43	*
	44	* omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
	45	* for normal idles.
	46	*
	47	* Note: This code get's copied to internal SRAM at boot. When the OMAP
	48	* wakes up it continues execution at the point it went to sleep.
	49	*/
	50	ENTRY(omap24xx_idle_loop_suspend)
	51	stmfd sp!, {r0, lr} @ save registers on stack
	52	mov r0, #0 @ clear for mcr setup
	53	mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
	54	ldmfd sp!, {r0, pc} @ restore regs and return
	55
	56	ENTRY(omap24xx_idle_loop_suspend_sz)
	57	.word . - omap24xx_idle_loop_suspend
	58
	59	/*
1835f1d7	60	* omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
670c104a TL	61	* SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
	62	* SDRC.
	63	*
	64	* Input:
	65	* R0 : DLL ctrl value pre-Sleep
1835f1d7 TL	66	* R1 : SDRC_DLLA_CTRL
1835f1d7 TL	67	* R2 : SDRC_POWER
670c104a TL	68	*
	69	* The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
	70	* when we get called, but the DLL probably isn't. We will wait a bit more in
	71	* case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
	72	* if in unlocked mode.
	73	*
	74	* For less than 242x-ES2.2 upon wake from a sleep mode where the external
	75	* oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
	76	* clock can pass into the PRCM can cause problems at DSP and IVA.
	77	* To work around this the code will switch to the 32kHz source prior to sleep.
	78	* Post sleep we will shift back to using the DPLL. Apparently,
	79	* CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
	80	* 3x12MHz + 3x32kHz clocks for a full switch.
	81	*
	82	* The DLL load value is not kept in RETENTION or OFF. It needs to be restored
	83	* at wake
	84	*/
	85	ENTRY(omap24xx_cpu_suspend)
	86	stmfd sp!, {r0 - r12, lr} @ save registers on stack
1835f1d7	87	mov r3, #0x0 @ clear for mcr call
670c104a TL	88	mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
	89	nop
	90	nop
1835f1d7	91	ldr r4, [r2] @ read SDRC_POWER
670c104a TL	92	orr r4, r4, #0x40 @ enable self refresh on idle req
670c104a TL	93	mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
1835f1d7	94	str r4, [r2] @ make it so
670c104a	95	nop
0dc23d70	96	mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
670c104a TL	97	nop
	98	loop:
	99	subs r5, r5, #0x1 @ awake, wait just a bit
	100	bne loop
	101
1835f1d7	102	/* The DPLL has to be on before we take the DDR out of self refresh */
670c104a	103	bic r4, r4, #0x40 @ now clear self refresh bit.
1835f1d7	104	str r4, [r2] @ write to SDRC_POWER
670c104a	105	ldr r4, A_SDRC0 @ make a clock happen
1835f1d7	106	ldr r4, [r4] @ read A_SDRC0
670c104a TL	107	nop @ start auto refresh only after clk ok
670c104a TL	108	movs r0, r0 @ see if DDR or SDR
670c104a TL	109	strne r0, [r1] @ rewrite DLLA to force DLL reload
	110	addne r1, r1, #0x8 @ move to DLLB
	111	strne r0, [r1] @ rewrite DLLB to force DLL reload
	112
	113	mov r5, #0x1000
	114	loop2:
	115	subs r5, r5, #0x1
	116	bne loop2
	117	/* resume*/
	118	ldmfd sp!, {r0 - r12, pc} @ restore regs and return
	119
670c104a TL	120	A_SDRC0:
670c104a TL	121	.word A_SDRC0_V
670c104a TL	122
	123	ENTRY(omap24xx_cpu_suspend_sz)
	124	.word . - omap24xx_cpu_suspend