[deliverable/linux.git] / arch / arm / mach-omap2 / sram242x.S

/*
 * linux/arch/arm/mach-omap2/sram242x.S
 *
 * Omap2 specific functions that need to be run in internal SRAM
 *
 * (C) Copyright 2004
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Richard Woodruff notes that any changes to this code must be carefully
 * audited and tested to ensure that they don't cause a TLB miss while
 * the SDRAM is inaccessible.  Such a situation will crash the system
 * since it will cause the ARM MMU to attempt to walk the page tables.
 * These crashes may be intermittent.
 */
#include <linux/linkage.h>

#include <asm/assembler.h>

#include <mach/hardware.h>

#include "iomap.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "sdrc.h"

	.text

	.align	3
ENTRY(omap242x_sram_ddr_init)
	stmfd	sp!, {r0 - r12, lr}	@ save registers on stack

	mov	r12, r2			@ capture CS1 vs CS0
	mov	r8, r3			@ capture force parameter

	/* frequency shift down */
	ldr	r2, omap242x_sdi_cm_clksel2_pll	@ get address of dpllout reg
	mov	r3, #0x1		@ value for 1x operation
	str	r3, [r2]		@ go to L1-freq operation

	/* voltage shift down */
	mov r9, #0x1			@ set up for L1 voltage call
	bl voltage_shift		@ go drop voltage

	/* dll lock mode */
	ldr	r11, omap242x_sdi_sdrc_dlla_ctrl	@ addr of dlla ctrl
	ldr	r10, [r11]		@ get current val
	cmp	r12, #0x1		@ cs1 base (2422 es2.05/1)
	addeq	r11, r11, #0x8		@ if cs1 base, move to DLLB
	mvn	r9, #0x4		@ mask to get clear bit2
	and	r10, r10, r9		@ clear bit2 for lock mode.
	orr	r10, r10, #0x8		@ make sure DLL on (es2 bit pos)
	orr	r10, r10, #0x2		@ 90 degree phase for all below 133Mhz
	str	r10, [r11]		@ commit to DLLA_CTRL
	bl	i_dll_wait		@ wait for dll to lock

	/* get dll value */
	add	r11, r11, #0x4		@ get addr of status reg
	ldr	r10, [r11]		@ get locked value

	/* voltage shift up */
	mov r9, #0x0			@ shift back to L0-voltage
	bl voltage_shift		@ go raise voltage

	/* frequency shift up */
	mov	r3, #0x2		@ value for 2x operation
	str	r3, [r2]		@ go to L0-freq operation

	/* reset entry mode for dllctrl */
	sub	r11, r11, #0x4		@ move from status to ctrl
	cmp	r12, #0x1		@ normalize if cs1 based
	subeq	r11, r11, #0x8		@ possibly back to DLLA
	cmp	r8, #0x1		@ if forced unlock exit
	orreq	r1, r1, #0x4		@ make sure exit with unlocked value
	str	r1, [r11]		@ restore DLLA_CTRL high value
	add	r11, r11, #0x8		@ move to DLLB_CTRL addr
	str	r1, [r11]		@ set value DLLB_CTRL
	bl	i_dll_wait		@ wait for possible lock

	/* set up for return, DDR should be good */
	str r10, [r0]			@ write dll_status and return counter
	ldmfd	sp!, {r0 - r12, pc}	@ restore regs and return

	/* ensure the DLL has relocked */
i_dll_wait:
	mov	r4, #0x800		@ delay DLL relock, min 0x400 L3 clocks
i_dll_delay:
	subs	r4, r4, #0x1
	bne	i_dll_delay
	mov	pc, lr

	/*
	 * shift up or down voltage, use R9 as input to tell level.
	 * wait for it to finish, use 32k sync counter, 1tick=31uS.
	 */
voltage_shift:
	ldr	r4, omap242x_sdi_prcm_voltctrl	@ get addr of volt ctrl.
	ldr	r5, [r4]		@ get value.
	ldr	r6, prcm_mask_val	@ get value of mask
	and	r5, r5, r6		@ apply mask to clear bits
	orr	r5, r5, r9		@ bulld value for L0/L1-volt operation.
	str	r5, [r4]		@ set up for change.
	mov	r3, #0x4000		@ get val for force
	orr	r5, r5, r3		@ build value for force
	str	r5, [r4]		@ Force transition to L1

	ldr	r3, omap242x_sdi_timer_32ksynct_cr	@ get addr of counter
	ldr	r5, [r3]		@ get value
	add	r5, r5, #0x3		@ give it at most 93uS
volt_delay:
	ldr	r7, [r3]		@ get timer value
	cmp	r5, r7			@ time up?
	bhi	volt_delay		@ not yet->branch
	mov	pc, lr			@ back to caller.

omap242x_sdi_cm_clksel2_pll:
	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
omap242x_sdi_sdrc_dlla_ctrl:
	.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
omap242x_sdi_prcm_voltctrl:
	.word OMAP2420_PRCM_VOLTCTRL
prcm_mask_val:
	.word 0xFFFF3FFC
omap242x_sdi_timer_32ksynct_cr:
	.word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
ENTRY(omap242x_sram_ddr_init_sz)
	.word	. - omap242x_sram_ddr_init

/*
 * Reprograms memory timings.
 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
 */
	.align	3
ENTRY(omap242x_sram_reprogram_sdrc)
	stmfd	sp!, {r0 - r10, lr}	@ save registers on stack
	mov	r3, #0x0		@ clear for mrc call
	mcr	p15, 0, r3, c7, c10, 4	@ memory barrier, finish ARM SDR/DDR
	nop
	nop
	ldr	r6, omap242x_srs_sdrc_rfr_ctrl	@ get addr of refresh reg
	ldr	r5, [r6]		@ get value
	mov	r5, r5, lsr #8		@ isolate rfr field and drop burst

	cmp	r0, #0x1		@ going to half speed?
	movne	r9, #0x0		@ if up set flag up for pre up, hi volt

	blne	voltage_shift_c		@ adjust voltage

	cmp	r0, #0x1		@ going to half speed (post branch link)
	moveq	r5, r5, lsr #1		@ divide by 2 if to half
	movne	r5, r5, lsl #1		@ mult by 2 if to full
	mov	r5, r5, lsl #8		@ put rfr field back into place
	add	r5, r5, #0x1		@ turn on burst of 1
	ldr	r4, omap242x_srs_cm_clksel2_pll	@ get address of out reg
	ldr	r3, [r4]		@ get curr value
	orr	r3, r3, #0x3
	bic	r3, r3, #0x3		@ clear lower bits
	orr	r3, r3, r0		@ new state value
	str	r3, [r4]		@ set new state (pll/x, x=1 or 2)
	nop
	nop

	moveq	r9, #0x1		@ if speed down, post down, drop volt
	bleq	voltage_shift_c

	mcr	p15, 0, r3, c7, c10, 4	@ memory barrier
	str	r5, [r6]		@ set new RFR_1 value
	add	r6, r6, #0x30		@ get RFR_2 addr
	str	r5, [r6]		@ set RFR_2
	nop
	cmp	r2, #0x1		@ (SDR or DDR) do we need to adjust DLL
	bne	freq_out		@ leave if SDR, no DLL function

	/* With DDR, we need to take care of the DLL for the frequency change */
	ldr	r2, omap242x_srs_sdrc_dlla_ctrl	@ addr of dlla ctrl
	str	r1, [r2]		@ write out new SDRC_DLLA_CTRL
	add	r2, r2, #0x8		@ addr to SDRC_DLLB_CTRL
	str	r1, [r2]		@ commit to SDRC_DLLB_CTRL
	mov	r1, #0x2000		@ wait DLL relock, min 0x400 L3 clocks
dll_wait:
	subs	r1, r1, #0x1
	bne	dll_wait
freq_out:
	ldmfd	sp!, {r0 - r10, pc}	@ restore regs and return

    /*
     * shift up or down voltage, use R9 as input to tell level.
     *	wait for it to finish, use 32k sync counter, 1tick=31uS.
     */
voltage_shift_c:
	ldr	r10, omap242x_srs_prcm_voltctrl	@ get addr of volt ctrl
	ldr	r8, [r10]		@ get value
	ldr	r7, ddr_prcm_mask_val	@ get value of mask
	and	r8, r8, r7		@ apply mask to clear bits
	orr	r8, r8, r9		@ bulld value for L0/L1-volt operation.
	str	r8, [r10]		@ set up for change.
	mov	r7, #0x4000		@ get val for force
	orr	r8, r8, r7		@ build value for force
	str	r8, [r10]		@ Force transition to L1

	ldr	r10, omap242x_srs_timer_32ksynct	@ get addr of counter
	ldr	r8, [r10]		@ get value
	add	r8, r8, #0x2		@ give it at most 62uS (min 31+)
volt_delay_c:
	ldr	r7, [r10]		@ get timer value
	cmp	r8, r7			@ time up?
	bhi	volt_delay_c		@ not yet->branch
	mov	pc, lr			@ back to caller

omap242x_srs_cm_clksel2_pll:
	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
omap242x_srs_sdrc_dlla_ctrl:
	.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
omap242x_srs_sdrc_rfr_ctrl:
	.word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap242x_srs_prcm_voltctrl:
	.word OMAP2420_PRCM_VOLTCTRL
ddr_prcm_mask_val:
	.word 0xFFFF3FFC
omap242x_srs_timer_32ksynct:
	.word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)

ENTRY(omap242x_sram_reprogram_sdrc_sz)
	.word	. - omap242x_sram_reprogram_sdrc

/*
 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
 */
	.align	3
ENTRY(omap242x_sram_set_prcm)
	stmfd	sp!, {r0-r12, lr}	@ regs to stack
	adr	r4, pbegin		@ addr of preload start
	adr	r8, pend		@ addr of preload end
	mcrr	p15, 1, r8, r4, c12	@ preload into icache
pbegin:
	/* move into fast relock bypass */
	ldr	r8, omap242x_ssp_pll_ctl	@ get addr
	ldr	r5, [r8]		@ get val
	mvn	r6, #0x3		@ clear mask
	and	r5, r5, r6		@ clear field
	orr	r7, r5, #0x2		@ fast relock val
	str	r7, [r8]		@ go to fast relock
	ldr	r4, omap242x_ssp_pll_stat	@ addr of stat
block:
	/* wait for bypass */
	ldr	r8, [r4]		@ stat value
	and	r8, r8, #0x3		@ mask for stat
	cmp	r8, #0x1		@ there yet
	bne	block			@ loop if not

	/* set new dpll dividers _after_ in bypass */
	ldr	r4, omap242x_ssp_pll_div	@ get addr
	str	r0, [r4]		@ set dpll ctrl val

	ldr	r4, omap242x_ssp_set_config	@ get addr
	mov	r8, #1			@ valid cfg msk
	str	r8, [r4]		@ make dividers take

	mov	r4, #100		@ dead spin a bit
wait_a_bit:
	subs	r4, r4, #1		@ dec loop
	bne	wait_a_bit		@ delay done?

	/* check if staying in bypass */
	cmp	r2, #0x1		@ stay in bypass?
	beq	pend			@ jump over dpll relock

	/* relock DPLL with new vals */
	ldr	r5, omap242x_ssp_pll_stat	@ get addr
	ldr	r4, omap242x_ssp_pll_ctl	@ get addr
	orr	r8, r7, #0x3		@ val for lock dpll
	str	r8, [r4]		@ set val
	mov	r0, #1000		@ dead spin a bit
wait_more:
	subs	r0, r0, #1		@ dec loop
	bne	wait_more		@ delay done?
wait_lock:
	ldr	r8, [r5]		@ get lock val
	and	r8, r8, #3		@ isolate field
	cmp	r8, #2			@ locked?
	bne	wait_lock		@ wait if not
pend:
	/* update memory timings & briefly lock dll */
	ldr	r4, omap242x_ssp_sdrc_rfr	@ get addr
	str	r1, [r4]		@ update refresh timing
	ldr	r11, omap242x_ssp_dlla_ctrl	@ get addr of DLLA ctrl
	ldr	r10, [r11]		@ get current val
	mvn	r9, #0x4		@ mask to get clear bit2
	and	r10, r10, r9		@ clear bit2 for lock mode
	orr	r10, r10, #0x8		@ make sure DLL on (es2 bit pos)
	str	r10, [r11]		@ commit to DLLA_CTRL
	add	r11, r11, #0x8		@ move to dllb
	str	r10, [r11]		@ hit DLLB also

	mov	r4, #0x800		@ relock time (min 0x400 L3 clocks)
wait_dll_lock:
	subs	r4, r4, #0x1
	bne	wait_dll_lock
	nop
	ldmfd	sp!, {r0-r12, pc}	@ restore regs and return

omap242x_ssp_set_config:
	.word OMAP2420_PRCM_CLKCFG_CTRL
omap242x_ssp_pll_ctl:
	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
omap242x_ssp_pll_stat:
	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
omap242x_ssp_pll_div:
	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
omap242x_ssp_sdrc_rfr:
	.word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap242x_ssp_dlla_ctrl:
	.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)

ENTRY(omap242x_sram_set_prcm_sz)
	.word	. - omap242x_sram_set_prcm
Commit	Line	Data
1dbae815	1	/*
c2d43e39	2	* linux/arch/arm/mach-omap2/sram242x.S
1dbae815 TL	3	*
	4	* Omap2 specific functions that need to be run in internal SRAM
	5	*
	6	* (C) Copyright 2004
	7	* Texas Instruments, <www.ti.com>
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
1124d2f9 PW	24	*
	25	* Richard Woodruff notes that any changes to this code must be carefully
	26	* audited and tested to ensure that they don't cause a TLB miss while
	27	* the SDRAM is inaccessible. Such a situation will crash the system
	28	* since it will cause the ARM MMU to attempt to walk the page tables.
	29	* These crashes may be intermittent.
1dbae815	30	*/
1dbae815	31	#include <linux/linkage.h>
ee0839c2	32
1dbae815	33	#include <asm/assembler.h>
ee0839c2	34
a09e64fb	35	#include <mach/hardware.h>
1dbae815	36
ee0839c2	37	#include "iomap.h"
59fb659b PW	38	#include "prm2xxx_3xxx.h"
59fb659b PW	39	#include "cm2xxx_3xxx.h"
c2d43e39	40	#include "sdrc.h"
1dbae815 TL	41
	42	.text
	43
b6338bdc	44	.align 3
c2d43e39	45	ENTRY(omap242x_sram_ddr_init)
1dbae815 TL	46	stmfd sp!, {r0 - r12, lr} @ save registers on stack
	47
	48	mov r12, r2 @ capture CS1 vs CS0
	49	mov r8, r3 @ capture force parameter
	50
	51	/* frequency shift down */
c2d43e39	52	ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
1dbae815 TL	53	mov r3, #0x1 @ value for 1x operation
	54	str r3, [r2] @ go to L1-freq operation
	55
	56	/* voltage shift down */
	57	mov r9, #0x1 @ set up for L1 voltage call
	58	bl voltage_shift @ go drop voltage
	59
	60	/* dll lock mode */
c2d43e39	61	ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
1dbae815 TL	62	ldr r10, [r11] @ get current val
	63	cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
	64	addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
	65	mvn r9, #0x4 @ mask to get clear bit2
	66	and r10, r10, r9 @ clear bit2 for lock mode.
	67	orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
	68	orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
	69	str r10, [r11] @ commit to DLLA_CTRL
	70	bl i_dll_wait @ wait for dll to lock
	71
	72	/* get dll value */
	73	add r11, r11, #0x4 @ get addr of status reg
	74	ldr r10, [r11] @ get locked value
	75
	76	/* voltage shift up */
	77	mov r9, #0x0 @ shift back to L0-voltage
	78	bl voltage_shift @ go raise voltage
	79
	80	/* frequency shift up */
	81	mov r3, #0x2 @ value for 2x operation
	82	str r3, [r2] @ go to L0-freq operation
	83
	84	/* reset entry mode for dllctrl */
	85	sub r11, r11, #0x4 @ move from status to ctrl
	86	cmp r12, #0x1 @ normalize if cs1 based
	87	subeq r11, r11, #0x8 @ possibly back to DLLA
	88	cmp r8, #0x1 @ if forced unlock exit
	89	orreq r1, r1, #0x4 @ make sure exit with unlocked value
	90	str r1, [r11] @ restore DLLA_CTRL high value
	91	add r11, r11, #0x8 @ move to DLLB_CTRL addr
	92	str r1, [r11] @ set value DLLB_CTRL
	93	bl i_dll_wait @ wait for possible lock
	94
	95	/* set up for return, DDR should be good */
	96	str r10, [r0] @ write dll_status and return counter
	97	ldmfd sp!, {r0 - r12, pc} @ restore regs and return
	98
	99	/* ensure the DLL has relocked */
	100	i_dll_wait:
	101	mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
	102	i_dll_delay:
	103	subs r4, r4, #0x1
	104	bne i_dll_delay
	105	mov pc, lr
	106
	107	/*
	108	* shift up or down voltage, use R9 as input to tell level.
	109	* wait for it to finish, use 32k sync counter, 1tick=31uS.
	110	*/
	111	voltage_shift:
c2d43e39	112	ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
1dbae815 TL	113	ldr r5, [r4] @ get value.
	114	ldr r6, prcm_mask_val @ get value of mask
	115	and r5, r5, r6 @ apply mask to clear bits
	116	orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
	117	str r5, [r4] @ set up for change.
	118	mov r3, #0x4000 @ get val for force
	119	orr r5, r5, r3 @ build value for force
	120	str r5, [r4] @ Force transition to L1
	121
c2d43e39	122	ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
1dbae815 TL	123	ldr r5, [r3] @ get value
	124	add r5, r5, #0x3 @ give it at most 93uS
	125	volt_delay:
	126	ldr r7, [r3] @ get timer value
	127	cmp r5, r7 @ time up?
	128	bhi volt_delay @ not yet->branch
	129	mov pc, lr @ back to caller.
	130
c2d43e39	131	omap242x_sdi_cm_clksel2_pll:
44595982	132	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
c2d43e39	133	omap242x_sdi_sdrc_dlla_ctrl:
44595982	134	.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
c2d43e39	135	omap242x_sdi_prcm_voltctrl:
8e3bd351	136	.word OMAP2420_PRCM_VOLTCTRL
1dbae815 TL	137	prcm_mask_val:
1dbae815 TL	138	.word 0xFFFF3FFC
c2d43e39	139	omap242x_sdi_timer_32ksynct_cr:
233fd64e	140	.word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
c2d43e39 TL	141	ENTRY(omap242x_sram_ddr_init_sz)
c2d43e39 TL	142	.word . - omap242x_sram_ddr_init
1dbae815 TL	143
	144	/*
	145	* Reprograms memory timings.
	146	* r0 = [PRCM_FULL \| PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR \| SDR]
	147	* PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
	148	*/
b6338bdc	149	.align 3
c2d43e39	150	ENTRY(omap242x_sram_reprogram_sdrc)
1dbae815 TL	151	stmfd sp!, {r0 - r10, lr} @ save registers on stack
	152	mov r3, #0x0 @ clear for mrc call
	153	mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
	154	nop
	155	nop
c2d43e39	156	ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
1dbae815 TL	157	ldr r5, [r6] @ get value
	158	mov r5, r5, lsr #8 @ isolate rfr field and drop burst
	159
	160	cmp r0, #0x1 @ going to half speed?
	161	movne r9, #0x0 @ if up set flag up for pre up, hi volt
	162
	163	blne voltage_shift_c @ adjust voltage
	164
	165	cmp r0, #0x1 @ going to half speed (post branch link)
	166	moveq r5, r5, lsr #1 @ divide by 2 if to half
	167	movne r5, r5, lsl #1 @ mult by 2 if to full
	168	mov r5, r5, lsl #8 @ put rfr field back into place
	169	add r5, r5, #0x1 @ turn on burst of 1
c2d43e39	170	ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
1dbae815 TL	171	ldr r3, [r4] @ get curr value
	172	orr r3, r3, #0x3
	173	bic r3, r3, #0x3 @ clear lower bits
	174	orr r3, r3, r0 @ new state value
	175	str r3, [r4] @ set new state (pll/x, x=1 or 2)
	176	nop
	177	nop
	178
	179	moveq r9, #0x1 @ if speed down, post down, drop volt
	180	bleq voltage_shift_c
	181
	182	mcr p15, 0, r3, c7, c10, 4 @ memory barrier
	183	str r5, [r6] @ set new RFR_1 value
	184	add r6, r6, #0x30 @ get RFR_2 addr
	185	str r5, [r6] @ set RFR_2
	186	nop
	187	cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
	188	bne freq_out @ leave if SDR, no DLL function
	189
	190	/* With DDR, we need to take care of the DLL for the frequency change */
c2d43e39	191	ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
1dbae815 TL	192	str r1, [r2] @ write out new SDRC_DLLA_CTRL
	193	add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
	194	str r1, [r2] @ commit to SDRC_DLLB_CTRL
	195	mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
	196	dll_wait:
	197	subs r1, r1, #0x1
	198	bne dll_wait
	199	freq_out:
	200	ldmfd sp!, {r0 - r10, pc} @ restore regs and return
	201
	202	/*
	203	* shift up or down voltage, use R9 as input to tell level.
	204	* wait for it to finish, use 32k sync counter, 1tick=31uS.
	205	*/
	206	voltage_shift_c:
c2d43e39	207	ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
1dbae815 TL	208	ldr r8, [r10] @ get value
	209	ldr r7, ddr_prcm_mask_val @ get value of mask
	210	and r8, r8, r7 @ apply mask to clear bits
	211	orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
	212	str r8, [r10] @ set up for change.
	213	mov r7, #0x4000 @ get val for force
	214	orr r8, r8, r7 @ build value for force
	215	str r8, [r10] @ Force transition to L1
	216
c2d43e39	217	ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter
1dbae815 TL	218	ldr r8, [r10] @ get value
	219	add r8, r8, #0x2 @ give it at most 62uS (min 31+)
	220	volt_delay_c:
	221	ldr r7, [r10] @ get timer value
	222	cmp r8, r7 @ time up?
	223	bhi volt_delay_c @ not yet->branch
	224	mov pc, lr @ back to caller
	225
c2d43e39	226	omap242x_srs_cm_clksel2_pll:
44595982	227	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
c2d43e39	228	omap242x_srs_sdrc_dlla_ctrl:
44595982	229	.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
c2d43e39	230	omap242x_srs_sdrc_rfr_ctrl:
44595982	231	.word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
c2d43e39	232	omap242x_srs_prcm_voltctrl:
8e3bd351	233	.word OMAP2420_PRCM_VOLTCTRL
1dbae815 TL	234	ddr_prcm_mask_val:
1dbae815 TL	235	.word 0xFFFF3FFC
c2d43e39	236	omap242x_srs_timer_32ksynct:
233fd64e	237	.word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1dbae815	238
c2d43e39 TL	239	ENTRY(omap242x_sram_reprogram_sdrc_sz)
c2d43e39 TL	240	.word . - omap242x_sram_reprogram_sdrc
1dbae815 TL	241
	242	/*
	243	* Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
	244	*/
b6338bdc	245	.align 3
c2d43e39	246	ENTRY(omap242x_sram_set_prcm)
1dbae815 TL	247	stmfd sp!, {r0-r12, lr} @ regs to stack
	248	adr r4, pbegin @ addr of preload start
	249	adr r8, pend @ addr of preload end
	250	mcrr p15, 1, r8, r4, c12 @ preload into icache
	251	pbegin:
	252	/* move into fast relock bypass */
c2d43e39	253	ldr r8, omap242x_ssp_pll_ctl @ get addr
1dbae815 TL	254	ldr r5, [r8] @ get val
	255	mvn r6, #0x3 @ clear mask
	256	and r5, r5, r6 @ clear field
	257	orr r7, r5, #0x2 @ fast relock val
	258	str r7, [r8] @ go to fast relock
c2d43e39	259	ldr r4, omap242x_ssp_pll_stat @ addr of stat
1dbae815 TL	260	block:
	261	/* wait for bypass */
	262	ldr r8, [r4] @ stat value
	263	and r8, r8, #0x3 @ mask for stat
	264	cmp r8, #0x1 @ there yet
	265	bne block @ loop if not
	266
	267	/* set new dpll dividers _after_ in bypass */
c2d43e39	268	ldr r4, omap242x_ssp_pll_div @ get addr
1dbae815 TL	269	str r0, [r4] @ set dpll ctrl val
1dbae815 TL	270
c2d43e39	271	ldr r4, omap242x_ssp_set_config @ get addr
1dbae815 TL	272	mov r8, #1 @ valid cfg msk
	273	str r8, [r4] @ make dividers take
	274
	275	mov r4, #100 @ dead spin a bit
	276	wait_a_bit:
	277	subs r4, r4, #1 @ dec loop
	278	bne wait_a_bit @ delay done?
	279
	280	/* check if staying in bypass */
	281	cmp r2, #0x1 @ stay in bypass?
	282	beq pend @ jump over dpll relock
	283
	284	/* relock DPLL with new vals */
c2d43e39 TL	285	ldr r5, omap242x_ssp_pll_stat @ get addr
c2d43e39 TL	286	ldr r4, omap242x_ssp_pll_ctl @ get addr
1dbae815 TL	287	orr r8, r7, #0x3 @ val for lock dpll
	288	str r8, [r4] @ set val
	289	mov r0, #1000 @ dead spin a bit
	290	wait_more:
	291	subs r0, r0, #1 @ dec loop
	292	bne wait_more @ delay done?
	293	wait_lock:
	294	ldr r8, [r5] @ get lock val
	295	and r8, r8, #3 @ isolate field
	296	cmp r8, #2 @ locked?
	297	bne wait_lock @ wait if not
	298	pend:
	299	/* update memory timings & briefly lock dll */
c2d43e39	300	ldr r4, omap242x_ssp_sdrc_rfr @ get addr
1dbae815	301	str r1, [r4] @ update refresh timing
c2d43e39	302	ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl
1dbae815 TL	303	ldr r10, [r11] @ get current val
	304	mvn r9, #0x4 @ mask to get clear bit2
	305	and r10, r10, r9 @ clear bit2 for lock mode
	306	orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
	307	str r10, [r11] @ commit to DLLA_CTRL
	308	add r11, r11, #0x8 @ move to dllb
	309	str r10, [r11] @ hit DLLB also
	310
	311	mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
	312	wait_dll_lock:
	313	subs r4, r4, #0x1
	314	bne wait_dll_lock
	315	nop
	316	ldmfd sp!, {r0-r12, pc} @ restore regs and return
	317
c2d43e39	318	omap242x_ssp_set_config:
8e3bd351	319	.word OMAP2420_PRCM_CLKCFG_CTRL
c2d43e39 TL	320	omap242x_ssp_pll_ctl:
	321	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
	322	omap242x_ssp_pll_stat:
	323	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
	324	omap242x_ssp_pll_div:
	325	.word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
	326	omap242x_ssp_sdrc_rfr:
44595982	327	.word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
c2d43e39	328	omap242x_ssp_dlla_ctrl:
44595982	329	.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
1dbae815	330
c2d43e39 TL	331	ENTRY(omap242x_sram_set_prcm_sz)
c2d43e39 TL	332	.word . - omap242x_sram_set_prcm