[deliverable/linux.git] / arch / arm / mach-omap2 / sram34xx.S

/*
 * linux/arch/arm/mach-omap3/sram.S
 *
 * Omap3 specific functions that need to be run in internal SRAM
 *
 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
 * Copyright (C) 2008 Nokia Corporation
 *
 * Rajendra Nayak <rnayak@ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>

#include <mach/io.h>

#include "sdrc.h"
#include "cm.h"

	.text

/* r1 parameters */
#define SDRC_NO_UNLOCK_DLL		0x0
#define SDRC_UNLOCK_DLL			0x1

/* SDRC_DLLA_CTRL bit settings */
#define FIXEDDELAY_SHIFT		24
#define FIXEDDELAY_MASK			(0xff << FIXEDDELAY_SHIFT)
#define DLLIDLE_MASK			0x4

/*
 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
 * FIXEDDELAY should be initialized to 0xf.  This apparently was
 * empirically determined during process testing, so no derivation
 * was provided.
 */
#define FIXEDDELAY_DEFAULT		(0x0f << FIXEDDELAY_SHIFT)

/* SDRC_DLLA_STATUS bit settings */
#define LOCKSTATUS_MASK			0x4

/* SDRC_POWER bit settings */
#define SRFRONIDLEREQ_MASK		0x40

/* CM_IDLEST1_CORE bit settings */
#define ST_SDRC_MASK			0x2

/* CM_ICLKEN1_CORE bit settings */
#define EN_SDRC_MASK			0x2

/* CM_CLKSEL1_PLL bit settings */
#define CORE_DPLL_CLKOUT_DIV_SHIFT	0x1b

/*
 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
 *
 * Params passed in registers:
 *  r0 = new M2 divider setting (only 1 and 2 supported right now)
 *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
 *      SDRC rates < 83MHz
 *  r2 = number of MPU cycles to wait for SDRC to stabilize after
 *      reprogramming the SDRC when switching to a slower MPU speed
 *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
 *
 * Params passed via the stack. The needed params will be copied in SRAM
 *  before use by the code in SRAM (SDRAM is not accessible during SDRC
 *  reconfiguration):
 *  new SDRC_RFR_CTRL_0 register contents
 *  new SDRC_ACTIM_CTRL_A_0 register contents
 *  new SDRC_ACTIM_CTRL_B_0 register contents
 *  new SDRC_MR_0 register value
 *  new SDRC_RFR_CTRL_1 register contents
 *  new SDRC_ACTIM_CTRL_A_1 register contents
 *  new SDRC_ACTIM_CTRL_B_1 register contents
 *  new SDRC_MR_1 register value
 *
 * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
 * the SDRC CS1 registers
 *
 * NOTE: This code no longer attempts to program the SDRC AC timing and MR
 * registers.  This is because the code currently cannot ensure that all
 * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
 * SDRAM when the registers are written.  If the registers are changed while
 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
 * may enter an unpredictable state.  In the future, the intent is to
 * re-enable this code in cases where we can ensure that no initiators are
 * touching the SDRAM.  Until that time, users who know that their use case
 * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
 * option.
 */
ENTRY(omap3_sram_configure_core_dpll)
	stmfd	sp!, {r1-r12, lr}	@ store regs to stack

					@ pull the extra args off the stack
					@  and store them in SRAM
	ldr	r4, [sp, #52]
	str     r4, omap_sdrc_rfr_ctrl_0_val
	ldr	r4, [sp, #56]
	str     r4, omap_sdrc_actim_ctrl_a_0_val
	ldr	r4, [sp, #60]
	str     r4, omap_sdrc_actim_ctrl_b_0_val
	ldr	r4, [sp, #64]
	str     r4, omap_sdrc_mr_0_val
	ldr	r4, [sp, #68]
	str     r4, omap_sdrc_rfr_ctrl_1_val
	cmp	r4, #0			@ if SDRC_RFR_CTRL_1 is 0,
	beq	skip_cs1_params		@  do not use cs1 params
	ldr	r4, [sp, #72]
	str     r4, omap_sdrc_actim_ctrl_a_1_val
	ldr	r4, [sp, #76]
	str     r4, omap_sdrc_actim_ctrl_b_1_val
	ldr	r4, [sp, #80]
	str     r4, omap_sdrc_mr_1_val
skip_cs1_params:
	dsb				@ flush buffered writes to interconnect

	cmp	r3, #1			@ if increasing SDRC clk rate,
	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
	bleq	unlock_dll
	blne	lock_dll
	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
	mov	r12, r2
	bl	wait_clk_stable		@ wait for SDRC to stabilize
	bl	enable_sdrc		@ take SDRC out of idle
	cmp	r1, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
	bleq	wait_dll_unlock
	blne	wait_dll_lock
	cmp	r3, #1			@ if increasing SDRC clk rate,
	beq	return_to_sdram		@ return to SDRAM code, otherwise,
	bl	configure_sdrc		@ reprogram SDRC regs now
return_to_sdram:
	isb				@ prevent speculative exec past here
	mov 	r0, #0 			@ return value
	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return
unlock_dll:
	ldr	r11, omap3_sdrc_dlla_ctrl
	ldr	r12, [r11]
	bic	r12, r12, #FIXEDDELAY_MASK
	orr	r12, r12, #FIXEDDELAY_DEFAULT
	orr	r12, r12, #DLLIDLE_MASK
	str	r12, [r11]		@ (no OCP barrier needed)
	bx	lr
lock_dll:
	ldr	r11, omap3_sdrc_dlla_ctrl
	ldr	r12, [r11]
	bic	r12, r12, #DLLIDLE_MASK
	str	r12, [r11]		@ (no OCP barrier needed)
	bx	lr
sdram_in_selfrefresh:
	ldr	r11, omap3_sdrc_power	@ read the SDRC_POWER register
	ldr	r12, [r11]		@ read the contents of SDRC_POWER
	mov	r9, r12			@ keep a copy of SDRC_POWER bits
	orr 	r12, r12, #SRFRONIDLEREQ_MASK	@ enable self refresh on idle
	str 	r12, [r11]		@ write back to SDRC_POWER register
	ldr	r12, [r11]		@ posted-write barrier for SDRC
idle_sdrc:
	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
	ldr	r12, [r11]
	bic	r12, r12, #EN_SDRC_MASK		@ disable iclk bit for SDRC
	str 	r12, [r11]
wait_sdrc_idle:
	ldr 	r11, omap3_cm_idlest1_core
	ldr 	r12, [r11]
	and 	r12, r12, #ST_SDRC_MASK		@ check for SDRC idle
	cmp 	r12, #ST_SDRC_MASK
	bne 	wait_sdrc_idle
	bx 	lr
configure_core_dpll:
	ldr 	r11, omap3_cm_clksel1_pll
	ldr	r12, [r11]
	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
	and	r12, r12, r10
	orr	r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
	str	r12, [r11]
	ldr	r12, [r11]		@ posted-write barrier for CM
	bx	lr
wait_clk_stable:
	subs 	r12, r12, #1
	bne	wait_clk_stable
	bx	lr
enable_sdrc:
	ldr 	r11, omap3_cm_iclken1_core
	ldr	r12, [r11]
	orr 	r12, r12, #EN_SDRC_MASK		@ enable iclk bit for SDRC
	str 	r12, [r11]
wait_sdrc_idle1:
	ldr 	r11, omap3_cm_idlest1_core
	ldr	r12, [r11]
	and 	r12, r12, #ST_SDRC_MASK
	cmp	r12, #0
	bne	wait_sdrc_idle1
restore_sdrc_power_val:
	ldr	r11, omap3_sdrc_power
	str	r9, [r11]		@ restore SDRC_POWER, no barrier needed
	bx	lr
wait_dll_lock:
	ldr	r11, omap3_sdrc_dlla_status
	ldr	r12, [r11]
	and 	r12, r12, #LOCKSTATUS_MASK
	cmp	r12, #LOCKSTATUS_MASK
	bne	wait_dll_lock
	bx	lr
wait_dll_unlock:
	ldr	r11, omap3_sdrc_dlla_status
	ldr	r12, [r11]
	and	r12, r12, #LOCKSTATUS_MASK
	cmp	r12, #0x0
	bne	wait_dll_unlock
	bx	lr
configure_sdrc:
	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
	str	r12, [r11]			@ store
#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
	ldr	r11, omap3_sdrc_actim_ctrl_a_0
	str	r12, [r11]
	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
	ldr	r11, omap3_sdrc_actim_ctrl_b_0
	str	r12, [r11]
	ldr	r12, omap_sdrc_mr_0_val
	ldr	r11, omap3_sdrc_mr_0
	str	r12, [r11]
#endif
	ldr	r12, omap_sdrc_rfr_ctrl_1_val
	cmp	r12, #0			@ if SDRC_RFR_CTRL_1 is 0,
	beq	skip_cs1_prog		@  do not program cs1 params
	ldr	r11, omap3_sdrc_rfr_ctrl_1
	str	r12, [r11]
#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
	ldr	r11, omap3_sdrc_actim_ctrl_a_1
	str	r12, [r11]
	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
	ldr	r11, omap3_sdrc_actim_ctrl_b_1
	str	r12, [r11]
	ldr	r12, omap_sdrc_mr_1_val
	ldr	r11, omap3_sdrc_mr_1
	str	r12, [r11]
#endif
skip_cs1_prog:
	ldr	r12, [r11]		@ posted-write barrier for SDRC
	bx	lr

omap3_sdrc_power:
	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
omap3_cm_clksel1_pll:
	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
omap3_cm_idlest1_core:
	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
omap3_cm_iclken1_core:
	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)

omap3_sdrc_rfr_ctrl_0:
	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap3_sdrc_rfr_ctrl_1:
	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
omap3_sdrc_actim_ctrl_a_0:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrl_a_1:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
omap3_sdrc_actim_ctrl_b_0:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
omap3_sdrc_actim_ctrl_b_1:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
omap3_sdrc_mr_0:
	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
omap3_sdrc_mr_1:
	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
omap_sdrc_rfr_ctrl_0_val:
	.word 0xDEADBEEF
omap_sdrc_rfr_ctrl_1_val:
	.word 0xDEADBEEF
omap_sdrc_actim_ctrl_a_0_val:
	.word 0xDEADBEEF
omap_sdrc_actim_ctrl_a_1_val:
	.word 0xDEADBEEF
omap_sdrc_actim_ctrl_b_0_val:
	.word 0xDEADBEEF
omap_sdrc_actim_ctrl_b_1_val:
	.word 0xDEADBEEF
omap_sdrc_mr_0_val:
	.word 0xDEADBEEF
omap_sdrc_mr_1_val:
	.word 0xDEADBEEF

omap3_sdrc_dlla_status:
	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl:
	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
core_m2_mask_val:
	.word 0x07FFFFFF

ENTRY(omap3_sram_configure_core_dpll_sz)
	.word	. - omap3_sram_configure_core_dpll
Commit	Line	Data
cc26b3b0 SMK	1	/*
	2	* linux/arch/arm/mach-omap3/sram.S
	3	*
	4	* Omap3 specific functions that need to be run in internal SRAM
	5	*
4267b5d1 PW	6	* Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
4267b5d1 PW	7	* Copyright (C) 2008 Nokia Corporation
cc26b3b0	8	*
4267b5d1	9	* Rajendra Nayak <rnayak@ti.com>
cc26b3b0	10	* Richard Woodruff <r-woodruff2@ti.com>
4267b5d1	11	* Paul Walmsley
cc26b3b0 SMK	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28	#include <linux/linkage.h>
	29	#include <asm/assembler.h>
	30	#include <mach/hardware.h>
	31
	32	#include <mach/io.h>
	33
	34	#include "sdrc.h"
	35	#include "cm.h"
	36
	37	.text
	38
58cda884	39	/* r1 parameters */
df14e474 PW	40	#define SDRC_NO_UNLOCK_DLL 0x0
	41	#define SDRC_UNLOCK_DLL 0x1
	42
	43	/* SDRC_DLLA_CTRL bit settings */
7b7bcefa PW	44	#define FIXEDDELAY_SHIFT 24
7b7bcefa PW	45	#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
df14e474 PW	46	#define DLLIDLE_MASK 0x4
df14e474 PW	47
7b7bcefa PW	48	/*
	49	* SDRC_DLLA_CTRL default values: TI hardware team indicates that
	50	* FIXEDDELAY should be initialized to 0xf. This apparently was
	51	* empirically determined during process testing, so no derivation
	52	* was provided.
	53	*/
	54	#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
	55
df14e474 PW	56	/* SDRC_DLLA_STATUS bit settings */
	57	#define LOCKSTATUS_MASK 0x4
	58
	59	/* SDRC_POWER bit settings */
	60	#define SRFRONIDLEREQ_MASK 0x40
df14e474 PW	61
	62	/* CM_IDLEST1_CORE bit settings */
	63	#define ST_SDRC_MASK 0x2
	64
	65	/* CM_ICLKEN1_CORE bit settings */
	66	#define EN_SDRC_MASK 0x2
	67
	68	/* CM_CLKSEL1_PLL bit settings */
	69	#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
	70
cc26b3b0	71	/*
4267b5d1	72	* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
58cda884 JP	73	*
	74	* Params passed in registers:
	75	* r0 = new M2 divider setting (only 1 and 2 supported right now)
	76	* r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
4519c2bf	77	* SDRC rates < 83MHz
58cda884	78	* r2 = number of MPU cycles to wait for SDRC to stabilize after
c9812d04	79	* reprogramming the SDRC when switching to a slower MPU speed
58cda884 JP	80	* r3 = increasing SDRC rate? (1 = yes, 0 = no)
	81	*
	82	* Params passed via the stack. The needed params will be copied in SRAM
	83	* before use by the code in SRAM (SDRAM is not accessible during SDRC
	84	* reconfiguration):
	85	* new SDRC_RFR_CTRL_0 register contents
	86	* new SDRC_ACTIM_CTRL_A_0 register contents
	87	* new SDRC_ACTIM_CTRL_B_0 register contents
	88	* new SDRC_MR_0 register value
	89	* new SDRC_RFR_CTRL_1 register contents
	90	* new SDRC_ACTIM_CTRL_A_1 register contents
	91	* new SDRC_ACTIM_CTRL_B_1 register contents
	92	* new SDRC_MR_1 register value
c9812d04	93	*
18862cbe PW	94	* If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
	95	* the SDRC CS1 registers
	96	*
	97	* NOTE: This code no longer attempts to program the SDRC AC timing and MR
	98	* registers. This is because the code currently cannot ensure that all
	99	* L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
	100	* SDRAM when the registers are written. If the registers are changed while
	101	* an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
	102	* may enter an unpredictable state. In the future, the intent is to
	103	* re-enable this code in cases where we can ensure that no initiators are
	104	* touching the SDRAM. Until that time, users who know that their use case
	105	* can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
	106	* option.
cc26b3b0 SMK	107	*/
	108	ENTRY(omap3_sram_configure_core_dpll)
	109	stmfd sp!, {r1-r12, lr} @ store regs to stack
58cda884 JP	110
	111	@ pull the extra args off the stack
	112	@ and store them in SRAM
	113	ldr r4, [sp, #52]
	114	str r4, omap_sdrc_rfr_ctrl_0_val
	115	ldr r4, [sp, #56]
	116	str r4, omap_sdrc_actim_ctrl_a_0_val
	117	ldr r4, [sp, #60]
	118	str r4, omap_sdrc_actim_ctrl_b_0_val
	119	ldr r4, [sp, #64]
	120	str r4, omap_sdrc_mr_0_val
	121	ldr r4, [sp, #68]
	122	str r4, omap_sdrc_rfr_ctrl_1_val
	123	cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
	124	beq skip_cs1_params @ do not use cs1 params
	125	ldr r4, [sp, #72]
	126	str r4, omap_sdrc_actim_ctrl_a_1_val
	127	ldr r4, [sp, #76]
	128	str r4, omap_sdrc_actim_ctrl_b_1_val
	129	ldr r4, [sp, #80]
	130	str r4, omap_sdrc_mr_1_val
	131	skip_cs1_params:
69d4255b	132	dsb @ flush buffered writes to interconnect
58cda884 JP	133
58cda884 JP	134	cmp r3, #1 @ if increasing SDRC clk rate,
3afec633	135	bleq configure_sdrc @ program the SDRC regs early (for RFR)
58cda884	136	cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
4519c2bf	137	bleq unlock_dll
cc26b3b0	138	blne lock_dll
4267b5d1 PW	139	bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
4267b5d1 PW	140	bl configure_core_dpll @ change the DPLL3 M2 divider
df56556e RN	141	mov r12, r2
df56556e RN	142	bl wait_clk_stable @ wait for SDRC to stabilize
4267b5d1	143	bl enable_sdrc @ take SDRC out of idle
58cda884	144	cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
4519c2bf	145	bleq wait_dll_unlock
cc26b3b0	146	blne wait_dll_lock
58cda884	147	cmp r3, #1 @ if increasing SDRC clk rate,
4267b5d1 PW	148	beq return_to_sdram @ return to SDRAM code, otherwise,
4267b5d1 PW	149	bl configure_sdrc @ reprogram SDRC regs now
c9812d04	150	return_to_sdram:
69d4255b	151	isb @ prevent speculative exec past here
cc26b3b0 SMK	152	mov r0, #0 @ return value
	153	ldmfd sp!, {r1-r12, pc} @ restore regs and return
	154	unlock_dll:
b2abb271 PW	155	ldr r11, omap3_sdrc_dlla_ctrl
b2abb271 PW	156	ldr r12, [r11]
8ff120e5	157	bic r12, r12, #FIXEDDELAY_MASK
7b7bcefa	158	orr r12, r12, #FIXEDDELAY_DEFAULT
df14e474	159	orr r12, r12, #DLLIDLE_MASK
b2abb271	160	str r12, [r11] @ (no OCP barrier needed)
cc26b3b0 SMK	161	bx lr
cc26b3b0 SMK	162	lock_dll:
b2abb271 PW	163	ldr r11, omap3_sdrc_dlla_ctrl
b2abb271 PW	164	ldr r12, [r11]
df14e474	165	bic r12, r12, #DLLIDLE_MASK
b2abb271	166	str r12, [r11] @ (no OCP barrier needed)
cc26b3b0 SMK	167	bx lr
cc26b3b0 SMK	168	sdram_in_selfrefresh:
b2abb271 PW	169	ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
	170	ldr r12, [r11] @ read the contents of SDRC_POWER
	171	mov r9, r12 @ keep a copy of SDRC_POWER bits
df14e474	172	orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
b2abb271 PW	173	str r12, [r11] @ write back to SDRC_POWER register
b2abb271 PW	174	ldr r12, [r11] @ posted-write barrier for SDRC
4267b5d1	175	idle_sdrc:
b2abb271 PW	176	ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
b2abb271 PW	177	ldr r12, [r11]
df14e474	178	bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
b2abb271	179	str r12, [r11]
cc26b3b0	180	wait_sdrc_idle:
b2abb271 PW	181	ldr r11, omap3_cm_idlest1_core
b2abb271 PW	182	ldr r12, [r11]
df14e474 PW	183	and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
df14e474 PW	184	cmp r12, #ST_SDRC_MASK
cc26b3b0 SMK	185	bne wait_sdrc_idle
	186	bx lr
	187	configure_core_dpll:
b2abb271 PW	188	ldr r11, omap3_cm_clksel1_pll
	189	ldr r12, [r11]
	190	ldr r10, core_m2_mask_val @ modify m2 for core dpll
	191	and r12, r12, r10
58cda884	192	orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
b2abb271 PW	193	str r12, [r11]
b2abb271 PW	194	ldr r12, [r11] @ posted-write barrier for CM
cc26b3b0 SMK	195	bx lr
cc26b3b0 SMK	196	wait_clk_stable:
b2abb271	197	subs r12, r12, #1
cc26b3b0	198	bne wait_clk_stable
cc26b3b0 SMK	199	bx lr
cc26b3b0 SMK	200	enable_sdrc:
b2abb271 PW	201	ldr r11, omap3_cm_iclken1_core
b2abb271 PW	202	ldr r12, [r11]
df14e474	203	orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
b2abb271	204	str r12, [r11]
cc26b3b0	205	wait_sdrc_idle1:
b2abb271 PW	206	ldr r11, omap3_cm_idlest1_core
b2abb271 PW	207	ldr r12, [r11]
df14e474	208	and r12, r12, #ST_SDRC_MASK
b2abb271	209	cmp r12, #0
cc26b3b0	210	bne wait_sdrc_idle1
fa0406a8	211	restore_sdrc_power_val:
b2abb271 PW	212	ldr r11, omap3_sdrc_power
b2abb271 PW	213	str r9, [r11] @ restore SDRC_POWER, no barrier needed
cc26b3b0 SMK	214	bx lr
cc26b3b0 SMK	215	wait_dll_lock:
b2abb271 PW	216	ldr r11, omap3_sdrc_dlla_status
b2abb271 PW	217	ldr r12, [r11]
df14e474 PW	218	and r12, r12, #LOCKSTATUS_MASK
df14e474 PW	219	cmp r12, #LOCKSTATUS_MASK
cc26b3b0 SMK	220	bne wait_dll_lock
	221	bx lr
	222	wait_dll_unlock:
b2abb271 PW	223	ldr r11, omap3_sdrc_dlla_status
b2abb271 PW	224	ldr r12, [r11]
df14e474	225	and r12, r12, #LOCKSTATUS_MASK
b2abb271	226	cmp r12, #0x0
cc26b3b0 SMK	227	bne wait_dll_unlock
	228	bx lr
	229	configure_sdrc:
58cda884 JP	230	ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
	231	ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
	232	str r12, [r11] @ store
18862cbe	233	#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
58cda884 JP	234	ldr r12, omap_sdrc_actim_ctrl_a_0_val
	235	ldr r11, omap3_sdrc_actim_ctrl_a_0
	236	str r12, [r11]
	237	ldr r12, omap_sdrc_actim_ctrl_b_0_val
	238	ldr r11, omap3_sdrc_actim_ctrl_b_0
	239	str r12, [r11]
	240	ldr r12, omap_sdrc_mr_0_val
d0ba3922	241	ldr r11, omap3_sdrc_mr_0
58cda884	242	str r12, [r11]
18862cbe	243	#endif
58cda884 JP	244	ldr r12, omap_sdrc_rfr_ctrl_1_val
	245	cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
	246	beq skip_cs1_prog @ do not program cs1 params
	247	ldr r11, omap3_sdrc_rfr_ctrl_1
	248	str r12, [r11]
18862cbe	249	#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
58cda884 JP	250	ldr r12, omap_sdrc_actim_ctrl_a_1_val
	251	ldr r11, omap3_sdrc_actim_ctrl_a_1
	252	str r12, [r11]
	253	ldr r12, omap_sdrc_actim_ctrl_b_1_val
	254	ldr r11, omap3_sdrc_actim_ctrl_b_1
	255	str r12, [r11]
	256	ldr r12, omap_sdrc_mr_1_val
	257	ldr r11, omap3_sdrc_mr_1
	258	str r12, [r11]
18862cbe	259	#endif
58cda884 JP	260	skip_cs1_prog:
58cda884 JP	261	ldr r12, [r11] @ posted-write barrier for SDRC
cc26b3b0 SMK	262	bx lr
	263
	264	omap3_sdrc_power:
	265	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
	266	omap3_cm_clksel1_pll:
	267	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
	268	omap3_cm_idlest1_core:
	269	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
	270	omap3_cm_iclken1_core:
	271	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
58cda884 JP	272
58cda884 JP	273	omap3_sdrc_rfr_ctrl_0:
cc26b3b0	274	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
58cda884 JP	275	omap3_sdrc_rfr_ctrl_1:
	276	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
	277	omap3_sdrc_actim_ctrl_a_0:
cc26b3b0	278	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
58cda884 JP	279	omap3_sdrc_actim_ctrl_a_1:
	280	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
	281	omap3_sdrc_actim_ctrl_b_0:
cc26b3b0	282	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
58cda884 JP	283	omap3_sdrc_actim_ctrl_b_1:
58cda884 JP	284	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
d0ba3922 PW	285	omap3_sdrc_mr_0:
d0ba3922 PW	286	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
58cda884 JP	287	omap3_sdrc_mr_1:
	288	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
	289	omap_sdrc_rfr_ctrl_0_val:
	290	.word 0xDEADBEEF
	291	omap_sdrc_rfr_ctrl_1_val:
	292	.word 0xDEADBEEF
	293	omap_sdrc_actim_ctrl_a_0_val:
	294	.word 0xDEADBEEF
	295	omap_sdrc_actim_ctrl_a_1_val:
	296	.word 0xDEADBEEF
	297	omap_sdrc_actim_ctrl_b_0_val:
	298	.word 0xDEADBEEF
	299	omap_sdrc_actim_ctrl_b_1_val:
	300	.word 0xDEADBEEF
	301	omap_sdrc_mr_0_val:
	302	.word 0xDEADBEEF
	303	omap_sdrc_mr_1_val:
	304	.word 0xDEADBEEF
	305
cc26b3b0 SMK	306	omap3_sdrc_dlla_status:
	307	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
	308	omap3_sdrc_dlla_ctrl:
	309	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
	310	core_m2_mask_val:
	311	.word 0x07FFFFFF
	312
	313	ENTRY(omap3_sram_configure_core_dpll_sz)
	314	.word . - omap3_sram_configure_core_dpll
58cda884	315