[deliverable/linux.git] / arch / arm / mach-omap2 / sram34xx.S

/*
 * linux/arch/arm/mach-omap3/sram.S
 *
 * Omap3 specific functions that need to be run in internal SRAM
 *
 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
 * Copyright (C) 2008 Nokia Corporation
 *
 * Rajendra Nayak <rnayak@ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>

#include <mach/io.h>

#include "sdrc.h"
#include "cm.h"

	.text

/* r4 parameters */
#define SDRC_NO_UNLOCK_DLL		0x0
#define SDRC_UNLOCK_DLL			0x1

/* SDRC_DLLA_CTRL bit settings */
#define FIXEDDELAY_SHIFT		24
#define FIXEDDELAY_MASK			(0xff << FIXEDDELAY_SHIFT)
#define DLLIDLE_MASK			0x4

/*
 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
 * FIXEDDELAY should be initialized to 0xf.  This apparently was
 * empirically determined during process testing, so no derivation
 * was provided.
 */
#define FIXEDDELAY_DEFAULT		(0x0f << FIXEDDELAY_SHIFT)

/* SDRC_DLLA_STATUS bit settings */
#define LOCKSTATUS_MASK			0x4

/* SDRC_POWER bit settings */
#define SRFRONIDLEREQ_MASK		0x40
#define PWDENA_MASK			0x4

/* CM_IDLEST1_CORE bit settings */
#define ST_SDRC_MASK			0x2

/* CM_ICLKEN1_CORE bit settings */
#define EN_SDRC_MASK			0x2

/* CM_CLKSEL1_PLL bit settings */
#define CORE_DPLL_CLKOUT_DIV_SHIFT	0x1b

/*
 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
 * r0 = new SDRC_RFR_CTRL register contents
 * r1 = new SDRC_ACTIM_CTRLA register contents
 * r2 = new SDRC_ACTIM_CTRLB register contents
 * r3 = new M2 divider setting (only 1 and 2 supported right now)
 * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
 *      SDRC rates < 83MHz
 * r5 = number of MPU cycles to wait for SDRC to stabilize after
 *      reprogramming the SDRC when switching to a slower MPU speed
 * r6 = new SDRC_MR_0 register value
 * r7 = increasing SDRC rate? (1 = yes, 0 = no)
 *
 */
ENTRY(omap3_sram_configure_core_dpll)
	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
	ldr	r4, [sp, #52]		@ pull extra args off the stack
	ldr	r5, [sp, #56]		@ load extra args from the stack
	ldr	r6, [sp, #60]		@ load extra args from the stack
	ldr	r7, [sp, #64]		@ load extra args from the stack
	dsb				@ flush buffered writes to interconnect
	cmp	r7, #1			@ if increasing SDRC clk rate,
	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
	bleq	unlock_dll
	blne	lock_dll
	bl	sdram_in_selfrefresh	@ put SDRAM in self refresh, idle SDRC
	bl 	configure_core_dpll	@ change the DPLL3 M2 divider
	bl	enable_sdrc		@ take SDRC out of idle
	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
	bleq	wait_dll_unlock
	blne	wait_dll_lock
	cmp	r7, #1			@ if increasing SDRC clk rate,
	beq	return_to_sdram		@ return to SDRAM code, otherwise,
	bl	configure_sdrc		@ reprogram SDRC regs now
	mov	r12, r5
	bl	wait_clk_stable		@ wait for SDRC to stabilize
return_to_sdram:
	isb				@ prevent speculative exec past here
	mov 	r0, #0 			@ return value
	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return
unlock_dll:
	ldr	r11, omap3_sdrc_dlla_ctrl
	ldr	r12, [r11]
	and	r12, r12, #FIXEDDELAY_MASK
	orr	r12, r12, #FIXEDDELAY_DEFAULT
	orr	r12, r12, #DLLIDLE_MASK
	str	r12, [r11]		@ (no OCP barrier needed)
	bx	lr
lock_dll:
	ldr	r11, omap3_sdrc_dlla_ctrl
	ldr	r12, [r11]
	bic	r12, r12, #DLLIDLE_MASK
	str	r12, [r11]		@ (no OCP barrier needed)
	bx	lr
sdram_in_selfrefresh:
	ldr	r11, omap3_sdrc_power	@ read the SDRC_POWER register
	ldr	r12, [r11]		@ read the contents of SDRC_POWER
	mov	r9, r12			@ keep a copy of SDRC_POWER bits
	orr 	r12, r12, #SRFRONIDLEREQ_MASK	@ enable self refresh on idle
	bic 	r12, r12, #PWDENA_MASK	@ clear PWDENA
	str 	r12, [r11]		@ write back to SDRC_POWER register
	ldr	r12, [r11]		@ posted-write barrier for SDRC
idle_sdrc:
	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
	ldr	r12, [r11]
	bic	r12, r12, #EN_SDRC_MASK		@ disable iclk bit for SDRC
	str 	r12, [r11]
wait_sdrc_idle:
	ldr 	r11, omap3_cm_idlest1_core
	ldr 	r12, [r11]
	and 	r12, r12, #ST_SDRC_MASK		@ check for SDRC idle
	cmp 	r12, #ST_SDRC_MASK
	bne 	wait_sdrc_idle
	bx 	lr
configure_core_dpll:
	ldr 	r11, omap3_cm_clksel1_pll
	ldr	r12, [r11]
	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
	and	r12, r12, r10
	orr	r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
	str	r12, [r11]
	ldr	r12, [r11]		@ posted-write barrier for CM
	bx	lr
wait_clk_stable:
	subs 	r12, r12, #1
	bne	wait_clk_stable
	bx	lr
enable_sdrc:
	ldr 	r11, omap3_cm_iclken1_core
	ldr	r12, [r11]
	orr 	r12, r12, #EN_SDRC_MASK		@ enable iclk bit for SDRC
	str 	r12, [r11]
wait_sdrc_idle1:
	ldr 	r11, omap3_cm_idlest1_core
	ldr	r12, [r11]
	and 	r12, r12, #ST_SDRC_MASK
	cmp	r12, #0
	bne	wait_sdrc_idle1
restore_sdrc_power_val:
	ldr	r11, omap3_sdrc_power
	str	r9, [r11]		@ restore SDRC_POWER, no barrier needed
	bx	lr
wait_dll_lock:
	ldr	r11, omap3_sdrc_dlla_status
	ldr	r12, [r11]
	and 	r12, r12, #LOCKSTATUS_MASK
	cmp	r12, #LOCKSTATUS_MASK
	bne	wait_dll_lock
	bx	lr
wait_dll_unlock:
	ldr	r11, omap3_sdrc_dlla_status
	ldr	r12, [r11]
	and	r12, r12, #LOCKSTATUS_MASK
	cmp	r12, #0x0
	bne	wait_dll_unlock
	bx	lr
configure_sdrc:
	ldr	r11, omap3_sdrc_rfr_ctrl
	str	r0, [r11]
	ldr	r11, omap3_sdrc_actim_ctrla
	str	r1, [r11]
	ldr	r11, omap3_sdrc_actim_ctrlb
	str	r2, [r11]
	ldr	r11, omap3_sdrc_mr_0
	str	r6, [r11]
	ldr	r6, [r11]		@ posted-write barrier for SDRC
	bx	lr

omap3_sdrc_power:
	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
omap3_cm_clksel1_pll:
	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
omap3_cm_idlest1_core:
	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
omap3_cm_iclken1_core:
	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
omap3_sdrc_rfr_ctrl:
	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap3_sdrc_actim_ctrla:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
omap3_sdrc_mr_0:
	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
omap3_sdrc_dlla_status:
	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl:
	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
core_m2_mask_val:
	.word 0x07FFFFFF

ENTRY(omap3_sram_configure_core_dpll_sz)
	.word	. - omap3_sram_configure_core_dpll
Commit	Line	Data
cc26b3b0 SMK	1	/*
	2	* linux/arch/arm/mach-omap3/sram.S
	3	*
	4	* Omap3 specific functions that need to be run in internal SRAM
	5	*
4267b5d1 PW	6	* Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
4267b5d1 PW	7	* Copyright (C) 2008 Nokia Corporation
cc26b3b0	8	*
4267b5d1	9	* Rajendra Nayak <rnayak@ti.com>
cc26b3b0	10	* Richard Woodruff <r-woodruff2@ti.com>
4267b5d1	11	* Paul Walmsley
cc26b3b0 SMK	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28	#include <linux/linkage.h>
	29	#include <asm/assembler.h>
	30	#include <mach/hardware.h>
	31
	32	#include <mach/io.h>
	33
	34	#include "sdrc.h"
	35	#include "cm.h"
	36
	37	.text
	38
df14e474 PW	39	/* r4 parameters */
	40	#define SDRC_NO_UNLOCK_DLL 0x0
	41	#define SDRC_UNLOCK_DLL 0x1
	42
	43	/* SDRC_DLLA_CTRL bit settings */
7b7bcefa PW	44	#define FIXEDDELAY_SHIFT 24
7b7bcefa PW	45	#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
df14e474 PW	46	#define DLLIDLE_MASK 0x4
df14e474 PW	47
7b7bcefa PW	48	/*
	49	* SDRC_DLLA_CTRL default values: TI hardware team indicates that
	50	* FIXEDDELAY should be initialized to 0xf. This apparently was
	51	* empirically determined during process testing, so no derivation
	52	* was provided.
	53	*/
	54	#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
	55
df14e474 PW	56	/* SDRC_DLLA_STATUS bit settings */
	57	#define LOCKSTATUS_MASK 0x4
	58
	59	/* SDRC_POWER bit settings */
	60	#define SRFRONIDLEREQ_MASK 0x40
	61	#define PWDENA_MASK 0x4
	62
	63	/* CM_IDLEST1_CORE bit settings */
	64	#define ST_SDRC_MASK 0x2
	65
	66	/* CM_ICLKEN1_CORE bit settings */
	67	#define EN_SDRC_MASK 0x2
	68
	69	/* CM_CLKSEL1_PLL bit settings */
	70	#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
	71
cc26b3b0	72	/*
4267b5d1 PW	73	* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
	74	* r0 = new SDRC_RFR_CTRL register contents
	75	* r1 = new SDRC_ACTIM_CTRLA register contents
	76	* r2 = new SDRC_ACTIM_CTRLB register contents
	77	* r3 = new M2 divider setting (only 1 and 2 supported right now)
	78	* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
4519c2bf	79	* SDRC rates < 83MHz
c9812d04 PW	80	* r5 = number of MPU cycles to wait for SDRC to stabilize after
c9812d04 PW	81	* reprogramming the SDRC when switching to a slower MPU speed
4267b5d1	82	* r6 = new SDRC_MR_0 register value
3afec633	83	* r7 = increasing SDRC rate? (1 = yes, 0 = no)
c9812d04	84	*
cc26b3b0 SMK	85	*/
	86	ENTRY(omap3_sram_configure_core_dpll)
	87	stmfd sp!, {r1-r12, lr} @ store regs to stack
4519c2bf	88	ldr r4, [sp, #52] @ pull extra args off the stack
c9812d04	89	ldr r5, [sp, #56] @ load extra args from the stack
d0ba3922	90	ldr r6, [sp, #60] @ load extra args from the stack
3afec633	91	ldr r7, [sp, #64] @ load extra args from the stack
69d4255b	92	dsb @ flush buffered writes to interconnect
3afec633 TK	93	cmp r7, #1 @ if increasing SDRC clk rate,
3afec633 TK	94	bleq configure_sdrc @ program the SDRC regs early (for RFR)
df14e474	95	cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
4519c2bf	96	bleq unlock_dll
cc26b3b0	97	blne lock_dll
4267b5d1 PW	98	bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
	99	bl configure_core_dpll @ change the DPLL3 M2 divider
	100	bl enable_sdrc @ take SDRC out of idle
df14e474	101	cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
4519c2bf	102	bleq wait_dll_unlock
cc26b3b0	103	blne wait_dll_lock
3afec633	104	cmp r7, #1 @ if increasing SDRC clk rate,
4267b5d1 PW	105	beq return_to_sdram @ return to SDRAM code, otherwise,
	106	bl configure_sdrc @ reprogram SDRC regs now
	107	mov r12, r5
	108	bl wait_clk_stable @ wait for SDRC to stabilize
c9812d04	109	return_to_sdram:
69d4255b	110	isb @ prevent speculative exec past here
cc26b3b0 SMK	111	mov r0, #0 @ return value
	112	ldmfd sp!, {r1-r12, pc} @ restore regs and return
	113	unlock_dll:
b2abb271 PW	114	ldr r11, omap3_sdrc_dlla_ctrl
b2abb271 PW	115	ldr r12, [r11]
7b7bcefa PW	116	and r12, r12, #FIXEDDELAY_MASK
7b7bcefa PW	117	orr r12, r12, #FIXEDDELAY_DEFAULT
df14e474	118	orr r12, r12, #DLLIDLE_MASK
b2abb271	119	str r12, [r11] @ (no OCP barrier needed)
cc26b3b0 SMK	120	bx lr
cc26b3b0 SMK	121	lock_dll:
b2abb271 PW	122	ldr r11, omap3_sdrc_dlla_ctrl
b2abb271 PW	123	ldr r12, [r11]
df14e474	124	bic r12, r12, #DLLIDLE_MASK
b2abb271	125	str r12, [r11] @ (no OCP barrier needed)
cc26b3b0 SMK	126	bx lr
cc26b3b0 SMK	127	sdram_in_selfrefresh:
b2abb271 PW	128	ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
	129	ldr r12, [r11] @ read the contents of SDRC_POWER
	130	mov r9, r12 @ keep a copy of SDRC_POWER bits
df14e474 PW	131	orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
df14e474 PW	132	bic r12, r12, #PWDENA_MASK @ clear PWDENA
b2abb271 PW	133	str r12, [r11] @ write back to SDRC_POWER register
b2abb271 PW	134	ldr r12, [r11] @ posted-write barrier for SDRC
4267b5d1	135	idle_sdrc:
b2abb271 PW	136	ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
b2abb271 PW	137	ldr r12, [r11]
df14e474	138	bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
b2abb271	139	str r12, [r11]
cc26b3b0	140	wait_sdrc_idle:
b2abb271 PW	141	ldr r11, omap3_cm_idlest1_core
b2abb271 PW	142	ldr r12, [r11]
df14e474 PW	143	and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
df14e474 PW	144	cmp r12, #ST_SDRC_MASK
cc26b3b0 SMK	145	bne wait_sdrc_idle
	146	bx lr
	147	configure_core_dpll:
b2abb271 PW	148	ldr r11, omap3_cm_clksel1_pll
	149	ldr r12, [r11]
	150	ldr r10, core_m2_mask_val @ modify m2 for core dpll
	151	and r12, r12, r10
df14e474	152	orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
b2abb271 PW	153	str r12, [r11]
b2abb271 PW	154	ldr r12, [r11] @ posted-write barrier for CM
cc26b3b0 SMK	155	bx lr
cc26b3b0 SMK	156	wait_clk_stable:
b2abb271	157	subs r12, r12, #1
cc26b3b0	158	bne wait_clk_stable
cc26b3b0 SMK	159	bx lr
cc26b3b0 SMK	160	enable_sdrc:
b2abb271 PW	161	ldr r11, omap3_cm_iclken1_core
b2abb271 PW	162	ldr r12, [r11]
df14e474	163	orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
b2abb271	164	str r12, [r11]
cc26b3b0	165	wait_sdrc_idle1:
b2abb271 PW	166	ldr r11, omap3_cm_idlest1_core
b2abb271 PW	167	ldr r12, [r11]
df14e474	168	and r12, r12, #ST_SDRC_MASK
b2abb271	169	cmp r12, #0
cc26b3b0	170	bne wait_sdrc_idle1
fa0406a8	171	restore_sdrc_power_val:
b2abb271 PW	172	ldr r11, omap3_sdrc_power
b2abb271 PW	173	str r9, [r11] @ restore SDRC_POWER, no barrier needed
cc26b3b0 SMK	174	bx lr
cc26b3b0 SMK	175	wait_dll_lock:
b2abb271 PW	176	ldr r11, omap3_sdrc_dlla_status
b2abb271 PW	177	ldr r12, [r11]
df14e474 PW	178	and r12, r12, #LOCKSTATUS_MASK
df14e474 PW	179	cmp r12, #LOCKSTATUS_MASK
cc26b3b0 SMK	180	bne wait_dll_lock
	181	bx lr
	182	wait_dll_unlock:
b2abb271 PW	183	ldr r11, omap3_sdrc_dlla_status
b2abb271 PW	184	ldr r12, [r11]
df14e474	185	and r12, r12, #LOCKSTATUS_MASK
b2abb271	186	cmp r12, #0x0
cc26b3b0 SMK	187	bne wait_dll_unlock
	188	bx lr
	189	configure_sdrc:
b2abb271 PW	190	ldr r11, omap3_sdrc_rfr_ctrl
	191	str r0, [r11]
	192	ldr r11, omap3_sdrc_actim_ctrla
	193	str r1, [r11]
	194	ldr r11, omap3_sdrc_actim_ctrlb
	195	str r2, [r11]
d0ba3922 PW	196	ldr r11, omap3_sdrc_mr_0
	197	str r6, [r11]
	198	ldr r6, [r11] @ posted-write barrier for SDRC
cc26b3b0 SMK	199	bx lr
	200
	201	omap3_sdrc_power:
	202	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
	203	omap3_cm_clksel1_pll:
	204	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
	205	omap3_cm_idlest1_core:
	206	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
	207	omap3_cm_iclken1_core:
	208	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
	209	omap3_sdrc_rfr_ctrl:
	210	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
	211	omap3_sdrc_actim_ctrla:
	212	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
	213	omap3_sdrc_actim_ctrlb:
	214	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
d0ba3922 PW	215	omap3_sdrc_mr_0:
d0ba3922 PW	216	.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
cc26b3b0 SMK	217	omap3_sdrc_dlla_status:
	218	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
	219	omap3_sdrc_dlla_ctrl:
	220	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
	221	core_m2_mask_val:
	222	.word 0x07FFFFFF
	223
	224	ENTRY(omap3_sram_configure_core_dpll_sz)
	225	.word . - omap3_sram_configure_core_dpll