Commit | Line | Data |
---|---|---|
1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
40fc3bb5 JH |
42 | #include <linux/platform_device.h> |
43 | #include <linux/platform_data/dmtimer-omap.h> | |
f8ce2547 | 44 | |
1dbae815 | 45 | #include <asm/mach/time.h> |
a45c983f | 46 | #include <asm/smp_twd.h> |
cbc94380 | 47 | #include <asm/sched_clock.h> |
7d7e1eba | 48 | |
3c7c5dab | 49 | #include <asm/arch_timer.h> |
2a296c8f | 50 | #include "omap_hwmod.h" |
25c7d49e | 51 | #include "omap_device.h" |
5c2e8852 | 52 | #include <plat/counter-32k.h> |
7d7e1eba | 53 | #include <plat/dmtimer.h> |
1d5aef49 | 54 | #include "omap-pm.h" |
b481113a | 55 | |
dbc04161 | 56 | #include "soc.h" |
7d7e1eba | 57 | #include "common.h" |
b481113a | 58 | #include "powerdomain.h" |
1dbae815 | 59 | |
aa561889 TL |
60 | /* Parent clocks, eventually these will come from the clock framework */ |
61 | ||
62 | #define OMAP2_MPU_SOURCE "sys_ck" | |
63 | #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE | |
64 | #define OMAP4_MPU_SOURCE "sys_clkin_ck" | |
65 | #define OMAP2_32K_SOURCE "func_32k_ck" | |
66 | #define OMAP3_32K_SOURCE "omap_32k_fck" | |
67 | #define OMAP4_32K_SOURCE "sys_32k_ck" | |
68 | ||
fa6d79d2 SS |
69 | #define REALTIME_COUNTER_BASE 0x48243200 |
70 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
71 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
72 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
73 | ||
aa561889 TL |
74 | /* Clockevent code */ |
75 | ||
76 | static struct omap_dm_timer clkev; | |
5a3a388f | 77 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 78 | |
0cd61b68 | 79 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 80 | { |
5a3a388f KH |
81 | struct clock_event_device *evt = &clockevent_gpt; |
82 | ||
ee17f114 | 83 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 84 | |
5a3a388f | 85 | evt->event_handler(evt); |
1dbae815 TL |
86 | return IRQ_HANDLED; |
87 | } | |
88 | ||
89 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 90 | .name = "gp_timer", |
b30fabad | 91 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
92 | .handler = omap2_gp_timer_interrupt, |
93 | }; | |
94 | ||
5a3a388f KH |
95 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
96 | struct clock_event_device *evt) | |
1dbae815 | 97 | { |
ee17f114 | 98 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
971d0254 | 99 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
5a3a388f KH |
100 | |
101 | return 0; | |
102 | } | |
103 | ||
104 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
105 | struct clock_event_device *evt) | |
106 | { | |
107 | u32 period; | |
108 | ||
971d0254 | 109 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
5a3a388f KH |
110 | |
111 | switch (mode) { | |
112 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 113 | period = clkev.rate / HZ; |
5a3a388f | 114 | period -= 1; |
aa561889 | 115 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 116 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
971d0254 | 117 | 0xffffffff - period, OMAP_TIMER_POSTED); |
ee17f114 | 118 | __omap_dm_timer_load_start(&clkev, |
aa561889 | 119 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
971d0254 | 120 | 0xffffffff - period, OMAP_TIMER_POSTED); |
5a3a388f KH |
121 | break; |
122 | case CLOCK_EVT_MODE_ONESHOT: | |
123 | break; | |
124 | case CLOCK_EVT_MODE_UNUSED: | |
125 | case CLOCK_EVT_MODE_SHUTDOWN: | |
126 | case CLOCK_EVT_MODE_RESUME: | |
127 | break; | |
128 | } | |
129 | } | |
130 | ||
131 | static struct clock_event_device clockevent_gpt = { | |
f36921be | 132 | .name = "gp_timer", |
5a3a388f | 133 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
11d6ec2e | 134 | .rating = 300, |
5a3a388f KH |
135 | .set_next_event = omap2_gp_timer_set_next_event, |
136 | .set_mode = omap2_gp_timer_set_mode, | |
137 | }; | |
138 | ||
ad24bde8 JH |
139 | static struct property device_disabled = { |
140 | .name = "status", | |
141 | .length = sizeof("disabled"), | |
142 | .value = "disabled", | |
143 | }; | |
144 | ||
145 | static struct of_device_id omap_timer_match[] __initdata = { | |
146 | { .compatible = "ti,omap2-timer", }, | |
147 | { } | |
148 | }; | |
149 | ||
9725f445 JH |
150 | /** |
151 | * omap_get_timer_dt - get a timer using device-tree | |
152 | * @match - device-tree match structure for matching a device type | |
153 | * @property - optional timer property to match | |
154 | * | |
155 | * Helper function to get a timer during early boot using device-tree for use | |
156 | * as kernel system timer. Optionally, the property argument can be used to | |
157 | * select a timer with a specific property. Once a timer is found then mark | |
158 | * the timer node in device-tree as disabled, to prevent the kernel from | |
159 | * registering this timer as a platform device and so no one else can use it. | |
160 | */ | |
161 | static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, | |
162 | const char *property) | |
163 | { | |
164 | struct device_node *np; | |
165 | ||
166 | for_each_matching_node(np, match) { | |
034bf091 | 167 | if (!of_device_is_available(np)) |
9725f445 | 168 | continue; |
9725f445 | 169 | |
034bf091 | 170 | if (property && !of_get_property(np, property, NULL)) |
9725f445 | 171 | continue; |
9725f445 | 172 | |
2727da85 | 173 | of_add_property(np, &device_disabled); |
9725f445 JH |
174 | return np; |
175 | } | |
176 | ||
177 | return NULL; | |
178 | } | |
179 | ||
ad24bde8 JH |
180 | /** |
181 | * omap_dmtimer_init - initialisation function when device tree is used | |
182 | * | |
183 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
184 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
185 | * kernel registering these devices remove them dynamically from the device | |
186 | * tree on boot. | |
187 | */ | |
bf85f205 | 188 | static void __init omap_dmtimer_init(void) |
ad24bde8 JH |
189 | { |
190 | struct device_node *np; | |
191 | ||
192 | if (!cpu_is_omap34xx()) | |
193 | return; | |
194 | ||
195 | /* If we are a secure device, remove any secure timer nodes */ | |
196 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 JH |
197 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
198 | if (np) | |
199 | of_node_put(np); | |
ad24bde8 JH |
200 | } |
201 | } | |
202 | ||
bfd6d021 JH |
203 | /** |
204 | * omap_dm_timer_get_errata - get errata flags for a timer | |
205 | * | |
206 | * Get the timer errata flags that are specific to the OMAP device being used. | |
207 | */ | |
bf85f205 | 208 | static u32 __init omap_dm_timer_get_errata(void) |
bfd6d021 JH |
209 | { |
210 | if (cpu_is_omap24xx()) | |
211 | return 0; | |
212 | ||
213 | return OMAP_TIMER_ERRATA_I103_I767; | |
214 | } | |
215 | ||
aa561889 TL |
216 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
217 | int gptimer_id, | |
9725f445 | 218 | const char *fck_source, |
bfd6d021 JH |
219 | const char *property, |
220 | int posted) | |
5a3a388f | 221 | { |
aa561889 | 222 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
9725f445 JH |
223 | const char *oh_name; |
224 | struct device_node *np; | |
aa561889 | 225 | struct omap_hwmod *oh; |
61b001c5 | 226 | struct resource irq, mem; |
f88095ba | 227 | int r = 0; |
aa561889 | 228 | |
9725f445 | 229 | if (of_have_populated_dt()) { |
61338d59 | 230 | np = omap_get_timer_dt(omap_timer_match, property); |
9725f445 JH |
231 | if (!np) |
232 | return -ENODEV; | |
233 | ||
234 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
235 | if (!oh_name) | |
236 | return -ENODEV; | |
237 | ||
238 | timer->irq = irq_of_parse_and_map(np, 0); | |
239 | if (!timer->irq) | |
240 | return -ENXIO; | |
241 | ||
242 | timer->io_base = of_iomap(np, 0); | |
243 | ||
244 | of_node_put(np); | |
245 | } else { | |
246 | if (omap_dm_timer_reserve_systimer(gptimer_id)) | |
247 | return -ENODEV; | |
248 | ||
249 | sprintf(name, "timer%d", gptimer_id); | |
250 | oh_name = name; | |
251 | } | |
252 | ||
9725f445 | 253 | oh = omap_hwmod_lookup(oh_name); |
aa561889 TL |
254 | if (!oh) |
255 | return -ENODEV; | |
256 | ||
9725f445 JH |
257 | if (!of_have_populated_dt()) { |
258 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | |
61b001c5 | 259 | &irq); |
9725f445 JH |
260 | if (r) |
261 | return -ENXIO; | |
61b001c5 | 262 | timer->irq = irq.start; |
9725f445 JH |
263 | |
264 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, | |
61b001c5 | 265 | &mem); |
9725f445 JH |
266 | if (r) |
267 | return -ENXIO; | |
9725f445 JH |
268 | |
269 | /* Static mapping, never released */ | |
61b001c5 | 270 | timer->io_base = ioremap(mem.start, mem.end - mem.start); |
9725f445 | 271 | } |
aa561889 | 272 | |
aa561889 TL |
273 | if (!timer->io_base) |
274 | return -ENXIO; | |
275 | ||
276 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 277 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 TL |
278 | if (IS_ERR(timer->fclk)) |
279 | return -ENODEV; | |
280 | ||
9725f445 | 281 | /* FIXME: Need to remove hard-coded test on timer ID */ |
aa561889 TL |
282 | if (gptimer_id != 12) { |
283 | struct clk *src; | |
284 | ||
285 | src = clk_get(NULL, fck_source); | |
286 | if (IS_ERR(src)) { | |
f88095ba | 287 | r = -EINVAL; |
aa561889 | 288 | } else { |
f88095ba JH |
289 | r = clk_set_parent(timer->fclk, src); |
290 | if (IS_ERR_VALUE(r)) | |
9725f445 JH |
291 | pr_warn("%s: %s cannot set source\n", |
292 | __func__, oh->name); | |
aa561889 TL |
293 | clk_put(src); |
294 | } | |
295 | } | |
b1538832 JH |
296 | |
297 | omap_hwmod_setup_one(oh_name); | |
298 | omap_hwmod_enable(oh); | |
ee17f114 | 299 | __omap_dm_timer_init_regs(timer); |
aa561889 | 300 | |
bfd6d021 JH |
301 | if (posted) |
302 | __omap_dm_timer_enable_posted(timer); | |
303 | ||
304 | /* Check that the intended posted configuration matches the actual */ | |
305 | if (posted != timer->posted) | |
306 | return -EINVAL; | |
1dbae815 | 307 | |
bfd6d021 | 308 | timer->rate = clk_get_rate(timer->fclk); |
aa561889 | 309 | timer->reserved = 1; |
38698bef | 310 | |
f88095ba | 311 | return r; |
aa561889 | 312 | } |
f248076c | 313 | |
aa561889 | 314 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
315 | const char *fck_source, |
316 | const char *property) | |
aa561889 TL |
317 | { |
318 | int res; | |
f248076c | 319 | |
bfd6d021 JH |
320 | clkev.errata = omap_dm_timer_get_errata(); |
321 | ||
322 | /* | |
323 | * For clock-event timers we never read the timer counter and | |
324 | * so we are not impacted by errata i103 and i767. Therefore, | |
325 | * we can safely ignore this errata for clock-event timers. | |
326 | */ | |
327 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | |
328 | ||
329 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, | |
330 | OMAP_TIMER_POSTED); | |
aa561889 | 331 | BUG_ON(res); |
f248076c | 332 | |
a032d33b | 333 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 334 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 335 | |
ee17f114 | 336 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 | 337 | |
11d6ec2e SS |
338 | clockevent_gpt.cpumask = cpu_possible_mask; |
339 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
838a2ae8 SG |
340 | clockevents_config_and_register(&clockevent_gpt, clkev.rate, |
341 | 3, /* Timer internal resynch latency */ | |
342 | 0xffffffff); | |
aa561889 TL |
343 | |
344 | pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", | |
345 | gptimer_id, clkev.rate); | |
5a3a388f KH |
346 | } |
347 | ||
f248076c | 348 | /* Clocksource code */ |
3d05a3e8 | 349 | static struct omap_dm_timer clksrc; |
1fe97c8f | 350 | static bool use_gptimer_clksrc; |
3d05a3e8 | 351 | |
5a3a388f KH |
352 | /* |
353 | * clocksource | |
354 | */ | |
8e19608e | 355 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 356 | { |
971d0254 | 357 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 358 | OMAP_TIMER_NONPOSTED); |
5a3a388f KH |
359 | } |
360 | ||
361 | static struct clocksource clocksource_gpt = { | |
f36921be | 362 | .name = "gp_timer", |
5a3a388f KH |
363 | .rating = 300, |
364 | .read = clocksource_read_cycles, | |
365 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
366 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
367 | }; | |
368 | ||
2f0778af | 369 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 370 | { |
3d05a3e8 | 371 | if (clksrc.reserved) |
971d0254 | 372 | return __omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 373 | OMAP_TIMER_NONPOSTED); |
5a3a388f | 374 | |
2f0778af | 375 | return 0; |
3d05a3e8 TL |
376 | } |
377 | ||
258e84af JH |
378 | static struct of_device_id omap_counter_match[] __initdata = { |
379 | { .compatible = "ti,omap-counter32k", }, | |
380 | { } | |
381 | }; | |
382 | ||
3d05a3e8 | 383 | /* Setup free-running counter for clocksource */ |
e0c3e27c | 384 | static int __init __maybe_unused omap2_sync32k_clocksource_init(void) |
1fe97c8f VH |
385 | { |
386 | int ret; | |
9883f7c8 | 387 | struct device_node *np = NULL; |
1fe97c8f VH |
388 | struct omap_hwmod *oh; |
389 | void __iomem *vbase; | |
390 | const char *oh_name = "counter_32k"; | |
391 | ||
9883f7c8 JH |
392 | /* |
393 | * If device-tree is present, then search the DT blob | |
394 | * to see if the 32kHz counter is supported. | |
395 | */ | |
396 | if (of_have_populated_dt()) { | |
397 | np = omap_get_timer_dt(omap_counter_match, NULL); | |
398 | if (!np) | |
399 | return -ENODEV; | |
400 | ||
401 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
402 | if (!oh_name) | |
403 | return -ENODEV; | |
404 | } | |
405 | ||
1fe97c8f VH |
406 | /* |
407 | * First check hwmod data is available for sync32k counter | |
408 | */ | |
409 | oh = omap_hwmod_lookup(oh_name); | |
410 | if (!oh || oh->slaves_cnt == 0) | |
411 | return -ENODEV; | |
412 | ||
413 | omap_hwmod_setup_one(oh_name); | |
414 | ||
9883f7c8 JH |
415 | if (np) { |
416 | vbase = of_iomap(np, 0); | |
417 | of_node_put(np); | |
418 | } else { | |
419 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
420 | } | |
421 | ||
1fe97c8f VH |
422 | if (!vbase) { |
423 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
424 | return -ENXIO; | |
425 | } | |
426 | ||
427 | ret = omap_hwmod_enable(oh); | |
428 | if (ret) { | |
429 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
430 | __func__, ret); | |
431 | return ret; | |
432 | } | |
433 | ||
434 | ret = omap_init_clocksource_32k(vbase); | |
435 | if (ret) { | |
436 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
437 | __func__, ret); | |
438 | omap_hwmod_idle(oh); | |
439 | } | |
440 | ||
441 | return ret; | |
442 | } | |
443 | ||
444 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
3d05a3e8 TL |
445 | const char *fck_source) |
446 | { | |
447 | int res; | |
448 | ||
bfd6d021 JH |
449 | clksrc.errata = omap_dm_timer_get_errata(); |
450 | ||
451 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL, | |
452 | OMAP_TIMER_NONPOSTED); | |
3d05a3e8 | 453 | BUG_ON(res); |
5a3a388f | 454 | |
ee17f114 | 455 | __omap_dm_timer_load_start(&clksrc, |
971d0254 | 456 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
bfd6d021 | 457 | OMAP_TIMER_NONPOSTED); |
2f0778af | 458 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 459 | |
3d05a3e8 TL |
460 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
461 | pr_err("Could not register clocksource %s\n", | |
462 | clocksource_gpt.name); | |
1fe97c8f VH |
463 | else |
464 | pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", | |
465 | gptimer_id, clksrc.rate); | |
466 | } | |
467 | ||
fa6d79d2 SS |
468 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
469 | /* | |
470 | * The realtime counter also called master counter, is a free-running | |
471 | * counter, which is related to real time. It produces the count used | |
472 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
473 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
474 | * in different power modes, the master counter shifts operation between | |
475 | * clocks, adjusting the increment per clock in hardware accordingly to | |
476 | * maintain a constant count rate. | |
477 | */ | |
478 | static void __init realtime_counter_init(void) | |
479 | { | |
480 | void __iomem *base; | |
481 | static struct clk *sys_clk; | |
482 | unsigned long rate; | |
483 | unsigned int reg, num, den; | |
484 | ||
485 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
486 | if (!base) { | |
487 | pr_err("%s: ioremap failed\n", __func__); | |
488 | return; | |
489 | } | |
490 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | |
533b2981 | 491 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
492 | pr_err("%s: failed to get system clock handle\n", __func__); |
493 | iounmap(base); | |
494 | return; | |
495 | } | |
496 | ||
497 | rate = clk_get_rate(sys_clk); | |
498 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
499 | switch (rate) { | |
500 | case 1200000: | |
501 | num = 64; | |
502 | den = 125; | |
503 | break; | |
504 | case 1300000: | |
505 | num = 768; | |
506 | den = 1625; | |
507 | break; | |
508 | case 19200000: | |
509 | num = 8; | |
510 | den = 25; | |
511 | break; | |
512 | case 2600000: | |
513 | num = 384; | |
514 | den = 1625; | |
515 | break; | |
516 | case 2700000: | |
517 | num = 256; | |
518 | den = 1125; | |
519 | break; | |
520 | case 38400000: | |
521 | default: | |
522 | /* Program it for 38.4 MHz */ | |
523 | num = 4; | |
524 | den = 25; | |
525 | break; | |
526 | } | |
527 | ||
528 | /* Program numerator and denumerator registers */ | |
529 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
530 | NUMERATOR_DENUMERATOR_MASK; | |
531 | reg |= num; | |
532 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
533 | ||
534 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
535 | NUMERATOR_DENUMERATOR_MASK; | |
536 | reg |= den; | |
537 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
538 | ||
539 | iounmap(base); | |
540 | } | |
541 | #else | |
542 | static inline void __init realtime_counter_init(void) | |
543 | {} | |
544 | #endif | |
545 | ||
6f80b3bb IG |
546 | #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
547 | clksrc_nr, clksrc_src) \ | |
6bb27d73 | 548 | void __init omap##name##_gptimer_timer_init(void) \ |
6f80b3bb | 549 | { \ |
ff931c82 RN |
550 | if (omap_clk_init) \ |
551 | omap_clk_init(); \ | |
6f80b3bb IG |
552 | omap_dmtimer_init(); \ |
553 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ | |
554 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ | |
555 | } | |
556 | ||
557 | #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ | |
3d05a3e8 | 558 | clksrc_nr, clksrc_src) \ |
6bb27d73 | 559 | void __init omap##name##_sync32k_timer_init(void) \ |
e74984e4 | 560 | { \ |
ff931c82 RN |
561 | if (omap_clk_init) \ |
562 | omap_clk_init(); \ | |
ad24bde8 | 563 | omap_dmtimer_init(); \ |
9725f445 | 564 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
6f80b3bb IG |
565 | /* Enable the use of clocksource="gp_timer" kernel parameter */ \ |
566 | if (use_gptimer_clksrc) \ | |
567 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\ | |
568 | else \ | |
569 | omap2_sync32k_clocksource_init(); \ | |
e74984e4 TL |
570 | } |
571 | ||
e74984e4 | 572 | #ifdef CONFIG_ARCH_OMAP2 |
6f80b3bb IG |
573 | OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon", |
574 | 2, OMAP2_MPU_SOURCE); | |
6f80b3bb | 575 | #endif /* CONFIG_ARCH_OMAP2 */ |
e74984e4 TL |
576 | |
577 | #ifdef CONFIG_ARCH_OMAP3 | |
6f80b3bb IG |
578 | OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon", |
579 | 2, OMAP3_MPU_SOURCE); | |
6f80b3bb IG |
580 | OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure", |
581 | 2, OMAP3_MPU_SOURCE); | |
26f01998 IG |
582 | OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon", |
583 | 2, OMAP3_MPU_SOURCE); | |
6f80b3bb | 584 | #endif /* CONFIG_ARCH_OMAP3 */ |
e74984e4 | 585 | |
08f30989 | 586 | #ifdef CONFIG_SOC_AM33XX |
6f80b3bb IG |
587 | OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", |
588 | 2, OMAP4_MPU_SOURCE); | |
6f80b3bb | 589 | #endif /* CONFIG_SOC_AM33XX */ |
08f30989 | 590 | |
e74984e4 | 591 | #ifdef CONFIG_ARCH_OMAP4 |
6f80b3bb IG |
592 | OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", |
593 | 2, OMAP4_MPU_SOURCE); | |
39e1d4c1 | 594 | #ifdef CONFIG_LOCAL_TIMERS |
6f80b3bb | 595 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); |
6bb27d73 | 596 | void __init omap4_local_timer_init(void) |
a45c983f | 597 | { |
6f80b3bb | 598 | omap4_sync32k_timer_init(); |
a45c983f MZ |
599 | /* Local timers are not supprted on OMAP4430 ES1.0 */ |
600 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
601 | int err; | |
602 | ||
eed0de27 SS |
603 | if (of_have_populated_dt()) { |
604 | twd_local_timer_of_register(); | |
605 | return; | |
606 | } | |
607 | ||
a45c983f MZ |
608 | err = twd_local_timer_register(&twd_local_timer); |
609 | if (err) | |
610 | pr_err("twd_local_timer_register failed %d\n", err); | |
611 | } | |
1dbae815 | 612 | } |
6f80b3bb | 613 | #else /* CONFIG_LOCAL_TIMERS */ |
6bb27d73 | 614 | void __init omap4_local_timer_init(void) |
6f80b3bb | 615 | { |
73f14f6d | 616 | omap4_sync32k_timer_init(); |
6f80b3bb IG |
617 | } |
618 | #endif /* CONFIG_LOCAL_TIMERS */ | |
6f80b3bb | 619 | #endif /* CONFIG_ARCH_OMAP4 */ |
c345c8b0 | 620 | |
37b3280d | 621 | #ifdef CONFIG_SOC_OMAP5 |
6f80b3bb IG |
622 | OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", |
623 | 2, OMAP4_MPU_SOURCE); | |
6bb27d73 | 624 | void __init omap5_realtime_timer_init(void) |
fa6d79d2 | 625 | { |
3c7c5dab SS |
626 | int err; |
627 | ||
6f80b3bb | 628 | omap5_sync32k_timer_init(); |
fa6d79d2 | 629 | realtime_counter_init(); |
3c7c5dab SS |
630 | |
631 | err = arch_timer_of_register(); | |
632 | if (err) | |
633 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | |
fa6d79d2 | 634 | } |
6f80b3bb | 635 | #endif /* CONFIG_SOC_OMAP5 */ |
37b3280d | 636 | |
c345c8b0 TKD |
637 | /** |
638 | * omap_timer_init - build and register timer device with an | |
639 | * associated timer hwmod | |
640 | * @oh: timer hwmod pointer to be used to build timer device | |
641 | * @user: parameter that can be passed from calling hwmod API | |
642 | * | |
643 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
644 | * devices present in the system. The number of timer devices is known | |
645 | * by parsing through the hwmod database for a given class name. At the | |
646 | * end of function call memory is allocated for timer device and it is | |
647 | * registered to the framework ready to be proved by the driver. | |
648 | */ | |
649 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
650 | { | |
651 | int id; | |
652 | int ret = 0; | |
653 | char *name = "omap_timer"; | |
654 | struct dmtimer_platform_data *pdata; | |
c541c15f | 655 | struct platform_device *pdev; |
c345c8b0 TKD |
656 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
657 | ||
658 | pr_debug("%s: %s\n", __func__, oh->name); | |
659 | ||
660 | /* on secure device, do not register secure timer */ | |
661 | timer_dev_attr = oh->dev_attr; | |
662 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
663 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
664 | return ret; | |
665 | ||
666 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
667 | if (!pdata) { | |
668 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
669 | return -ENOMEM; | |
670 | } | |
671 | ||
672 | /* | |
673 | * Extract the IDs from name field in hwmod database | |
674 | * and use the same for constructing ids' for the | |
675 | * timer devices. In a way, we are avoiding usage of | |
676 | * static variable witin the function to do the same. | |
677 | * CAUTION: We have to be careful and make sure the | |
678 | * name in hwmod database does not change in which case | |
679 | * we might either make corresponding change here or | |
680 | * switch back static variable mechanism. | |
681 | */ | |
682 | sscanf(oh->name, "timer%2d", &id); | |
683 | ||
d1c1691b JH |
684 | if (timer_dev_attr) |
685 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 686 | |
bfd6d021 | 687 | pdata->timer_errata = omap_dm_timer_get_errata(); |
6e740f9a TL |
688 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; |
689 | ||
c1d1cd59 | 690 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); |
c345c8b0 | 691 | |
c541c15f | 692 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
693 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
694 | __func__, name, oh->name); | |
695 | ret = -EINVAL; | |
696 | } | |
697 | ||
698 | kfree(pdata); | |
699 | ||
700 | return ret; | |
701 | } | |
3392cdd3 TKD |
702 | |
703 | /** | |
704 | * omap2_dm_timer_init - top level regular device initialization | |
705 | * | |
706 | * Uses dedicated hwmod api to parse through hwmod database for | |
707 | * given class name and then build and register the timer device. | |
708 | */ | |
709 | static int __init omap2_dm_timer_init(void) | |
710 | { | |
711 | int ret; | |
712 | ||
9725f445 JH |
713 | /* If dtb is there, the devices will be created dynamically */ |
714 | if (of_have_populated_dt()) | |
715 | return -ENODEV; | |
716 | ||
3392cdd3 TKD |
717 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); |
718 | if (unlikely(ret)) { | |
719 | pr_err("%s: device registration failed.\n", __func__); | |
720 | return -EINVAL; | |
721 | } | |
722 | ||
723 | return 0; | |
724 | } | |
b76c8b19 | 725 | omap_arch_initcall(omap2_dm_timer_init); |
1fe97c8f VH |
726 | |
727 | /** | |
728 | * omap2_override_clocksource - clocksource override with user configuration | |
729 | * | |
730 | * Allows user to override default clocksource, using kernel parameter | |
731 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
732 | * | |
733 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
734 | * and not introducing any OMAP specific interface. | |
735 | */ | |
736 | static int __init omap2_override_clocksource(char *str) | |
737 | { | |
738 | if (!str) | |
739 | return 0; | |
740 | /* | |
741 | * For OMAP architecture, we only have two options | |
742 | * - sync_32k (default) | |
743 | * - gp_timer (sys_clk based) | |
744 | */ | |
745 | if (!strcmp(str, "gp_timer")) | |
746 | use_gptimer_clksrc = true; | |
747 | ||
748 | return 0; | |
749 | } | |
750 | early_param("clocksource", omap2_override_clocksource); |