Commit | Line | Data |
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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
40fc3bb5 JH |
42 | #include <linux/platform_device.h> |
43 | #include <linux/platform_data/dmtimer-omap.h> | |
38ff87f7 | 44 | #include <linux/sched_clock.h> |
f8ce2547 | 45 | |
1dbae815 | 46 | #include <asm/mach/time.h> |
a45c983f | 47 | #include <asm/smp_twd.h> |
7d7e1eba | 48 | |
2a296c8f | 49 | #include "omap_hwmod.h" |
25c7d49e | 50 | #include "omap_device.h" |
5c2e8852 | 51 | #include <plat/counter-32k.h> |
7d7e1eba | 52 | #include <plat/dmtimer.h> |
1d5aef49 | 53 | #include "omap-pm.h" |
b481113a | 54 | |
dbc04161 | 55 | #include "soc.h" |
7d7e1eba | 56 | #include "common.h" |
afc9d590 | 57 | #include "control.h" |
b481113a | 58 | #include "powerdomain.h" |
5523e409 | 59 | #include "omap-secure.h" |
1dbae815 | 60 | |
fa6d79d2 SS |
61 | #define REALTIME_COUNTER_BASE 0x48243200 |
62 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
63 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
64 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
65 | ||
aa561889 TL |
66 | /* Clockevent code */ |
67 | ||
68 | static struct omap_dm_timer clkev; | |
5a3a388f | 69 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 70 | |
d5da94b8 | 71 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
5523e409 S |
72 | static unsigned long arch_timer_freq; |
73 | ||
74 | void set_cntfreq(void) | |
75 | { | |
76 | omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); | |
77 | } | |
d5da94b8 | 78 | #endif |
1dbae815 | 79 | |
0cd61b68 | 80 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 81 | { |
5a3a388f KH |
82 | struct clock_event_device *evt = &clockevent_gpt; |
83 | ||
ee17f114 | 84 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 85 | |
5a3a388f | 86 | evt->event_handler(evt); |
1dbae815 TL |
87 | return IRQ_HANDLED; |
88 | } | |
89 | ||
90 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 91 | .name = "gp_timer", |
fe806d04 | 92 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
93 | .handler = omap2_gp_timer_interrupt, |
94 | }; | |
95 | ||
5a3a388f KH |
96 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
97 | struct clock_event_device *evt) | |
1dbae815 | 98 | { |
ee17f114 | 99 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
971d0254 | 100 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
5a3a388f KH |
101 | |
102 | return 0; | |
103 | } | |
104 | ||
74364615 VK |
105 | static int omap2_gp_timer_shutdown(struct clock_event_device *evt) |
106 | { | |
107 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) | |
5a3a388f KH |
112 | { |
113 | u32 period; | |
114 | ||
971d0254 | 115 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
5a3a388f | 116 | |
74364615 VK |
117 | period = clkev.rate / HZ; |
118 | period -= 1; | |
119 | /* Looks like we need to first set the load value separately */ | |
120 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, | |
121 | OMAP_TIMER_POSTED); | |
122 | __omap_dm_timer_load_start(&clkev, | |
123 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, | |
124 | 0xffffffff - period, OMAP_TIMER_POSTED); | |
125 | return 0; | |
5a3a388f KH |
126 | } |
127 | ||
128 | static struct clock_event_device clockevent_gpt = { | |
74364615 VK |
129 | .features = CLOCK_EVT_FEAT_PERIODIC | |
130 | CLOCK_EVT_FEAT_ONESHOT, | |
131 | .rating = 300, | |
132 | .set_next_event = omap2_gp_timer_set_next_event, | |
133 | .set_state_shutdown = omap2_gp_timer_shutdown, | |
134 | .set_state_periodic = omap2_gp_timer_set_periodic, | |
135 | .set_state_oneshot = omap2_gp_timer_shutdown, | |
136 | .tick_resume = omap2_gp_timer_shutdown, | |
5a3a388f KH |
137 | }; |
138 | ||
ad24bde8 JH |
139 | static struct property device_disabled = { |
140 | .name = "status", | |
141 | .length = sizeof("disabled"), | |
142 | .value = "disabled", | |
143 | }; | |
144 | ||
31957609 | 145 | static const struct of_device_id omap_timer_match[] __initconst = { |
002e1ec5 JH |
146 | { .compatible = "ti,omap2420-timer", }, |
147 | { .compatible = "ti,omap3430-timer", }, | |
148 | { .compatible = "ti,omap4430-timer", }, | |
149 | { .compatible = "ti,omap5430-timer", }, | |
132754e4 TL |
150 | { .compatible = "ti,dm814-timer", }, |
151 | { .compatible = "ti,dm816-timer", }, | |
002e1ec5 JH |
152 | { .compatible = "ti,am335x-timer", }, |
153 | { .compatible = "ti,am335x-timer-1ms", }, | |
ad24bde8 JH |
154 | { } |
155 | }; | |
156 | ||
9725f445 JH |
157 | /** |
158 | * omap_get_timer_dt - get a timer using device-tree | |
159 | * @match - device-tree match structure for matching a device type | |
160 | * @property - optional timer property to match | |
161 | * | |
162 | * Helper function to get a timer during early boot using device-tree for use | |
163 | * as kernel system timer. Optionally, the property argument can be used to | |
164 | * select a timer with a specific property. Once a timer is found then mark | |
165 | * the timer node in device-tree as disabled, to prevent the kernel from | |
166 | * registering this timer as a platform device and so no one else can use it. | |
167 | */ | |
31957609 | 168 | static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, |
9725f445 JH |
169 | const char *property) |
170 | { | |
171 | struct device_node *np; | |
172 | ||
173 | for_each_matching_node(np, match) { | |
034bf091 | 174 | if (!of_device_is_available(np)) |
9725f445 | 175 | continue; |
9725f445 | 176 | |
034bf091 | 177 | if (property && !of_get_property(np, property, NULL)) |
9725f445 | 178 | continue; |
9725f445 | 179 | |
2eb03937 JH |
180 | if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || |
181 | of_get_property(np, "ti,timer-dsp", NULL) || | |
182 | of_get_property(np, "ti,timer-pwm", NULL) || | |
183 | of_get_property(np, "ti,timer-secure", NULL))) | |
184 | continue; | |
185 | ||
bf4c9449 FB |
186 | if (!of_device_is_compatible(np, "ti,omap-counter32k")) |
187 | of_add_property(np, &device_disabled); | |
9725f445 JH |
188 | return np; |
189 | } | |
190 | ||
191 | return NULL; | |
192 | } | |
193 | ||
ad24bde8 JH |
194 | /** |
195 | * omap_dmtimer_init - initialisation function when device tree is used | |
196 | * | |
197 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
198 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
199 | * kernel registering these devices remove them dynamically from the device | |
200 | * tree on boot. | |
201 | */ | |
bf85f205 | 202 | static void __init omap_dmtimer_init(void) |
ad24bde8 JH |
203 | { |
204 | struct device_node *np; | |
205 | ||
206 | if (!cpu_is_omap34xx()) | |
207 | return; | |
208 | ||
209 | /* If we are a secure device, remove any secure timer nodes */ | |
210 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 | 211 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
9a0cb985 | 212 | of_node_put(np); |
ad24bde8 JH |
213 | } |
214 | } | |
215 | ||
bfd6d021 JH |
216 | /** |
217 | * omap_dm_timer_get_errata - get errata flags for a timer | |
218 | * | |
219 | * Get the timer errata flags that are specific to the OMAP device being used. | |
220 | */ | |
bf85f205 | 221 | static u32 __init omap_dm_timer_get_errata(void) |
bfd6d021 JH |
222 | { |
223 | if (cpu_is_omap24xx()) | |
224 | return 0; | |
225 | ||
226 | return OMAP_TIMER_ERRATA_I103_I767; | |
227 | } | |
228 | ||
aa561889 | 229 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
e95ea43a JH |
230 | const char *fck_source, |
231 | const char *property, | |
232 | const char **timer_name, | |
233 | int posted) | |
5a3a388f | 234 | { |
aa561889 | 235 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
37bd6ca8 | 236 | const char *oh_name = NULL; |
9725f445 | 237 | struct device_node *np; |
aa561889 | 238 | struct omap_hwmod *oh; |
61b001c5 | 239 | struct resource irq, mem; |
a7990a19 | 240 | struct clk *src; |
f88095ba | 241 | int r = 0; |
aa561889 | 242 | |
9725f445 | 243 | if (of_have_populated_dt()) { |
61338d59 | 244 | np = omap_get_timer_dt(omap_timer_match, property); |
9725f445 JH |
245 | if (!np) |
246 | return -ENODEV; | |
247 | ||
248 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
249 | if (!oh_name) | |
250 | return -ENODEV; | |
251 | ||
252 | timer->irq = irq_of_parse_and_map(np, 0); | |
253 | if (!timer->irq) | |
254 | return -ENXIO; | |
255 | ||
256 | timer->io_base = of_iomap(np, 0); | |
257 | ||
258 | of_node_put(np); | |
259 | } else { | |
8f6924dc | 260 | if (omap_dm_timer_reserve_systimer(timer->id)) |
9725f445 JH |
261 | return -ENODEV; |
262 | ||
8f6924dc | 263 | sprintf(name, "timer%d", timer->id); |
9725f445 JH |
264 | oh_name = name; |
265 | } | |
266 | ||
9725f445 | 267 | oh = omap_hwmod_lookup(oh_name); |
aa561889 TL |
268 | if (!oh) |
269 | return -ENODEV; | |
270 | ||
e95ea43a JH |
271 | *timer_name = oh->name; |
272 | ||
9725f445 JH |
273 | if (!of_have_populated_dt()) { |
274 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | |
61b001c5 | 275 | &irq); |
9725f445 JH |
276 | if (r) |
277 | return -ENXIO; | |
61b001c5 | 278 | timer->irq = irq.start; |
9725f445 JH |
279 | |
280 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, | |
61b001c5 | 281 | &mem); |
9725f445 JH |
282 | if (r) |
283 | return -ENXIO; | |
9725f445 JH |
284 | |
285 | /* Static mapping, never released */ | |
61b001c5 | 286 | timer->io_base = ioremap(mem.start, mem.end - mem.start); |
9725f445 | 287 | } |
aa561889 | 288 | |
aa561889 TL |
289 | if (!timer->io_base) |
290 | return -ENXIO; | |
291 | ||
292 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 293 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 | 294 | if (IS_ERR(timer->fclk)) |
a7990a19 | 295 | return PTR_ERR(timer->fclk); |
aa561889 | 296 | |
a7990a19 JH |
297 | src = clk_get(NULL, fck_source); |
298 | if (IS_ERR(src)) | |
299 | return PTR_ERR(src); | |
aa561889 | 300 | |
874b300a TL |
301 | WARN(clk_set_parent(timer->fclk, src) < 0, |
302 | "Cannot set timer parent clock, no PLL clock driver?"); | |
b1538832 | 303 | |
a7990a19 JH |
304 | clk_put(src); |
305 | ||
b1538832 JH |
306 | omap_hwmod_setup_one(oh_name); |
307 | omap_hwmod_enable(oh); | |
ee17f114 | 308 | __omap_dm_timer_init_regs(timer); |
aa561889 | 309 | |
bfd6d021 JH |
310 | if (posted) |
311 | __omap_dm_timer_enable_posted(timer); | |
312 | ||
313 | /* Check that the intended posted configuration matches the actual */ | |
314 | if (posted != timer->posted) | |
315 | return -EINVAL; | |
1dbae815 | 316 | |
bfd6d021 | 317 | timer->rate = clk_get_rate(timer->fclk); |
aa561889 | 318 | timer->reserved = 1; |
38698bef | 319 | |
f88095ba | 320 | return r; |
aa561889 | 321 | } |
f248076c | 322 | |
0b3e6fca GS |
323 | #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) |
324 | void tick_broadcast(const struct cpumask *mask) | |
325 | { | |
326 | } | |
327 | #endif | |
328 | ||
aa561889 | 329 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
330 | const char *fck_source, |
331 | const char *property) | |
aa561889 TL |
332 | { |
333 | int res; | |
f248076c | 334 | |
8f6924dc | 335 | clkev.id = gptimer_id; |
bfd6d021 JH |
336 | clkev.errata = omap_dm_timer_get_errata(); |
337 | ||
338 | /* | |
339 | * For clock-event timers we never read the timer counter and | |
340 | * so we are not impacted by errata i103 and i767. Therefore, | |
341 | * we can safely ignore this errata for clock-event timers. | |
342 | */ | |
343 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | |
344 | ||
8f6924dc | 345 | res = omap_dm_timer_init_one(&clkev, fck_source, property, |
e95ea43a | 346 | &clockevent_gpt.name, OMAP_TIMER_POSTED); |
aa561889 | 347 | BUG_ON(res); |
f248076c | 348 | |
a032d33b | 349 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 350 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 351 | |
ee17f114 | 352 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 | 353 | |
11d6ec2e SS |
354 | clockevent_gpt.cpumask = cpu_possible_mask; |
355 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
838a2ae8 SG |
356 | clockevents_config_and_register(&clockevent_gpt, clkev.rate, |
357 | 3, /* Timer internal resynch latency */ | |
358 | 0xffffffff); | |
aa561889 | 359 | |
e95ea43a JH |
360 | pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, |
361 | clkev.rate); | |
5a3a388f KH |
362 | } |
363 | ||
f248076c | 364 | /* Clocksource code */ |
3d05a3e8 | 365 | static struct omap_dm_timer clksrc; |
332f1931 | 366 | static bool use_gptimer_clksrc __initdata; |
3d05a3e8 | 367 | |
5a3a388f KH |
368 | /* |
369 | * clocksource | |
370 | */ | |
8e19608e | 371 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 372 | { |
971d0254 | 373 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 374 | OMAP_TIMER_NONPOSTED); |
5a3a388f KH |
375 | } |
376 | ||
377 | static struct clocksource clocksource_gpt = { | |
5a3a388f KH |
378 | .rating = 300, |
379 | .read = clocksource_read_cycles, | |
380 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
381 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
382 | }; | |
383 | ||
f99ba47c | 384 | static u64 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 385 | { |
3d05a3e8 | 386 | if (clksrc.reserved) |
971d0254 | 387 | return __omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 388 | OMAP_TIMER_NONPOSTED); |
5a3a388f | 389 | |
2f0778af | 390 | return 0; |
3d05a3e8 TL |
391 | } |
392 | ||
31957609 | 393 | static const struct of_device_id omap_counter_match[] __initconst = { |
258e84af JH |
394 | { .compatible = "ti,omap-counter32k", }, |
395 | { } | |
396 | }; | |
397 | ||
3d05a3e8 | 398 | /* Setup free-running counter for clocksource */ |
e0c3e27c | 399 | static int __init __maybe_unused omap2_sync32k_clocksource_init(void) |
1fe97c8f VH |
400 | { |
401 | int ret; | |
9883f7c8 | 402 | struct device_node *np = NULL; |
1fe97c8f | 403 | struct omap_hwmod *oh; |
1fe97c8f VH |
404 | const char *oh_name = "counter_32k"; |
405 | ||
9883f7c8 JH |
406 | /* |
407 | * If device-tree is present, then search the DT blob | |
408 | * to see if the 32kHz counter is supported. | |
409 | */ | |
410 | if (of_have_populated_dt()) { | |
411 | np = omap_get_timer_dt(omap_counter_match, NULL); | |
412 | if (!np) | |
413 | return -ENODEV; | |
414 | ||
415 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
416 | if (!oh_name) | |
417 | return -ENODEV; | |
418 | } | |
419 | ||
1fe97c8f VH |
420 | /* |
421 | * First check hwmod data is available for sync32k counter | |
422 | */ | |
423 | oh = omap_hwmod_lookup(oh_name); | |
424 | if (!oh || oh->slaves_cnt == 0) | |
425 | return -ENODEV; | |
426 | ||
427 | omap_hwmod_setup_one(oh_name); | |
428 | ||
1fe97c8f VH |
429 | ret = omap_hwmod_enable(oh); |
430 | if (ret) { | |
431 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
432 | __func__, ret); | |
433 | return ret; | |
434 | } | |
435 | ||
bf4c9449 FB |
436 | if (!of_have_populated_dt()) { |
437 | void __iomem *vbase; | |
1fe97c8f | 438 | |
bf4c9449 | 439 | vbase = omap_hwmod_get_mpu_rt_va(oh); |
1fe97c8f | 440 | |
bf4c9449 FB |
441 | ret = omap_init_clocksource_32k(vbase); |
442 | if (ret) { | |
443 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
444 | __func__, ret); | |
445 | omap_hwmod_idle(oh); | |
446 | } | |
447 | } | |
1fe97c8f VH |
448 | return ret; |
449 | } | |
450 | ||
451 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
2eb03937 JH |
452 | const char *fck_source, |
453 | const char *property) | |
3d05a3e8 TL |
454 | { |
455 | int res; | |
456 | ||
8f6924dc | 457 | clksrc.id = gptimer_id; |
bfd6d021 JH |
458 | clksrc.errata = omap_dm_timer_get_errata(); |
459 | ||
8f6924dc | 460 | res = omap_dm_timer_init_one(&clksrc, fck_source, property, |
e95ea43a | 461 | &clocksource_gpt.name, |
bfd6d021 | 462 | OMAP_TIMER_NONPOSTED); |
3d05a3e8 | 463 | BUG_ON(res); |
5a3a388f | 464 | |
ee17f114 | 465 | __omap_dm_timer_load_start(&clksrc, |
971d0254 | 466 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
bfd6d021 | 467 | OMAP_TIMER_NONPOSTED); |
f99ba47c | 468 | sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 469 | |
3d05a3e8 TL |
470 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
471 | pr_err("Could not register clocksource %s\n", | |
472 | clocksource_gpt.name); | |
1fe97c8f | 473 | else |
e95ea43a JH |
474 | pr_info("OMAP clocksource: %s at %lu Hz\n", |
475 | clocksource_gpt.name, clksrc.rate); | |
1fe97c8f VH |
476 | } |
477 | ||
3afbb9af FB |
478 | static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src, |
479 | const char *clkev_prop, int clksrc_nr, const char *clksrc_src, | |
480 | const char *clksrc_prop, bool gptimer) | |
481 | { | |
482 | omap_clk_init(); | |
483 | omap_dmtimer_init(); | |
484 | omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop); | |
485 | ||
486 | /* Enable the use of clocksource="gp_timer" kernel parameter */ | |
487 | if (use_gptimer_clksrc || gptimer) | |
488 | omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src, | |
489 | clksrc_prop); | |
490 | else | |
491 | omap2_sync32k_clocksource_init(); | |
492 | } | |
493 | ||
6f82e25d | 494 | void __init omap_init_time(void) |
3afbb9af FB |
495 | { |
496 | __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", | |
497 | 2, "timer_sys_ck", NULL, false); | |
9c46ffcd FB |
498 | |
499 | if (of_have_populated_dt()) | |
a5e1d715 | 500 | clocksource_probe(); |
3afbb9af FB |
501 | } |
502 | ||
503 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) | |
504 | void __init omap3_secure_sync32k_timer_init(void) | |
505 | { | |
506 | __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", | |
507 | 2, "timer_sys_ck", NULL, false); | |
508 | } | |
509 | #endif /* CONFIG_ARCH_OMAP3 */ | |
510 | ||
511 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) | |
512 | void __init omap3_gptimer_timer_init(void) | |
513 | { | |
514 | __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, | |
515 | 1, "timer_sys_ck", "ti,timer-alwon", true); | |
516 | } | |
517 | #endif | |
518 | ||
519 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ | |
520 | defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX) | |
521 | static void __init omap4_sync32k_timer_init(void) | |
522 | { | |
523 | __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", | |
524 | 2, "sys_clkin_ck", NULL, false); | |
525 | } | |
526 | ||
527 | void __init omap4_local_timer_init(void) | |
528 | { | |
529 | omap4_sync32k_timer_init(); | |
a5e1d715 | 530 | clocksource_probe(); |
3afbb9af FB |
531 | } |
532 | #endif | |
533 | ||
534 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) | |
535 | ||
fa6d79d2 SS |
536 | /* |
537 | * The realtime counter also called master counter, is a free-running | |
538 | * counter, which is related to real time. It produces the count used | |
539 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
540 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
541 | * in different power modes, the master counter shifts operation between | |
542 | * clocks, adjusting the increment per clock in hardware accordingly to | |
543 | * maintain a constant count rate. | |
544 | */ | |
545 | static void __init realtime_counter_init(void) | |
546 | { | |
3afbb9af | 547 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
fa6d79d2 SS |
548 | void __iomem *base; |
549 | static struct clk *sys_clk; | |
550 | unsigned long rate; | |
afc9d590 LS |
551 | unsigned int reg; |
552 | unsigned long long num, den; | |
fa6d79d2 SS |
553 | |
554 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
555 | if (!base) { | |
556 | pr_err("%s: ioremap failed\n", __func__); | |
557 | return; | |
558 | } | |
7f585bbf | 559 | sys_clk = clk_get(NULL, "sys_clkin"); |
533b2981 | 560 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
561 | pr_err("%s: failed to get system clock handle\n", __func__); |
562 | iounmap(base); | |
563 | return; | |
564 | } | |
565 | ||
566 | rate = clk_get_rate(sys_clk); | |
afc9d590 LS |
567 | |
568 | if (soc_is_dra7xx()) { | |
569 | /* | |
570 | * Errata i856 says the 32.768KHz crystal does not start at | |
571 | * power on, so the CPU falls back to an emulated 32KHz clock | |
572 | * based on sysclk / 610 instead. This causes the master counter | |
573 | * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 | |
574 | * (OR sysclk * 75 / 244) | |
575 | * | |
576 | * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. | |
577 | * Of course any board built without a populated 32.768KHz | |
578 | * crystal would also need this fix even if the CPU is fixed | |
579 | * later. | |
580 | * | |
581 | * Either case can be detected by using the two speedselect bits | |
582 | * If they are not 0, then the 32.768KHz clock driving the | |
583 | * coarse counter that corrects the fine counter every time it | |
584 | * ticks is actually rate/610 rather than 32.768KHz and we | |
585 | * should compensate to avoid the 570ppm (at 20MHz, much worse | |
586 | * at other rates) too fast system time. | |
587 | */ | |
588 | reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); | |
589 | if (reg & DRA7_SPEEDSELECT_MASK) { | |
590 | num = 75; | |
591 | den = 244; | |
592 | goto sysclk1_based; | |
593 | } | |
594 | } | |
595 | ||
fa6d79d2 SS |
596 | /* Numerator/denumerator values refer TRM Realtime Counter section */ |
597 | switch (rate) { | |
572b24e6 | 598 | case 12000000: |
fa6d79d2 SS |
599 | num = 64; |
600 | den = 125; | |
601 | break; | |
572b24e6 | 602 | case 13000000: |
fa6d79d2 SS |
603 | num = 768; |
604 | den = 1625; | |
605 | break; | |
606 | case 19200000: | |
607 | num = 8; | |
608 | den = 25; | |
609 | break; | |
38a1981c S |
610 | case 20000000: |
611 | num = 192; | |
612 | den = 625; | |
613 | break; | |
572b24e6 | 614 | case 26000000: |
fa6d79d2 SS |
615 | num = 384; |
616 | den = 1625; | |
617 | break; | |
572b24e6 | 618 | case 27000000: |
fa6d79d2 SS |
619 | num = 256; |
620 | den = 1125; | |
621 | break; | |
622 | case 38400000: | |
623 | default: | |
624 | /* Program it for 38.4 MHz */ | |
625 | num = 4; | |
626 | den = 25; | |
627 | break; | |
628 | } | |
629 | ||
afc9d590 | 630 | sysclk1_based: |
fa6d79d2 | 631 | /* Program numerator and denumerator registers */ |
edfaf05c | 632 | reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & |
fa6d79d2 SS |
633 | NUMERATOR_DENUMERATOR_MASK; |
634 | reg |= num; | |
edfaf05c | 635 | writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); |
fa6d79d2 | 636 | |
edfaf05c | 637 | reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & |
fa6d79d2 SS |
638 | NUMERATOR_DENUMERATOR_MASK; |
639 | reg |= den; | |
edfaf05c | 640 | writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); |
fa6d79d2 | 641 | |
afc9d590 | 642 | arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); |
5523e409 S |
643 | set_cntfreq(); |
644 | ||
fa6d79d2 | 645 | iounmap(base); |
fa6d79d2 | 646 | #endif |
6f80b3bb IG |
647 | } |
648 | ||
6bb27d73 | 649 | void __init omap5_realtime_timer_init(void) |
fa6d79d2 | 650 | { |
00ea4d56 | 651 | omap4_sync32k_timer_init(); |
fa6d79d2 | 652 | realtime_counter_init(); |
3c7c5dab | 653 | |
3722ed23 | 654 | clocksource_probe(); |
fa6d79d2 | 655 | } |
0b8214fe | 656 | #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ |
37b3280d | 657 | |
c345c8b0 TKD |
658 | /** |
659 | * omap_timer_init - build and register timer device with an | |
660 | * associated timer hwmod | |
661 | * @oh: timer hwmod pointer to be used to build timer device | |
662 | * @user: parameter that can be passed from calling hwmod API | |
663 | * | |
664 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
665 | * devices present in the system. The number of timer devices is known | |
666 | * by parsing through the hwmod database for a given class name. At the | |
667 | * end of function call memory is allocated for timer device and it is | |
668 | * registered to the framework ready to be proved by the driver. | |
669 | */ | |
670 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
671 | { | |
672 | int id; | |
673 | int ret = 0; | |
674 | char *name = "omap_timer"; | |
675 | struct dmtimer_platform_data *pdata; | |
c541c15f | 676 | struct platform_device *pdev; |
c345c8b0 TKD |
677 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
678 | ||
679 | pr_debug("%s: %s\n", __func__, oh->name); | |
680 | ||
681 | /* on secure device, do not register secure timer */ | |
682 | timer_dev_attr = oh->dev_attr; | |
683 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
684 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
685 | return ret; | |
686 | ||
687 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
688 | if (!pdata) { | |
689 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
690 | return -ENOMEM; | |
691 | } | |
692 | ||
693 | /* | |
694 | * Extract the IDs from name field in hwmod database | |
695 | * and use the same for constructing ids' for the | |
696 | * timer devices. In a way, we are avoiding usage of | |
697 | * static variable witin the function to do the same. | |
698 | * CAUTION: We have to be careful and make sure the | |
699 | * name in hwmod database does not change in which case | |
700 | * we might either make corresponding change here or | |
701 | * switch back static variable mechanism. | |
702 | */ | |
703 | sscanf(oh->name, "timer%2d", &id); | |
704 | ||
d1c1691b JH |
705 | if (timer_dev_attr) |
706 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 707 | |
bfd6d021 | 708 | pdata->timer_errata = omap_dm_timer_get_errata(); |
6e740f9a TL |
709 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; |
710 | ||
c1d1cd59 | 711 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); |
c345c8b0 | 712 | |
c541c15f | 713 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
714 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
715 | __func__, name, oh->name); | |
716 | ret = -EINVAL; | |
717 | } | |
718 | ||
719 | kfree(pdata); | |
720 | ||
721 | return ret; | |
722 | } | |
3392cdd3 TKD |
723 | |
724 | /** | |
725 | * omap2_dm_timer_init - top level regular device initialization | |
726 | * | |
727 | * Uses dedicated hwmod api to parse through hwmod database for | |
728 | * given class name and then build and register the timer device. | |
729 | */ | |
730 | static int __init omap2_dm_timer_init(void) | |
731 | { | |
732 | int ret; | |
733 | ||
9725f445 JH |
734 | /* If dtb is there, the devices will be created dynamically */ |
735 | if (of_have_populated_dt()) | |
736 | return -ENODEV; | |
737 | ||
3392cdd3 TKD |
738 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); |
739 | if (unlikely(ret)) { | |
740 | pr_err("%s: device registration failed.\n", __func__); | |
741 | return -EINVAL; | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
b76c8b19 | 746 | omap_arch_initcall(omap2_dm_timer_init); |
1fe97c8f VH |
747 | |
748 | /** | |
749 | * omap2_override_clocksource - clocksource override with user configuration | |
750 | * | |
751 | * Allows user to override default clocksource, using kernel parameter | |
752 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
753 | * | |
754 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
755 | * and not introducing any OMAP specific interface. | |
756 | */ | |
757 | static int __init omap2_override_clocksource(char *str) | |
758 | { | |
759 | if (!str) | |
760 | return 0; | |
761 | /* | |
762 | * For OMAP architecture, we only have two options | |
763 | * - sync_32k (default) | |
764 | * - gp_timer (sys_clk based) | |
765 | */ | |
766 | if (!strcmp(str, "gp_timer")) | |
767 | use_gptimer_clksrc = true; | |
768 | ||
769 | return 0; | |
770 | } | |
771 | early_param("clocksource", omap2_override_clocksource); |