[deliverable/linux.git] / arch / arm / mach-omap2 / timer.c

/*
 * linux/arch/arm/mach-omap2/timer.c
 *
 * OMAP2 GP timer support.
 *
 * Copyright (C) 2009 Nokia Corporation
 *
 * Update to use new clocksource/clockevent layers
 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
 * Copyright (C) 2007 MontaVista Software, Inc.
 *
 * Original driver:
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *         Juha Yrjölä <juha.yrjola@nokia.com>
 * OMAP Dual-mode timer framework support by Timo Teras
 *
 * Some parts based off of TI's 24xx code:
 *
 * Copyright (C) 2004-2009 Texas Instruments, Inc.
 *
 * Roughly modelled after the OMAP1 MPU timer code.
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/slab.h>

#include <asm/mach/time.h>
#include <plat/dmtimer.h>
#include <asm/smp_twd.h>
#include <asm/sched_clock.h>
#include "common.h"
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>

#include "powerdomain.h"

/* Parent clocks, eventually these will come from the clock framework */

#define OMAP2_MPU_SOURCE	"sys_ck"
#define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
#define OMAP4_MPU_SOURCE	"sys_clkin_ck"
#define OMAP2_32K_SOURCE	"func_32k_ck"
#define OMAP3_32K_SOURCE	"omap_32k_fck"
#define OMAP4_32K_SOURCE	"sys_32k_ck"

#ifdef CONFIG_OMAP_32K_TIMER
#define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
#define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
#define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
#define OMAP3_SECURE_TIMER	12
#else
#define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
#define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
#define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
#define OMAP3_SECURE_TIMER	1
#endif

/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
#define MAX_GPTIMER_ID		12

static u32 sys_timer_reserved;

/* Clockevent code */

static struct omap_dm_timer clkev;
static struct clock_event_device clockevent_gpt;

static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_gpt;

	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction omap2_gp_timer_irq = {
	.name		= "gp_timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= omap2_gp_timer_interrupt,
};

static int omap2_gp_timer_set_next_event(unsigned long cycles,
					 struct clock_event_device *evt)
{
	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
						0xffffffff - cycles, 1);

	return 0;
}

static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *evt)
{
	u32 period;

	__omap_dm_timer_stop(&clkev, 1, clkev.rate);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		period = clkev.rate / HZ;
		period -= 1;
		/* Looks like we need to first set the load value separately */
		__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
					0xffffffff - period, 1);
		__omap_dm_timer_load_start(&clkev,
					OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
						0xffffffff - period, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device clockevent_gpt = {
	.name		= "gp_timer",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.set_next_event	= omap2_gp_timer_set_next_event,
	.set_mode	= omap2_gp_timer_set_mode,
};

static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
						int gptimer_id,
						const char *fck_source)
{
	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
	struct omap_hwmod *oh;
	struct resource irq_rsrc, mem_rsrc;
	size_t size;
	int res = 0;
	int r;

	sprintf(name, "timer%d", gptimer_id);
	omap_hwmod_setup_one(name);
	oh = omap_hwmod_lookup(name);
	if (!oh)
		return -ENODEV;

	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
	if (r)
		return -ENXIO;
	timer->irq = irq_rsrc.start;

	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
	if (r)
		return -ENXIO;
	timer->phys_base = mem_rsrc.start;
	size = mem_rsrc.end - mem_rsrc.start;

	/* Static mapping, never released */
	timer->io_base = ioremap(timer->phys_base, size);
	if (!timer->io_base)
		return -ENXIO;

	/* After the dmtimer is using hwmod these clocks won't be needed */
	sprintf(name, "gpt%d_fck", gptimer_id);
	timer->fclk = clk_get(NULL, name);
	if (IS_ERR(timer->fclk))
		return -ENODEV;

	omap_hwmod_enable(oh);

	sys_timer_reserved |= (1 << (gptimer_id - 1));

	if (gptimer_id != 12) {
		struct clk *src;

		src = clk_get(NULL, fck_source);
		if (IS_ERR(src)) {
			res = -EINVAL;
		} else {
			res = __omap_dm_timer_set_source(timer->fclk, src);
			if (IS_ERR_VALUE(res))
				pr_warning("%s: timer%i cannot set source\n",
						__func__, gptimer_id);
			clk_put(src);
		}
	}
	__omap_dm_timer_init_regs(timer);
	__omap_dm_timer_reset(timer, 1, 1);
	timer->posted = 1;

	timer->rate = clk_get_rate(timer->fclk);

	timer->reserved = 1;

	return res;
}

static void __init omap2_gp_clockevent_init(int gptimer_id,
						const char *fck_source)
{
	int res;

	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
	BUG_ON(res);

	omap2_gp_timer_irq.dev_id = (void *)&clkev;
	setup_irq(clkev.irq, &omap2_gp_timer_irq);

	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);

	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
				     clockevent_gpt.shift);
	clockevent_gpt.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &clockevent_gpt);
	clockevent_gpt.min_delta_ns =
		clockevent_delta2ns(3, &clockevent_gpt);
		/* Timer internal resynch latency. */

	clockevent_gpt.cpumask = cpumask_of(0);
	clockevents_register_device(&clockevent_gpt);

	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
		gptimer_id, clkev.rate);
}

/* Clocksource code */
static struct omap_dm_timer clksrc;
static bool use_gptimer_clksrc;

/*
 * clocksource
 */
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
}

static struct clocksource clocksource_gpt = {
	.name		= "gp_timer",
	.rating		= 300,
	.read		= clocksource_read_cycles,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static u32 notrace dmtimer_read_sched_clock(void)
{
	if (clksrc.reserved)
		return __omap_dm_timer_read_counter(&clksrc, 1);

	return 0;
}

/* Setup free-running counter for clocksource */
static int __init omap2_sync32k_clocksource_init(void)
{
	int ret;
	struct omap_hwmod *oh;
	void __iomem *vbase;
	const char *oh_name = "counter_32k";

	/*
	 * First check hwmod data is available for sync32k counter
	 */
	oh = omap_hwmod_lookup(oh_name);
	if (!oh || oh->slaves_cnt == 0)
		return -ENODEV;

	omap_hwmod_setup_one(oh_name);

	vbase = omap_hwmod_get_mpu_rt_va(oh);
	if (!vbase) {
		pr_warn("%s: failed to get counter_32k resource\n", __func__);
		return -ENXIO;
	}

	ret = omap_hwmod_enable(oh);
	if (ret) {
		pr_warn("%s: failed to enable counter_32k module (%d)\n",
							__func__, ret);
		return ret;
	}

	ret = omap_init_clocksource_32k(vbase);
	if (ret) {
		pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
							__func__, ret);
		omap_hwmod_idle(oh);
	}

	return ret;
}

static void __init omap2_gptimer_clocksource_init(int gptimer_id,
						const char *fck_source)
{
	int res;

	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
	BUG_ON(res);

	__omap_dm_timer_load_start(&clksrc,
			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
	setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);

	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
		pr_err("Could not register clocksource %s\n",
			clocksource_gpt.name);
	else
		pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
			gptimer_id, clksrc.rate);
}

static void __init omap2_clocksource_init(int gptimer_id,
						const char *fck_source)
{
	/*
	 * First give preference to kernel parameter configuration
	 * by user (clocksource="gp_timer").
	 *
	 * In case of missing kernel parameter for clocksource,
	 * first check for availability for 32k-sync timer, in case
	 * of failure in finding 32k_counter module or registering
	 * it as clocksource, execution will fallback to gp-timer.
	 */
	if (use_gptimer_clksrc == true)
		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
	else if (omap2_sync32k_clocksource_init())
		/* Fall back to gp-timer code */
		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
}

#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
				clksrc_nr, clksrc_src)			\
static void __init omap##name##_timer_init(void)			\
{									\
	omap2_gp_clockevent_init((clkev_nr), clkev_src);		\
	omap2_clocksource_init((clksrc_nr), clksrc_src);		\
}

#define OMAP_SYS_TIMER(name)						\
struct sys_timer omap##name##_timer = {					\
	.init	= omap##name##_timer_init,				\
};

#ifdef CONFIG_ARCH_OMAP2
OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
OMAP_SYS_TIMER(2)
#endif

#ifdef CONFIG_ARCH_OMAP3
OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3)
OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
			2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3_secure)
#endif

#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_LOCAL_TIMERS
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
			      OMAP44XX_LOCAL_TWD_BASE,
			      OMAP44XX_IRQ_LOCALTIMER);
#endif

static void __init omap4_timer_init(void)
{
	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
#ifdef CONFIG_LOCAL_TIMERS
	/* Local timers are not supprted on OMAP4430 ES1.0 */
	if (omap_rev() != OMAP4430_REV_ES1_0) {
		int err;

		err = twd_local_timer_register(&twd_local_timer);
		if (err)
			pr_err("twd_local_timer_register failed %d\n", err);
	}
#endif
}
OMAP_SYS_TIMER(4)
#endif

/**
 * omap2_dm_timer_set_src - change the timer input clock source
 * @pdev:	timer platform device pointer
 * @source:	array index of parent clock source
 */
static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
{
	int ret;
	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
	struct clk *fclk, *parent;
	char *parent_name = NULL;

	fclk = clk_get(&pdev->dev, "fck");
	if (IS_ERR_OR_NULL(fclk)) {
		dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
				__func__, __LINE__);
		return -EINVAL;
	}

	switch (source) {
	case OMAP_TIMER_SRC_SYS_CLK:
		parent_name = "sys_ck";
		break;

	case OMAP_TIMER_SRC_32_KHZ:
		parent_name = "32k_ck";
		break;

	case OMAP_TIMER_SRC_EXT_CLK:
		if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
			parent_name = "alt_ck";
			break;
		}
		dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
			__func__, __LINE__);
		clk_put(fclk);
		return -EINVAL;
	}

	parent = clk_get(&pdev->dev, parent_name);
	if (IS_ERR_OR_NULL(parent)) {
		dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
			__func__, __LINE__, parent_name);
		clk_put(fclk);
		return -EINVAL;
	}

	ret = clk_set_parent(fclk, parent);
	if (IS_ERR_VALUE(ret)) {
		dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
			__func__, parent_name);
		ret = -EINVAL;
	}

	clk_put(parent);
	clk_put(fclk);

	return ret;
}

/**
 * omap_timer_init - build and register timer device with an
 * associated timer hwmod
 * @oh:	timer hwmod pointer to be used to build timer device
 * @user:	parameter that can be passed from calling hwmod API
 *
 * Called by omap_hwmod_for_each_by_class to register each of the timer
 * devices present in the system. The number of timer devices is known
 * by parsing through the hwmod database for a given class name. At the
 * end of function call memory is allocated for timer device and it is
 * registered to the framework ready to be proved by the driver.
 */
static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
{
	int id;
	int ret = 0;
	char *name = "omap_timer";
	struct dmtimer_platform_data *pdata;
	struct platform_device *pdev;
	struct omap_timer_capability_dev_attr *timer_dev_attr;
	struct powerdomain *pwrdm;

	pr_debug("%s: %s\n", __func__, oh->name);

	/* on secure device, do not register secure timer */
	timer_dev_attr = oh->dev_attr;
	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
		if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
			return ret;

	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	if (!pdata) {
		pr_err("%s: No memory for [%s]\n", __func__, oh->name);
		return -ENOMEM;
	}

	/*
	 * Extract the IDs from name field in hwmod database
	 * and use the same for constructing ids' for the
	 * timer devices. In a way, we are avoiding usage of
	 * static variable witin the function to do the same.
	 * CAUTION: We have to be careful and make sure the
	 * name in hwmod database does not change in which case
	 * we might either make corresponding change here or
	 * switch back static variable mechanism.
	 */
	sscanf(oh->name, "timer%2d", &id);

	pdata->set_timer_src = omap2_dm_timer_set_src;
	pdata->timer_ip_version = oh->class->rev;

	/* Mark clocksource and clockevent timers as reserved */
	if ((sys_timer_reserved >> (id - 1)) & 0x1)
		pdata->reserved = 1;

	pwrdm = omap_hwmod_get_pwrdm(oh);
	pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
#ifdef CONFIG_PM
	pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
#endif
	pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
				 NULL, 0, 0);

	if (IS_ERR(pdev)) {
		pr_err("%s: Can't build omap_device for %s: %s.\n",
			__func__, name, oh->name);
		ret = -EINVAL;
	}

	kfree(pdata);

	return ret;
}

/**
 * omap2_dm_timer_init - top level regular device initialization
 *
 * Uses dedicated hwmod api to parse through hwmod database for
 * given class name and then build and register the timer device.
 */
static int __init omap2_dm_timer_init(void)
{
	int ret;

	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
	if (unlikely(ret)) {
		pr_err("%s: device registration failed.\n", __func__);
		return -EINVAL;
	}

	return 0;
}
arch_initcall(omap2_dm_timer_init);

/**
 * omap2_override_clocksource - clocksource override with user configuration
 *
 * Allows user to override default clocksource, using kernel parameter
 *   clocksource="gp_timer"	(For all OMAP2PLUS architectures)
 *
 * Note that, here we are using same standard kernel parameter "clocksource=",
 * and not introducing any OMAP specific interface.
 */
static int __init omap2_override_clocksource(char *str)
{
	if (!str)
		return 0;
	/*
	 * For OMAP architecture, we only have two options
	 *    - sync_32k (default)
	 *    - gp_timer (sys_clk based)
	 */
	if (!strcmp(str, "gp_timer"))
		use_gptimer_clksrc = true;

	return 0;
}
early_param("clocksource", omap2_override_clocksource);
Commit	Line	Data
1dbae815	1	/*
0f622e8c	2	* linux/arch/arm/mach-omap2/timer.c
1dbae815 TL	3	*
	4	* OMAP2 GP timer support.
	5	*
f248076c PW	6	* Copyright (C) 2009 Nokia Corporation
f248076c PW	7	*
5a3a388f KH	8	* Update to use new clocksource/clockevent layers
	9	* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
	10	* Copyright (C) 2007 MontaVista Software, Inc.
	11	*
	12	* Original driver:
1dbae815 TL	13	* Copyright (C) 2005 Nokia Corporation
1dbae815 TL	14	* Author: Paul Mundt <paul.mundt@nokia.com>
96de0e25	15	* Juha Yrjölä <juha.yrjola@nokia.com>
77900a2f	16	* OMAP Dual-mode timer framework support by Timo Teras
1dbae815 TL	17	*
	18	* Some parts based off of TI's 24xx code:
	19	*
44169075	20	* Copyright (C) 2004-2009 Texas Instruments, Inc.
1dbae815 TL	21	*
1dbae815 TL	22	* Roughly modelled after the OMAP1 MPU timer code.
44169075	23	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
1dbae815 TL	24	*
	25	* This file is subject to the terms and conditions of the GNU General Public
	26	* License. See the file "COPYING" in the main directory of this archive
	27	* for more details.
	28	*/
	29	#include <linux/init.h>
	30	#include <linux/time.h>
	31	#include <linux/interrupt.h>
	32	#include <linux/err.h>
f8ce2547	33	#include <linux/clk.h>
77900a2f	34	#include <linux/delay.h>
e6687290	35	#include <linux/irq.h>
5a3a388f KH	36	#include <linux/clocksource.h>
5a3a388f KH	37	#include <linux/clockchips.h>
c345c8b0	38	#include <linux/slab.h>
f8ce2547	39
1dbae815	40	#include <asm/mach/time.h>
ce491cf8	41	#include <plat/dmtimer.h>
a45c983f	42	#include <asm/smp_twd.h>
cbc94380	43	#include <asm/sched_clock.h>
4e65331c	44	#include "common.h"
38698bef	45	#include <plat/omap_hwmod.h>
c345c8b0	46	#include <plat/omap_device.h>
b481113a TKD	47	#include <plat/omap-pm.h>
	48
	49	#include "powerdomain.h"
1dbae815	50
aa561889 TL	51	/* Parent clocks, eventually these will come from the clock framework */
	52
	53	#define OMAP2_MPU_SOURCE "sys_ck"
	54	#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
	55	#define OMAP4_MPU_SOURCE "sys_clkin_ck"
	56	#define OMAP2_32K_SOURCE "func_32k_ck"
	57	#define OMAP3_32K_SOURCE "omap_32k_fck"
	58	#define OMAP4_32K_SOURCE "sys_32k_ck"
	59
	60	#ifdef CONFIG_OMAP_32K_TIMER
	61	#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
	62	#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
	63	#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
	64	#define OMAP3_SECURE_TIMER 12
	65	#else
	66	#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
	67	#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
	68	#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
	69	#define OMAP3_SECURE_TIMER 1
	70	#endif
d8328f3b	71
f248076c PW	72	/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
	73	#define MAX_GPTIMER_ID 12
	74
0dad9fae	75	static u32 sys_timer_reserved;
11a0186f	76
aa561889 TL	77	/* Clockevent code */
	78
	79	static struct omap_dm_timer clkev;
5a3a388f	80	static struct clock_event_device clockevent_gpt;
1dbae815	81
0cd61b68	82	static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
1dbae815	83	{
5a3a388f KH	84	struct clock_event_device *evt = &clockevent_gpt;
5a3a388f KH	85
ee17f114	86	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
1dbae815	87
5a3a388f	88	evt->event_handler(evt);
1dbae815 TL	89	return IRQ_HANDLED;
	90	}
	91
	92	static struct irqaction omap2_gp_timer_irq = {
f36921be	93	.name = "gp_timer",
b30fabad	94	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
1dbae815 TL	95	.handler = omap2_gp_timer_interrupt,
	96	};
	97
5a3a388f KH	98	static int omap2_gp_timer_set_next_event(unsigned long cycles,
5a3a388f KH	99	struct clock_event_device *evt)
1dbae815	100	{
ee17f114	101	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
aa561889	102	0xffffffff - cycles, 1);
5a3a388f KH	103
	104	return 0;
	105	}
	106
	107	static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
	108	struct clock_event_device *evt)
	109	{
	110	u32 period;
	111
ee17f114	112	__omap_dm_timer_stop(&clkev, 1, clkev.rate);
5a3a388f KH	113
	114	switch (mode) {
	115	case CLOCK_EVT_MODE_PERIODIC:
aa561889	116	period = clkev.rate / HZ;
5a3a388f	117	period -= 1;
aa561889	118	/* Looks like we need to first set the load value separately */
ee17f114	119	__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
aa561889	120	0xffffffff - period, 1);
ee17f114	121	__omap_dm_timer_load_start(&clkev,
aa561889 TL	122	OMAP_TIMER_CTRL_AR \| OMAP_TIMER_CTRL_ST,
aa561889 TL	123	0xffffffff - period, 1);
5a3a388f KH	124	break;
	125	case CLOCK_EVT_MODE_ONESHOT:
	126	break;
	127	case CLOCK_EVT_MODE_UNUSED:
	128	case CLOCK_EVT_MODE_SHUTDOWN:
	129	case CLOCK_EVT_MODE_RESUME:
	130	break;
	131	}
	132	}
	133
	134	static struct clock_event_device clockevent_gpt = {
f36921be	135	.name = "gp_timer",
5a3a388f KH	136	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	137	.shift = 32,
	138	.set_next_event = omap2_gp_timer_set_next_event,
	139	.set_mode = omap2_gp_timer_set_mode,
	140	};
	141
aa561889 TL	142	static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
	143	int gptimer_id,
	144	const char *fck_source)
5a3a388f	145	{
aa561889 TL	146	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
aa561889 TL	147	struct omap_hwmod *oh;
6c0c27fd	148	struct resource irq_rsrc, mem_rsrc;
aa561889 TL	149	size_t size;
aa561889 TL	150	int res = 0;
6c0c27fd	151	int r;
aa561889 TL	152
	153	sprintf(name, "timer%d", gptimer_id);
	154	omap_hwmod_setup_one(name);
	155	oh = omap_hwmod_lookup(name);
	156	if (!oh)
	157	return -ENODEV;
	158
6c0c27fd PW	159	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
	160	if (r)
	161	return -ENXIO;
	162	timer->irq = irq_rsrc.start;
	163
	164	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
	165	if (r)
	166	return -ENXIO;
	167	timer->phys_base = mem_rsrc.start;
	168	size = mem_rsrc.end - mem_rsrc.start;
aa561889 TL	169
	170	/* Static mapping, never released */
	171	timer->io_base = ioremap(timer->phys_base, size);
	172	if (!timer->io_base)
	173	return -ENXIO;
	174
	175	/* After the dmtimer is using hwmod these clocks won't be needed */
	176	sprintf(name, "gpt%d_fck", gptimer_id);
	177	timer->fclk = clk_get(NULL, name);
	178	if (IS_ERR(timer->fclk))
	179	return -ENODEV;
	180
aa561889 TL	181	omap_hwmod_enable(oh);
aa561889 TL	182
11a0186f TL	183	sys_timer_reserved \|= (1 << (gptimer_id - 1));
11a0186f TL	184
aa561889 TL	185	if (gptimer_id != 12) {
	186	struct clk *src;
	187
	188	src = clk_get(NULL, fck_source);
	189	if (IS_ERR(src)) {
	190	res = -EINVAL;
	191	} else {
	192	res = __omap_dm_timer_set_source(timer->fclk, src);
	193	if (IS_ERR_VALUE(res))
	194	pr_warning("%s: timer%i cannot set source\n",
	195	__func__, gptimer_id);
	196	clk_put(src);
	197	}
	198	}
ee17f114 TL	199	__omap_dm_timer_init_regs(timer);
ee17f114 TL	200	__omap_dm_timer_reset(timer, 1, 1);
aa561889 TL	201	timer->posted = 1;
	202
	203	timer->rate = clk_get_rate(timer->fclk);
1dbae815	204
aa561889	205	timer->reserved = 1;
38698bef	206
aa561889 TL	207	return res;
aa561889 TL	208	}
f248076c	209
aa561889 TL	210	static void __init omap2_gp_clockevent_init(int gptimer_id,
	211	const char *fck_source)
	212	{
	213	int res;
f248076c	214
aa561889 TL	215	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
aa561889 TL	216	BUG_ON(res);
f248076c	217
98e182a2	218	omap2_gp_timer_irq.dev_id = (void *)&clkev;
aa561889	219	setup_irq(clkev.irq, &omap2_gp_timer_irq);
5a3a388f	220
ee17f114	221	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
aa561889 TL	222
aa561889 TL	223	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
5a3a388f KH	224	clockevent_gpt.shift);
	225	clockevent_gpt.max_delta_ns =
	226	clockevent_delta2ns(0xffffffff, &clockevent_gpt);
	227	clockevent_gpt.min_delta_ns =
df88acbb AK	228	clockevent_delta2ns(3, &clockevent_gpt);
df88acbb AK	229	/* Timer internal resynch latency. */
5a3a388f	230
320ab2b0	231	clockevent_gpt.cpumask = cpumask_of(0);
5a3a388f	232	clockevents_register_device(&clockevent_gpt);
aa561889 TL	233
	234	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
	235	gptimer_id, clkev.rate);
5a3a388f KH	236	}
5a3a388f KH	237
f248076c	238	/* Clocksource code */
3d05a3e8	239	static struct omap_dm_timer clksrc;
1fe97c8f	240	static bool use_gptimer_clksrc;
3d05a3e8	241
5a3a388f KH	242	/*
	243	* clocksource
	244	*/
8e19608e	245	static cycle_t clocksource_read_cycles(struct clocksource *cs)
5a3a388f	246	{
ee17f114	247	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
5a3a388f KH	248	}
	249
	250	static struct clocksource clocksource_gpt = {
f36921be	251	.name = "gp_timer",
5a3a388f KH	252	.rating = 300,
	253	.read = clocksource_read_cycles,
	254	.mask = CLOCKSOURCE_MASK(32),
5a3a388f KH	255	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	256	};
	257
2f0778af	258	static u32 notrace dmtimer_read_sched_clock(void)
cbc94380	259	{
3d05a3e8	260	if (clksrc.reserved)
dbc3982a	261	return __omap_dm_timer_read_counter(&clksrc, 1);
5a3a388f	262
2f0778af	263	return 0;
3d05a3e8 TL	264	}
	265
	266	/* Setup free-running counter for clocksource */
1fe97c8f VH	267	static int __init omap2_sync32k_clocksource_init(void)
	268	{
	269	int ret;
	270	struct omap_hwmod *oh;
	271	void __iomem *vbase;
	272	const char *oh_name = "counter_32k";
	273
	274	/*
	275	* First check hwmod data is available for sync32k counter
	276	*/
	277	oh = omap_hwmod_lookup(oh_name);
	278	if (!oh \|\| oh->slaves_cnt == 0)
	279	return -ENODEV;
	280
	281	omap_hwmod_setup_one(oh_name);
	282
	283	vbase = omap_hwmod_get_mpu_rt_va(oh);
	284	if (!vbase) {
	285	pr_warn("%s: failed to get counter_32k resource\n", __func__);
	286	return -ENXIO;
	287	}
	288
	289	ret = omap_hwmod_enable(oh);
	290	if (ret) {
	291	pr_warn("%s: failed to enable counter_32k module (%d)\n",
	292	__func__, ret);
	293	return ret;
	294	}
	295
	296	ret = omap_init_clocksource_32k(vbase);
	297	if (ret) {
	298	pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
	299	__func__, ret);
	300	omap_hwmod_idle(oh);
	301	}
	302
	303	return ret;
	304	}
	305
	306	static void __init omap2_gptimer_clocksource_init(int gptimer_id,
3d05a3e8 TL	307	const char *fck_source)
	308	{
	309	int res;
	310
	311	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
	312	BUG_ON(res);
5a3a388f	313
ee17f114	314	__omap_dm_timer_load_start(&clksrc,
e9d0b97e	315	OMAP_TIMER_CTRL_ST \| OMAP_TIMER_CTRL_AR, 0, 1);
2f0778af	316	setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
cbc94380	317
3d05a3e8 TL	318	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
	319	pr_err("Could not register clocksource %s\n",
	320	clocksource_gpt.name);
1fe97c8f VH	321	else
	322	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
	323	gptimer_id, clksrc.rate);
	324	}
	325
	326	static void __init omap2_clocksource_init(int gptimer_id,
	327	const char *fck_source)
	328	{
	329	/*
	330	* First give preference to kernel parameter configuration
	331	* by user (clocksource="gp_timer").
	332	*
	333	* In case of missing kernel parameter for clocksource,
	334	* first check for availability for 32k-sync timer, in case
	335	* of failure in finding 32k_counter module or registering
	336	* it as clocksource, execution will fallback to gp-timer.
	337	*/
	338	if (use_gptimer_clksrc == true)
	339	omap2_gptimer_clocksource_init(gptimer_id, fck_source);
	340	else if (omap2_sync32k_clocksource_init())
	341	/* Fall back to gp-timer code */
	342	omap2_gptimer_clocksource_init(gptimer_id, fck_source);
5a3a388f	343	}
5a3a388f	344
3d05a3e8 TL	345	#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
3d05a3e8 TL	346	clksrc_nr, clksrc_src) \
e74984e4 TL	347	static void __init omap##name##_timer_init(void) \
e74984e4 TL	348	{ \
aa561889	349	omap2_gp_clockevent_init((clkev_nr), clkev_src); \
1fe97c8f	350	omap2_clocksource_init((clksrc_nr), clksrc_src); \
e74984e4 TL	351	}
	352
	353	#define OMAP_SYS_TIMER(name) \
	354	struct sys_timer omap##name##_timer = { \
	355	.init = omap##name##_timer_init, \
	356	};
	357
	358	#ifdef CONFIG_ARCH_OMAP2
3d05a3e8	359	OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
e74984e4 TL	360	OMAP_SYS_TIMER(2)
	361	#endif
	362
	363	#ifdef CONFIG_ARCH_OMAP3
3d05a3e8	364	OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
e74984e4	365	OMAP_SYS_TIMER(3)
3d05a3e8 TL	366	OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
3d05a3e8 TL	367	2, OMAP3_MPU_SOURCE)
e74984e4 TL	368	OMAP_SYS_TIMER(3_secure)
	369	#endif
	370
	371	#ifdef CONFIG_ARCH_OMAP4
39e1d4c1	372	#ifdef CONFIG_LOCAL_TIMERS
a45c983f MZ	373	static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
	374	OMAP44XX_LOCAL_TWD_BASE,
	375	OMAP44XX_IRQ_LOCALTIMER);
39e1d4c1	376	#endif
a45c983f MZ	377
	378	static void __init omap4_timer_init(void)
	379	{
aa561889	380	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
1fe97c8f	381	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
a45c983f MZ	382	#ifdef CONFIG_LOCAL_TIMERS
	383	/* Local timers are not supprted on OMAP4430 ES1.0 */
	384	if (omap_rev() != OMAP4430_REV_ES1_0) {
	385	int err;
	386
	387	err = twd_local_timer_register(&twd_local_timer);
	388	if (err)
	389	pr_err("twd_local_timer_register failed %d\n", err);
	390	}
	391	#endif
1dbae815	392	}
e74984e4 TL	393	OMAP_SYS_TIMER(4)
e74984e4 TL	394	#endif
c345c8b0 TKD	395
	396	/**
	397	* omap2_dm_timer_set_src - change the timer input clock source
	398	* @pdev: timer platform device pointer
	399	* @source: array index of parent clock source
	400	*/
	401	static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
	402	{
	403	int ret;
	404	struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
	405	struct clk fclk, parent;
	406	char *parent_name = NULL;
	407
	408	fclk = clk_get(&pdev->dev, "fck");
	409	if (IS_ERR_OR_NULL(fclk)) {
	410	dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
	411	__func__, __LINE__);
	412	return -EINVAL;
	413	}
	414
	415	switch (source) {
	416	case OMAP_TIMER_SRC_SYS_CLK:
	417	parent_name = "sys_ck";
	418	break;
	419
	420	case OMAP_TIMER_SRC_32_KHZ:
	421	parent_name = "32k_ck";
	422	break;
	423
	424	case OMAP_TIMER_SRC_EXT_CLK:
	425	if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
	426	parent_name = "alt_ck";
	427	break;
	428	}
	429	dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
	430	__func__, __LINE__);
	431	clk_put(fclk);
	432	return -EINVAL;
	433	}
	434
	435	parent = clk_get(&pdev->dev, parent_name);
	436	if (IS_ERR_OR_NULL(parent)) {
	437	dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
	438	__func__, __LINE__, parent_name);
	439	clk_put(fclk);
	440	return -EINVAL;
	441	}
	442
	443	ret = clk_set_parent(fclk, parent);
	444	if (IS_ERR_VALUE(ret)) {
	445	dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
	446	__func__, parent_name);
	447	ret = -EINVAL;
	448	}
	449
	450	clk_put(parent);
	451	clk_put(fclk);
	452
	453	return ret;
	454	}
	455
c345c8b0 TKD	456	/**
	457	* omap_timer_init - build and register timer device with an
	458	* associated timer hwmod
	459	* @oh: timer hwmod pointer to be used to build timer device
	460	* @user: parameter that can be passed from calling hwmod API
	461	*
	462	* Called by omap_hwmod_for_each_by_class to register each of the timer
	463	* devices present in the system. The number of timer devices is known
	464	* by parsing through the hwmod database for a given class name. At the
	465	* end of function call memory is allocated for timer device and it is
	466	* registered to the framework ready to be proved by the driver.
	467	*/
	468	static int __init omap_timer_init(struct omap_hwmod oh, void unused)
	469	{
	470	int id;
	471	int ret = 0;
	472	char *name = "omap_timer";
	473	struct dmtimer_platform_data *pdata;
c541c15f	474	struct platform_device *pdev;
c345c8b0	475	struct omap_timer_capability_dev_attr *timer_dev_attr;
b481113a	476	struct powerdomain *pwrdm;
c345c8b0 TKD	477
	478	pr_debug("%s: %s\n", __func__, oh->name);
	479
	480	/* on secure device, do not register secure timer */
	481	timer_dev_attr = oh->dev_attr;
	482	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
	483	if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
	484	return ret;
	485
	486	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	487	if (!pdata) {
	488	pr_err("%s: No memory for [%s]\n", __func__, oh->name);
	489	return -ENOMEM;
	490	}
	491
	492	/*
	493	* Extract the IDs from name field in hwmod database
	494	* and use the same for constructing ids' for the
	495	* timer devices. In a way, we are avoiding usage of
	496	* static variable witin the function to do the same.
	497	* CAUTION: We have to be careful and make sure the
	498	* name in hwmod database does not change in which case
	499	* we might either make corresponding change here or
	500	* switch back static variable mechanism.
	501	*/
	502	sscanf(oh->name, "timer%2d", &id);
	503
	504	pdata->set_timer_src = omap2_dm_timer_set_src;
	505	pdata->timer_ip_version = oh->class->rev;
	506
0dad9fae TL	507	/* Mark clocksource and clockevent timers as reserved */
	508	if ((sys_timer_reserved >> (id - 1)) & 0x1)
	509	pdata->reserved = 1;
	510
b481113a TKD	511	pwrdm = omap_hwmod_get_pwrdm(oh);
	512	pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
	513	#ifdef CONFIG_PM
	514	pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	515	#endif
c541c15f	516	pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
c16ae1e6	517	NULL, 0, 0);
c345c8b0	518
c541c15f	519	if (IS_ERR(pdev)) {
c345c8b0 TKD	520	pr_err("%s: Can't build omap_device for %s: %s.\n",
	521	__func__, name, oh->name);
	522	ret = -EINVAL;
	523	}
	524
	525	kfree(pdata);
	526
	527	return ret;
	528	}
3392cdd3 TKD	529
	530	/**
	531	* omap2_dm_timer_init - top level regular device initialization
	532	*
	533	* Uses dedicated hwmod api to parse through hwmod database for
	534	* given class name and then build and register the timer device.
	535	*/
	536	static int __init omap2_dm_timer_init(void)
	537	{
	538	int ret;
	539
	540	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
	541	if (unlikely(ret)) {
	542	pr_err("%s: device registration failed.\n", __func__);
	543	return -EINVAL;
	544	}
	545
	546	return 0;
	547	}
	548	arch_initcall(omap2_dm_timer_init);
1fe97c8f VH	549
	550	/**
	551	* omap2_override_clocksource - clocksource override with user configuration
	552	*
	553	* Allows user to override default clocksource, using kernel parameter
	554	* clocksource="gp_timer" (For all OMAP2PLUS architectures)
	555	*
	556	* Note that, here we are using same standard kernel parameter "clocksource=",
	557	* and not introducing any OMAP specific interface.
	558	*/
	559	static int __init omap2_override_clocksource(char *str)
	560	{
	561	if (!str)
	562	return 0;
	563	/*
	564	* For OMAP architecture, we only have two options
	565	* - sync_32k (default)
	566	* - gp_timer (sys_clk based)
	567	*/
	568	if (!strcmp(str, "gp_timer"))
	569	use_gptimer_clksrc = true;
	570
	571	return 0;
	572	}
	573	early_param("clocksource", omap2_override_clocksource);