Commit | Line | Data |
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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
40fc3bb5 JH |
42 | #include <linux/platform_device.h> |
43 | #include <linux/platform_data/dmtimer-omap.h> | |
f8ce2547 | 44 | |
1dbae815 | 45 | #include <asm/mach/time.h> |
a45c983f | 46 | #include <asm/smp_twd.h> |
cbc94380 | 47 | #include <asm/sched_clock.h> |
7d7e1eba | 48 | |
3c7c5dab | 49 | #include <asm/arch_timer.h> |
2a296c8f | 50 | #include "omap_hwmod.h" |
25c7d49e | 51 | #include "omap_device.h" |
5c2e8852 | 52 | #include <plat/counter-32k.h> |
7d7e1eba | 53 | #include <plat/dmtimer.h> |
1d5aef49 | 54 | #include "omap-pm.h" |
b481113a | 55 | |
dbc04161 | 56 | #include "soc.h" |
7d7e1eba | 57 | #include "common.h" |
b481113a | 58 | #include "powerdomain.h" |
1dbae815 | 59 | |
fa6d79d2 SS |
60 | #define REALTIME_COUNTER_BASE 0x48243200 |
61 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
62 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
63 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
64 | ||
aa561889 TL |
65 | /* Clockevent code */ |
66 | ||
67 | static struct omap_dm_timer clkev; | |
5a3a388f | 68 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 69 | |
0cd61b68 | 70 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 71 | { |
5a3a388f KH |
72 | struct clock_event_device *evt = &clockevent_gpt; |
73 | ||
ee17f114 | 74 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 75 | |
5a3a388f | 76 | evt->event_handler(evt); |
1dbae815 TL |
77 | return IRQ_HANDLED; |
78 | } | |
79 | ||
80 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 81 | .name = "gp_timer", |
b30fabad | 82 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
83 | .handler = omap2_gp_timer_interrupt, |
84 | }; | |
85 | ||
5a3a388f KH |
86 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
87 | struct clock_event_device *evt) | |
1dbae815 | 88 | { |
ee17f114 | 89 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
971d0254 | 90 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
5a3a388f KH |
91 | |
92 | return 0; | |
93 | } | |
94 | ||
95 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
96 | struct clock_event_device *evt) | |
97 | { | |
98 | u32 period; | |
99 | ||
971d0254 | 100 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
5a3a388f KH |
101 | |
102 | switch (mode) { | |
103 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 104 | period = clkev.rate / HZ; |
5a3a388f | 105 | period -= 1; |
aa561889 | 106 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 107 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
971d0254 | 108 | 0xffffffff - period, OMAP_TIMER_POSTED); |
ee17f114 | 109 | __omap_dm_timer_load_start(&clkev, |
aa561889 | 110 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
971d0254 | 111 | 0xffffffff - period, OMAP_TIMER_POSTED); |
5a3a388f KH |
112 | break; |
113 | case CLOCK_EVT_MODE_ONESHOT: | |
114 | break; | |
115 | case CLOCK_EVT_MODE_UNUSED: | |
116 | case CLOCK_EVT_MODE_SHUTDOWN: | |
117 | case CLOCK_EVT_MODE_RESUME: | |
118 | break; | |
119 | } | |
120 | } | |
121 | ||
122 | static struct clock_event_device clockevent_gpt = { | |
5a3a388f KH |
123 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
124 | .shift = 32, | |
11d6ec2e | 125 | .rating = 300, |
5a3a388f KH |
126 | .set_next_event = omap2_gp_timer_set_next_event, |
127 | .set_mode = omap2_gp_timer_set_mode, | |
128 | }; | |
129 | ||
ad24bde8 JH |
130 | static struct property device_disabled = { |
131 | .name = "status", | |
132 | .length = sizeof("disabled"), | |
133 | .value = "disabled", | |
134 | }; | |
135 | ||
136 | static struct of_device_id omap_timer_match[] __initdata = { | |
137 | { .compatible = "ti,omap2-timer", }, | |
138 | { } | |
139 | }; | |
140 | ||
9725f445 JH |
141 | /** |
142 | * omap_get_timer_dt - get a timer using device-tree | |
143 | * @match - device-tree match structure for matching a device type | |
144 | * @property - optional timer property to match | |
145 | * | |
146 | * Helper function to get a timer during early boot using device-tree for use | |
147 | * as kernel system timer. Optionally, the property argument can be used to | |
148 | * select a timer with a specific property. Once a timer is found then mark | |
149 | * the timer node in device-tree as disabled, to prevent the kernel from | |
150 | * registering this timer as a platform device and so no one else can use it. | |
151 | */ | |
152 | static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, | |
153 | const char *property) | |
154 | { | |
155 | struct device_node *np; | |
156 | ||
157 | for_each_matching_node(np, match) { | |
034bf091 | 158 | if (!of_device_is_available(np)) |
9725f445 | 159 | continue; |
9725f445 | 160 | |
034bf091 | 161 | if (property && !of_get_property(np, property, NULL)) |
9725f445 | 162 | continue; |
9725f445 | 163 | |
2eb03937 JH |
164 | if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || |
165 | of_get_property(np, "ti,timer-dsp", NULL) || | |
166 | of_get_property(np, "ti,timer-pwm", NULL) || | |
167 | of_get_property(np, "ti,timer-secure", NULL))) | |
168 | continue; | |
169 | ||
2727da85 | 170 | of_add_property(np, &device_disabled); |
9725f445 JH |
171 | return np; |
172 | } | |
173 | ||
174 | return NULL; | |
175 | } | |
176 | ||
ad24bde8 JH |
177 | /** |
178 | * omap_dmtimer_init - initialisation function when device tree is used | |
179 | * | |
180 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
181 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
182 | * kernel registering these devices remove them dynamically from the device | |
183 | * tree on boot. | |
184 | */ | |
bf85f205 | 185 | static void __init omap_dmtimer_init(void) |
ad24bde8 JH |
186 | { |
187 | struct device_node *np; | |
188 | ||
189 | if (!cpu_is_omap34xx()) | |
190 | return; | |
191 | ||
192 | /* If we are a secure device, remove any secure timer nodes */ | |
193 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 JH |
194 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
195 | if (np) | |
196 | of_node_put(np); | |
ad24bde8 JH |
197 | } |
198 | } | |
199 | ||
bfd6d021 JH |
200 | /** |
201 | * omap_dm_timer_get_errata - get errata flags for a timer | |
202 | * | |
203 | * Get the timer errata flags that are specific to the OMAP device being used. | |
204 | */ | |
bf85f205 | 205 | static u32 __init omap_dm_timer_get_errata(void) |
bfd6d021 JH |
206 | { |
207 | if (cpu_is_omap24xx()) | |
208 | return 0; | |
209 | ||
210 | return OMAP_TIMER_ERRATA_I103_I767; | |
211 | } | |
212 | ||
aa561889 | 213 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
e95ea43a JH |
214 | int gptimer_id, |
215 | const char *fck_source, | |
216 | const char *property, | |
217 | const char **timer_name, | |
218 | int posted) | |
5a3a388f | 219 | { |
aa561889 | 220 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
9725f445 JH |
221 | const char *oh_name; |
222 | struct device_node *np; | |
aa561889 | 223 | struct omap_hwmod *oh; |
61b001c5 | 224 | struct resource irq, mem; |
a7990a19 | 225 | struct clk *src; |
f88095ba | 226 | int r = 0; |
aa561889 | 227 | |
9725f445 JH |
228 | if (of_have_populated_dt()) { |
229 | np = omap_get_timer_dt(omap_timer_match, NULL); | |
230 | if (!np) | |
231 | return -ENODEV; | |
232 | ||
233 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
234 | if (!oh_name) | |
235 | return -ENODEV; | |
236 | ||
237 | timer->irq = irq_of_parse_and_map(np, 0); | |
238 | if (!timer->irq) | |
239 | return -ENXIO; | |
240 | ||
241 | timer->io_base = of_iomap(np, 0); | |
242 | ||
243 | of_node_put(np); | |
244 | } else { | |
245 | if (omap_dm_timer_reserve_systimer(gptimer_id)) | |
246 | return -ENODEV; | |
247 | ||
248 | sprintf(name, "timer%d", gptimer_id); | |
249 | oh_name = name; | |
250 | } | |
251 | ||
9725f445 | 252 | oh = omap_hwmod_lookup(oh_name); |
aa561889 TL |
253 | if (!oh) |
254 | return -ENODEV; | |
255 | ||
e95ea43a JH |
256 | *timer_name = oh->name; |
257 | ||
9725f445 JH |
258 | if (!of_have_populated_dt()) { |
259 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | |
61b001c5 | 260 | &irq); |
9725f445 JH |
261 | if (r) |
262 | return -ENXIO; | |
61b001c5 | 263 | timer->irq = irq.start; |
9725f445 JH |
264 | |
265 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, | |
61b001c5 | 266 | &mem); |
9725f445 JH |
267 | if (r) |
268 | return -ENXIO; | |
9725f445 JH |
269 | |
270 | /* Static mapping, never released */ | |
61b001c5 | 271 | timer->io_base = ioremap(mem.start, mem.end - mem.start); |
9725f445 | 272 | } |
aa561889 | 273 | |
aa561889 TL |
274 | if (!timer->io_base) |
275 | return -ENXIO; | |
276 | ||
277 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 278 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 | 279 | if (IS_ERR(timer->fclk)) |
a7990a19 JH |
280 | return PTR_ERR(timer->fclk); |
281 | ||
282 | src = clk_get(NULL, fck_source); | |
283 | if (IS_ERR(src)) | |
284 | return PTR_ERR(src); | |
aa561889 | 285 | |
a7990a19 JH |
286 | if (clk_get_parent(timer->fclk) != src) { |
287 | r = clk_set_parent(timer->fclk, src); | |
288 | if (r < 0) { | |
289 | pr_warn("%s: %s cannot set source\n", __func__, | |
290 | oh->name); | |
aa561889 | 291 | clk_put(src); |
a7990a19 | 292 | return r; |
aa561889 TL |
293 | } |
294 | } | |
b1538832 | 295 | |
a7990a19 JH |
296 | clk_put(src); |
297 | ||
b1538832 JH |
298 | omap_hwmod_setup_one(oh_name); |
299 | omap_hwmod_enable(oh); | |
ee17f114 | 300 | __omap_dm_timer_init_regs(timer); |
aa561889 | 301 | |
bfd6d021 JH |
302 | if (posted) |
303 | __omap_dm_timer_enable_posted(timer); | |
304 | ||
305 | /* Check that the intended posted configuration matches the actual */ | |
306 | if (posted != timer->posted) | |
307 | return -EINVAL; | |
1dbae815 | 308 | |
bfd6d021 | 309 | timer->rate = clk_get_rate(timer->fclk); |
aa561889 | 310 | timer->reserved = 1; |
38698bef | 311 | |
f88095ba | 312 | return r; |
aa561889 | 313 | } |
f248076c | 314 | |
aa561889 | 315 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
316 | const char *fck_source, |
317 | const char *property) | |
aa561889 TL |
318 | { |
319 | int res; | |
f248076c | 320 | |
bfd6d021 JH |
321 | clkev.errata = omap_dm_timer_get_errata(); |
322 | ||
323 | /* | |
324 | * For clock-event timers we never read the timer counter and | |
325 | * so we are not impacted by errata i103 and i767. Therefore, | |
326 | * we can safely ignore this errata for clock-event timers. | |
327 | */ | |
328 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | |
329 | ||
330 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, | |
e95ea43a | 331 | &clockevent_gpt.name, OMAP_TIMER_POSTED); |
aa561889 | 332 | BUG_ON(res); |
f248076c | 333 | |
a032d33b | 334 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 335 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 336 | |
ee17f114 | 337 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 TL |
338 | |
339 | clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, | |
5a3a388f KH |
340 | clockevent_gpt.shift); |
341 | clockevent_gpt.max_delta_ns = | |
342 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | |
343 | clockevent_gpt.min_delta_ns = | |
df88acbb AK |
344 | clockevent_delta2ns(3, &clockevent_gpt); |
345 | /* Timer internal resynch latency. */ | |
5a3a388f | 346 | |
11d6ec2e SS |
347 | clockevent_gpt.cpumask = cpu_possible_mask; |
348 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
5a3a388f | 349 | clockevents_register_device(&clockevent_gpt); |
aa561889 | 350 | |
e95ea43a JH |
351 | pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, |
352 | clkev.rate); | |
5a3a388f KH |
353 | } |
354 | ||
f248076c | 355 | /* Clocksource code */ |
3d05a3e8 | 356 | static struct omap_dm_timer clksrc; |
1fe97c8f | 357 | static bool use_gptimer_clksrc; |
3d05a3e8 | 358 | |
5a3a388f KH |
359 | /* |
360 | * clocksource | |
361 | */ | |
8e19608e | 362 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 363 | { |
971d0254 | 364 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 365 | OMAP_TIMER_NONPOSTED); |
5a3a388f KH |
366 | } |
367 | ||
368 | static struct clocksource clocksource_gpt = { | |
5a3a388f KH |
369 | .rating = 300, |
370 | .read = clocksource_read_cycles, | |
371 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
372 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
373 | }; | |
374 | ||
2f0778af | 375 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 376 | { |
3d05a3e8 | 377 | if (clksrc.reserved) |
971d0254 | 378 | return __omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 379 | OMAP_TIMER_NONPOSTED); |
5a3a388f | 380 | |
2f0778af | 381 | return 0; |
3d05a3e8 TL |
382 | } |
383 | ||
258e84af JH |
384 | static struct of_device_id omap_counter_match[] __initdata = { |
385 | { .compatible = "ti,omap-counter32k", }, | |
386 | { } | |
387 | }; | |
388 | ||
3d05a3e8 | 389 | /* Setup free-running counter for clocksource */ |
e0c3e27c | 390 | static int __init __maybe_unused omap2_sync32k_clocksource_init(void) |
1fe97c8f VH |
391 | { |
392 | int ret; | |
9883f7c8 | 393 | struct device_node *np = NULL; |
1fe97c8f VH |
394 | struct omap_hwmod *oh; |
395 | void __iomem *vbase; | |
396 | const char *oh_name = "counter_32k"; | |
397 | ||
9883f7c8 JH |
398 | /* |
399 | * If device-tree is present, then search the DT blob | |
400 | * to see if the 32kHz counter is supported. | |
401 | */ | |
402 | if (of_have_populated_dt()) { | |
403 | np = omap_get_timer_dt(omap_counter_match, NULL); | |
404 | if (!np) | |
405 | return -ENODEV; | |
406 | ||
407 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
408 | if (!oh_name) | |
409 | return -ENODEV; | |
410 | } | |
411 | ||
1fe97c8f VH |
412 | /* |
413 | * First check hwmod data is available for sync32k counter | |
414 | */ | |
415 | oh = omap_hwmod_lookup(oh_name); | |
416 | if (!oh || oh->slaves_cnt == 0) | |
417 | return -ENODEV; | |
418 | ||
419 | omap_hwmod_setup_one(oh_name); | |
420 | ||
9883f7c8 JH |
421 | if (np) { |
422 | vbase = of_iomap(np, 0); | |
423 | of_node_put(np); | |
424 | } else { | |
425 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
426 | } | |
427 | ||
1fe97c8f VH |
428 | if (!vbase) { |
429 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
430 | return -ENXIO; | |
431 | } | |
432 | ||
433 | ret = omap_hwmod_enable(oh); | |
434 | if (ret) { | |
435 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
436 | __func__, ret); | |
437 | return ret; | |
438 | } | |
439 | ||
440 | ret = omap_init_clocksource_32k(vbase); | |
441 | if (ret) { | |
442 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
443 | __func__, ret); | |
444 | omap_hwmod_idle(oh); | |
445 | } | |
446 | ||
447 | return ret; | |
448 | } | |
449 | ||
450 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
2eb03937 JH |
451 | const char *fck_source, |
452 | const char *property) | |
3d05a3e8 TL |
453 | { |
454 | int res; | |
455 | ||
bfd6d021 JH |
456 | clksrc.errata = omap_dm_timer_get_errata(); |
457 | ||
2eb03937 | 458 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, property, |
e95ea43a | 459 | &clocksource_gpt.name, |
bfd6d021 | 460 | OMAP_TIMER_NONPOSTED); |
3d05a3e8 | 461 | BUG_ON(res); |
5a3a388f | 462 | |
ee17f114 | 463 | __omap_dm_timer_load_start(&clksrc, |
971d0254 | 464 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
bfd6d021 | 465 | OMAP_TIMER_NONPOSTED); |
2f0778af | 466 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 467 | |
3d05a3e8 TL |
468 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
469 | pr_err("Could not register clocksource %s\n", | |
470 | clocksource_gpt.name); | |
1fe97c8f | 471 | else |
e95ea43a JH |
472 | pr_info("OMAP clocksource: %s at %lu Hz\n", |
473 | clocksource_gpt.name, clksrc.rate); | |
1fe97c8f VH |
474 | } |
475 | ||
fa6d79d2 SS |
476 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
477 | /* | |
478 | * The realtime counter also called master counter, is a free-running | |
479 | * counter, which is related to real time. It produces the count used | |
480 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
481 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
482 | * in different power modes, the master counter shifts operation between | |
483 | * clocks, adjusting the increment per clock in hardware accordingly to | |
484 | * maintain a constant count rate. | |
485 | */ | |
486 | static void __init realtime_counter_init(void) | |
487 | { | |
488 | void __iomem *base; | |
489 | static struct clk *sys_clk; | |
490 | unsigned long rate; | |
491 | unsigned int reg, num, den; | |
492 | ||
493 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
494 | if (!base) { | |
495 | pr_err("%s: ioremap failed\n", __func__); | |
496 | return; | |
497 | } | |
498 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | |
533b2981 | 499 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
500 | pr_err("%s: failed to get system clock handle\n", __func__); |
501 | iounmap(base); | |
502 | return; | |
503 | } | |
504 | ||
505 | rate = clk_get_rate(sys_clk); | |
506 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
507 | switch (rate) { | |
508 | case 1200000: | |
509 | num = 64; | |
510 | den = 125; | |
511 | break; | |
512 | case 1300000: | |
513 | num = 768; | |
514 | den = 1625; | |
515 | break; | |
516 | case 19200000: | |
517 | num = 8; | |
518 | den = 25; | |
519 | break; | |
520 | case 2600000: | |
521 | num = 384; | |
522 | den = 1625; | |
523 | break; | |
524 | case 2700000: | |
525 | num = 256; | |
526 | den = 1125; | |
527 | break; | |
528 | case 38400000: | |
529 | default: | |
530 | /* Program it for 38.4 MHz */ | |
531 | num = 4; | |
532 | den = 25; | |
533 | break; | |
534 | } | |
535 | ||
536 | /* Program numerator and denumerator registers */ | |
537 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
538 | NUMERATOR_DENUMERATOR_MASK; | |
539 | reg |= num; | |
540 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
541 | ||
542 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
543 | NUMERATOR_DENUMERATOR_MASK; | |
544 | reg |= den; | |
545 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
546 | ||
547 | iounmap(base); | |
548 | } | |
549 | #else | |
550 | static inline void __init realtime_counter_init(void) | |
551 | {} | |
552 | #endif | |
553 | ||
6f80b3bb | 554 | #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
2eb03937 | 555 | clksrc_nr, clksrc_src, clksrc_prop) \ |
6bb27d73 | 556 | void __init omap##name##_gptimer_timer_init(void) \ |
6f80b3bb IG |
557 | { \ |
558 | omap_dmtimer_init(); \ | |
559 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ | |
2eb03937 JH |
560 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ |
561 | clksrc_prop); \ | |
6f80b3bb IG |
562 | } |
563 | ||
564 | #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ | |
2eb03937 | 565 | clksrc_nr, clksrc_src, clksrc_prop) \ |
6bb27d73 | 566 | void __init omap##name##_sync32k_timer_init(void) \ |
e74984e4 | 567 | { \ |
ad24bde8 | 568 | omap_dmtimer_init(); \ |
9725f445 | 569 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
6f80b3bb IG |
570 | /* Enable the use of clocksource="gp_timer" kernel parameter */ \ |
571 | if (use_gptimer_clksrc) \ | |
2eb03937 JH |
572 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ |
573 | clksrc_prop); \ | |
6f80b3bb IG |
574 | else \ |
575 | omap2_sync32k_clocksource_init(); \ | |
e74984e4 TL |
576 | } |
577 | ||
e74984e4 | 578 | #ifdef CONFIG_ARCH_OMAP2 |
7bdc83f7 | 579 | OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", |
2eb03937 | 580 | 2, "timer_sys_ck", NULL); |
6f80b3bb | 581 | #endif /* CONFIG_ARCH_OMAP2 */ |
e74984e4 TL |
582 | |
583 | #ifdef CONFIG_ARCH_OMAP3 | |
7bdc83f7 | 584 | OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", |
2eb03937 | 585 | 2, "timer_sys_ck", NULL); |
7bdc83f7 | 586 | OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", |
2eb03937 | 587 | 2, "timer_sys_ck", NULL); |
6f80b3bb | 588 | #endif /* CONFIG_ARCH_OMAP3 */ |
e74984e4 | 589 | |
00ea4d56 | 590 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
2eb03937 JH |
591 | OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, |
592 | 1, "timer_sys_ck", "ti,timer-alwon"); | |
00ea4d56 | 593 | #endif |
08f30989 | 594 | |
00ea4d56 | 595 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) |
7bdc83f7 | 596 | OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", |
2eb03937 | 597 | 2, "sys_clkin_ck", NULL); |
00ea4d56 JH |
598 | #endif |
599 | ||
600 | #ifdef CONFIG_ARCH_OMAP4 | |
39e1d4c1 | 601 | #ifdef CONFIG_LOCAL_TIMERS |
6f80b3bb | 602 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); |
6bb27d73 | 603 | void __init omap4_local_timer_init(void) |
a45c983f | 604 | { |
6f80b3bb | 605 | omap4_sync32k_timer_init(); |
a45c983f MZ |
606 | /* Local timers are not supprted on OMAP4430 ES1.0 */ |
607 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
608 | int err; | |
609 | ||
eed0de27 SS |
610 | if (of_have_populated_dt()) { |
611 | twd_local_timer_of_register(); | |
612 | return; | |
613 | } | |
614 | ||
a45c983f MZ |
615 | err = twd_local_timer_register(&twd_local_timer); |
616 | if (err) | |
617 | pr_err("twd_local_timer_register failed %d\n", err); | |
618 | } | |
1dbae815 | 619 | } |
6f80b3bb | 620 | #else /* CONFIG_LOCAL_TIMERS */ |
6bb27d73 | 621 | void __init omap4_local_timer_init(void) |
6f80b3bb | 622 | { |
73f14f6d | 623 | omap4_sync32k_timer_init(); |
6f80b3bb IG |
624 | } |
625 | #endif /* CONFIG_LOCAL_TIMERS */ | |
6f80b3bb | 626 | #endif /* CONFIG_ARCH_OMAP4 */ |
c345c8b0 | 627 | |
37b3280d | 628 | #ifdef CONFIG_SOC_OMAP5 |
6bb27d73 | 629 | void __init omap5_realtime_timer_init(void) |
fa6d79d2 | 630 | { |
3c7c5dab SS |
631 | int err; |
632 | ||
00ea4d56 | 633 | omap4_sync32k_timer_init(); |
fa6d79d2 | 634 | realtime_counter_init(); |
3c7c5dab SS |
635 | |
636 | err = arch_timer_of_register(); | |
637 | if (err) | |
638 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | |
fa6d79d2 | 639 | } |
6f80b3bb | 640 | #endif /* CONFIG_SOC_OMAP5 */ |
37b3280d | 641 | |
c345c8b0 TKD |
642 | /** |
643 | * omap_timer_init - build and register timer device with an | |
644 | * associated timer hwmod | |
645 | * @oh: timer hwmod pointer to be used to build timer device | |
646 | * @user: parameter that can be passed from calling hwmod API | |
647 | * | |
648 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
649 | * devices present in the system. The number of timer devices is known | |
650 | * by parsing through the hwmod database for a given class name. At the | |
651 | * end of function call memory is allocated for timer device and it is | |
652 | * registered to the framework ready to be proved by the driver. | |
653 | */ | |
654 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
655 | { | |
656 | int id; | |
657 | int ret = 0; | |
658 | char *name = "omap_timer"; | |
659 | struct dmtimer_platform_data *pdata; | |
c541c15f | 660 | struct platform_device *pdev; |
c345c8b0 TKD |
661 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
662 | ||
663 | pr_debug("%s: %s\n", __func__, oh->name); | |
664 | ||
665 | /* on secure device, do not register secure timer */ | |
666 | timer_dev_attr = oh->dev_attr; | |
667 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
668 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
669 | return ret; | |
670 | ||
671 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
672 | if (!pdata) { | |
673 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
674 | return -ENOMEM; | |
675 | } | |
676 | ||
677 | /* | |
678 | * Extract the IDs from name field in hwmod database | |
679 | * and use the same for constructing ids' for the | |
680 | * timer devices. In a way, we are avoiding usage of | |
681 | * static variable witin the function to do the same. | |
682 | * CAUTION: We have to be careful and make sure the | |
683 | * name in hwmod database does not change in which case | |
684 | * we might either make corresponding change here or | |
685 | * switch back static variable mechanism. | |
686 | */ | |
687 | sscanf(oh->name, "timer%2d", &id); | |
688 | ||
d1c1691b JH |
689 | if (timer_dev_attr) |
690 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 691 | |
bfd6d021 | 692 | pdata->timer_errata = omap_dm_timer_get_errata(); |
6e740f9a TL |
693 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; |
694 | ||
c541c15f | 695 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), |
c16ae1e6 | 696 | NULL, 0, 0); |
c345c8b0 | 697 | |
c541c15f | 698 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
699 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
700 | __func__, name, oh->name); | |
701 | ret = -EINVAL; | |
702 | } | |
703 | ||
704 | kfree(pdata); | |
705 | ||
706 | return ret; | |
707 | } | |
3392cdd3 TKD |
708 | |
709 | /** | |
710 | * omap2_dm_timer_init - top level regular device initialization | |
711 | * | |
712 | * Uses dedicated hwmod api to parse through hwmod database for | |
713 | * given class name and then build and register the timer device. | |
714 | */ | |
715 | static int __init omap2_dm_timer_init(void) | |
716 | { | |
717 | int ret; | |
718 | ||
9725f445 JH |
719 | /* If dtb is there, the devices will be created dynamically */ |
720 | if (of_have_populated_dt()) | |
721 | return -ENODEV; | |
722 | ||
3392cdd3 TKD |
723 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); |
724 | if (unlikely(ret)) { | |
725 | pr_err("%s: device registration failed.\n", __func__); | |
726 | return -EINVAL; | |
727 | } | |
728 | ||
729 | return 0; | |
730 | } | |
731 | arch_initcall(omap2_dm_timer_init); | |
1fe97c8f VH |
732 | |
733 | /** | |
734 | * omap2_override_clocksource - clocksource override with user configuration | |
735 | * | |
736 | * Allows user to override default clocksource, using kernel parameter | |
737 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
738 | * | |
739 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
740 | * and not introducing any OMAP specific interface. | |
741 | */ | |
742 | static int __init omap2_override_clocksource(char *str) | |
743 | { | |
744 | if (!str) | |
745 | return 0; | |
746 | /* | |
747 | * For OMAP architecture, we only have two options | |
748 | * - sync_32k (default) | |
749 | * - gp_timer (sys_clk based) | |
750 | */ | |
751 | if (!strcmp(str, "gp_timer")) | |
752 | use_gptimer_clksrc = true; | |
753 | ||
754 | return 0; | |
755 | } | |
756 | early_param("clocksource", omap2_override_clocksource); |