Commit | Line | Data |
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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
40fc3bb5 JH |
42 | #include <linux/platform_device.h> |
43 | #include <linux/platform_data/dmtimer-omap.h> | |
38ff87f7 | 44 | #include <linux/sched_clock.h> |
f8ce2547 | 45 | |
1dbae815 | 46 | #include <asm/mach/time.h> |
a45c983f | 47 | #include <asm/smp_twd.h> |
7d7e1eba | 48 | |
2a296c8f | 49 | #include "omap_hwmod.h" |
25c7d49e | 50 | #include "omap_device.h" |
5c2e8852 | 51 | #include <plat/counter-32k.h> |
7d7e1eba | 52 | #include <plat/dmtimer.h> |
1d5aef49 | 53 | #include "omap-pm.h" |
b481113a | 54 | |
dbc04161 | 55 | #include "soc.h" |
7d7e1eba | 56 | #include "common.h" |
b481113a | 57 | #include "powerdomain.h" |
5523e409 | 58 | #include "omap-secure.h" |
1dbae815 | 59 | |
fa6d79d2 SS |
60 | #define REALTIME_COUNTER_BASE 0x48243200 |
61 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
62 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
63 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
64 | ||
aa561889 TL |
65 | /* Clockevent code */ |
66 | ||
67 | static struct omap_dm_timer clkev; | |
5a3a388f | 68 | static struct clock_event_device clockevent_gpt; |
5523e409 S |
69 | static unsigned long arch_timer_freq; |
70 | ||
71 | void set_cntfreq(void) | |
72 | { | |
73 | omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); | |
74 | } | |
1dbae815 | 75 | |
0cd61b68 | 76 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 77 | { |
5a3a388f KH |
78 | struct clock_event_device *evt = &clockevent_gpt; |
79 | ||
ee17f114 | 80 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 81 | |
5a3a388f | 82 | evt->event_handler(evt); |
1dbae815 TL |
83 | return IRQ_HANDLED; |
84 | } | |
85 | ||
86 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 87 | .name = "gp_timer", |
b30fabad | 88 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
89 | .handler = omap2_gp_timer_interrupt, |
90 | }; | |
91 | ||
5a3a388f KH |
92 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
93 | struct clock_event_device *evt) | |
1dbae815 | 94 | { |
ee17f114 | 95 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
971d0254 | 96 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
5a3a388f KH |
97 | |
98 | return 0; | |
99 | } | |
100 | ||
101 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
102 | struct clock_event_device *evt) | |
103 | { | |
104 | u32 period; | |
105 | ||
971d0254 | 106 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
5a3a388f KH |
107 | |
108 | switch (mode) { | |
109 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 110 | period = clkev.rate / HZ; |
5a3a388f | 111 | period -= 1; |
aa561889 | 112 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 113 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
971d0254 | 114 | 0xffffffff - period, OMAP_TIMER_POSTED); |
ee17f114 | 115 | __omap_dm_timer_load_start(&clkev, |
aa561889 | 116 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
971d0254 | 117 | 0xffffffff - period, OMAP_TIMER_POSTED); |
5a3a388f KH |
118 | break; |
119 | case CLOCK_EVT_MODE_ONESHOT: | |
120 | break; | |
121 | case CLOCK_EVT_MODE_UNUSED: | |
122 | case CLOCK_EVT_MODE_SHUTDOWN: | |
123 | case CLOCK_EVT_MODE_RESUME: | |
124 | break; | |
125 | } | |
126 | } | |
127 | ||
128 | static struct clock_event_device clockevent_gpt = { | |
5a3a388f | 129 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
11d6ec2e | 130 | .rating = 300, |
5a3a388f KH |
131 | .set_next_event = omap2_gp_timer_set_next_event, |
132 | .set_mode = omap2_gp_timer_set_mode, | |
133 | }; | |
134 | ||
ad24bde8 JH |
135 | static struct property device_disabled = { |
136 | .name = "status", | |
137 | .length = sizeof("disabled"), | |
138 | .value = "disabled", | |
139 | }; | |
140 | ||
141 | static struct of_device_id omap_timer_match[] __initdata = { | |
002e1ec5 JH |
142 | { .compatible = "ti,omap2420-timer", }, |
143 | { .compatible = "ti,omap3430-timer", }, | |
144 | { .compatible = "ti,omap4430-timer", }, | |
145 | { .compatible = "ti,omap5430-timer", }, | |
146 | { .compatible = "ti,am335x-timer", }, | |
147 | { .compatible = "ti,am335x-timer-1ms", }, | |
ad24bde8 JH |
148 | { } |
149 | }; | |
150 | ||
9725f445 JH |
151 | /** |
152 | * omap_get_timer_dt - get a timer using device-tree | |
153 | * @match - device-tree match structure for matching a device type | |
154 | * @property - optional timer property to match | |
155 | * | |
156 | * Helper function to get a timer during early boot using device-tree for use | |
157 | * as kernel system timer. Optionally, the property argument can be used to | |
158 | * select a timer with a specific property. Once a timer is found then mark | |
159 | * the timer node in device-tree as disabled, to prevent the kernel from | |
160 | * registering this timer as a platform device and so no one else can use it. | |
161 | */ | |
162 | static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, | |
163 | const char *property) | |
164 | { | |
165 | struct device_node *np; | |
166 | ||
167 | for_each_matching_node(np, match) { | |
034bf091 | 168 | if (!of_device_is_available(np)) |
9725f445 | 169 | continue; |
9725f445 | 170 | |
034bf091 | 171 | if (property && !of_get_property(np, property, NULL)) |
9725f445 | 172 | continue; |
9725f445 | 173 | |
2eb03937 JH |
174 | if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || |
175 | of_get_property(np, "ti,timer-dsp", NULL) || | |
176 | of_get_property(np, "ti,timer-pwm", NULL) || | |
177 | of_get_property(np, "ti,timer-secure", NULL))) | |
178 | continue; | |
179 | ||
2727da85 | 180 | of_add_property(np, &device_disabled); |
9725f445 JH |
181 | return np; |
182 | } | |
183 | ||
184 | return NULL; | |
185 | } | |
186 | ||
ad24bde8 JH |
187 | /** |
188 | * omap_dmtimer_init - initialisation function when device tree is used | |
189 | * | |
190 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
191 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
192 | * kernel registering these devices remove them dynamically from the device | |
193 | * tree on boot. | |
194 | */ | |
bf85f205 | 195 | static void __init omap_dmtimer_init(void) |
ad24bde8 JH |
196 | { |
197 | struct device_node *np; | |
198 | ||
199 | if (!cpu_is_omap34xx()) | |
200 | return; | |
201 | ||
202 | /* If we are a secure device, remove any secure timer nodes */ | |
203 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 JH |
204 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
205 | if (np) | |
206 | of_node_put(np); | |
ad24bde8 JH |
207 | } |
208 | } | |
209 | ||
bfd6d021 JH |
210 | /** |
211 | * omap_dm_timer_get_errata - get errata flags for a timer | |
212 | * | |
213 | * Get the timer errata flags that are specific to the OMAP device being used. | |
214 | */ | |
bf85f205 | 215 | static u32 __init omap_dm_timer_get_errata(void) |
bfd6d021 JH |
216 | { |
217 | if (cpu_is_omap24xx()) | |
218 | return 0; | |
219 | ||
220 | return OMAP_TIMER_ERRATA_I103_I767; | |
221 | } | |
222 | ||
aa561889 | 223 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
e95ea43a JH |
224 | const char *fck_source, |
225 | const char *property, | |
226 | const char **timer_name, | |
227 | int posted) | |
5a3a388f | 228 | { |
aa561889 | 229 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
37bd6ca8 | 230 | const char *oh_name = NULL; |
9725f445 | 231 | struct device_node *np; |
aa561889 | 232 | struct omap_hwmod *oh; |
61b001c5 | 233 | struct resource irq, mem; |
a7990a19 | 234 | struct clk *src; |
f88095ba | 235 | int r = 0; |
aa561889 | 236 | |
9725f445 | 237 | if (of_have_populated_dt()) { |
61338d59 | 238 | np = omap_get_timer_dt(omap_timer_match, property); |
9725f445 JH |
239 | if (!np) |
240 | return -ENODEV; | |
241 | ||
242 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
243 | if (!oh_name) | |
244 | return -ENODEV; | |
245 | ||
246 | timer->irq = irq_of_parse_and_map(np, 0); | |
247 | if (!timer->irq) | |
248 | return -ENXIO; | |
249 | ||
250 | timer->io_base = of_iomap(np, 0); | |
251 | ||
252 | of_node_put(np); | |
253 | } else { | |
8f6924dc | 254 | if (omap_dm_timer_reserve_systimer(timer->id)) |
9725f445 JH |
255 | return -ENODEV; |
256 | ||
8f6924dc | 257 | sprintf(name, "timer%d", timer->id); |
9725f445 JH |
258 | oh_name = name; |
259 | } | |
260 | ||
9725f445 | 261 | oh = omap_hwmod_lookup(oh_name); |
aa561889 TL |
262 | if (!oh) |
263 | return -ENODEV; | |
264 | ||
e95ea43a JH |
265 | *timer_name = oh->name; |
266 | ||
9725f445 JH |
267 | if (!of_have_populated_dt()) { |
268 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | |
61b001c5 | 269 | &irq); |
9725f445 JH |
270 | if (r) |
271 | return -ENXIO; | |
61b001c5 | 272 | timer->irq = irq.start; |
9725f445 JH |
273 | |
274 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, | |
61b001c5 | 275 | &mem); |
9725f445 JH |
276 | if (r) |
277 | return -ENXIO; | |
9725f445 JH |
278 | |
279 | /* Static mapping, never released */ | |
61b001c5 | 280 | timer->io_base = ioremap(mem.start, mem.end - mem.start); |
9725f445 | 281 | } |
aa561889 | 282 | |
aa561889 TL |
283 | if (!timer->io_base) |
284 | return -ENXIO; | |
285 | ||
286 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 287 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 | 288 | if (IS_ERR(timer->fclk)) |
a7990a19 | 289 | return PTR_ERR(timer->fclk); |
aa561889 | 290 | |
a7990a19 JH |
291 | src = clk_get(NULL, fck_source); |
292 | if (IS_ERR(src)) | |
293 | return PTR_ERR(src); | |
aa561889 | 294 | |
a7990a19 JH |
295 | if (clk_get_parent(timer->fclk) != src) { |
296 | r = clk_set_parent(timer->fclk, src); | |
297 | if (r < 0) { | |
298 | pr_warn("%s: %s cannot set source\n", __func__, | |
299 | oh->name); | |
aa561889 | 300 | clk_put(src); |
a7990a19 | 301 | return r; |
aa561889 TL |
302 | } |
303 | } | |
b1538832 | 304 | |
a7990a19 JH |
305 | clk_put(src); |
306 | ||
b1538832 JH |
307 | omap_hwmod_setup_one(oh_name); |
308 | omap_hwmod_enable(oh); | |
ee17f114 | 309 | __omap_dm_timer_init_regs(timer); |
aa561889 | 310 | |
bfd6d021 JH |
311 | if (posted) |
312 | __omap_dm_timer_enable_posted(timer); | |
313 | ||
314 | /* Check that the intended posted configuration matches the actual */ | |
315 | if (posted != timer->posted) | |
316 | return -EINVAL; | |
1dbae815 | 317 | |
bfd6d021 | 318 | timer->rate = clk_get_rate(timer->fclk); |
aa561889 | 319 | timer->reserved = 1; |
38698bef | 320 | |
f88095ba | 321 | return r; |
aa561889 | 322 | } |
f248076c | 323 | |
aa561889 | 324 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
325 | const char *fck_source, |
326 | const char *property) | |
aa561889 TL |
327 | { |
328 | int res; | |
f248076c | 329 | |
8f6924dc | 330 | clkev.id = gptimer_id; |
bfd6d021 JH |
331 | clkev.errata = omap_dm_timer_get_errata(); |
332 | ||
333 | /* | |
334 | * For clock-event timers we never read the timer counter and | |
335 | * so we are not impacted by errata i103 and i767. Therefore, | |
336 | * we can safely ignore this errata for clock-event timers. | |
337 | */ | |
338 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | |
339 | ||
8f6924dc | 340 | res = omap_dm_timer_init_one(&clkev, fck_source, property, |
e95ea43a | 341 | &clockevent_gpt.name, OMAP_TIMER_POSTED); |
aa561889 | 342 | BUG_ON(res); |
f248076c | 343 | |
a032d33b | 344 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 345 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 346 | |
ee17f114 | 347 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 | 348 | |
11d6ec2e SS |
349 | clockevent_gpt.cpumask = cpu_possible_mask; |
350 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
838a2ae8 SG |
351 | clockevents_config_and_register(&clockevent_gpt, clkev.rate, |
352 | 3, /* Timer internal resynch latency */ | |
353 | 0xffffffff); | |
aa561889 | 354 | |
e95ea43a JH |
355 | pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, |
356 | clkev.rate); | |
5a3a388f KH |
357 | } |
358 | ||
f248076c | 359 | /* Clocksource code */ |
3d05a3e8 | 360 | static struct omap_dm_timer clksrc; |
1fe97c8f | 361 | static bool use_gptimer_clksrc; |
3d05a3e8 | 362 | |
5a3a388f KH |
363 | /* |
364 | * clocksource | |
365 | */ | |
8e19608e | 366 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 367 | { |
971d0254 | 368 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 369 | OMAP_TIMER_NONPOSTED); |
5a3a388f KH |
370 | } |
371 | ||
372 | static struct clocksource clocksource_gpt = { | |
5a3a388f KH |
373 | .rating = 300, |
374 | .read = clocksource_read_cycles, | |
375 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
376 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
377 | }; | |
378 | ||
2f0778af | 379 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 380 | { |
3d05a3e8 | 381 | if (clksrc.reserved) |
971d0254 | 382 | return __omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 383 | OMAP_TIMER_NONPOSTED); |
5a3a388f | 384 | |
2f0778af | 385 | return 0; |
3d05a3e8 TL |
386 | } |
387 | ||
258e84af JH |
388 | static struct of_device_id omap_counter_match[] __initdata = { |
389 | { .compatible = "ti,omap-counter32k", }, | |
390 | { } | |
391 | }; | |
392 | ||
3d05a3e8 | 393 | /* Setup free-running counter for clocksource */ |
e0c3e27c | 394 | static int __init __maybe_unused omap2_sync32k_clocksource_init(void) |
1fe97c8f VH |
395 | { |
396 | int ret; | |
9883f7c8 | 397 | struct device_node *np = NULL; |
1fe97c8f VH |
398 | struct omap_hwmod *oh; |
399 | void __iomem *vbase; | |
400 | const char *oh_name = "counter_32k"; | |
401 | ||
9883f7c8 JH |
402 | /* |
403 | * If device-tree is present, then search the DT blob | |
404 | * to see if the 32kHz counter is supported. | |
405 | */ | |
406 | if (of_have_populated_dt()) { | |
407 | np = omap_get_timer_dt(omap_counter_match, NULL); | |
408 | if (!np) | |
409 | return -ENODEV; | |
410 | ||
411 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
412 | if (!oh_name) | |
413 | return -ENODEV; | |
414 | } | |
415 | ||
1fe97c8f VH |
416 | /* |
417 | * First check hwmod data is available for sync32k counter | |
418 | */ | |
419 | oh = omap_hwmod_lookup(oh_name); | |
420 | if (!oh || oh->slaves_cnt == 0) | |
421 | return -ENODEV; | |
422 | ||
423 | omap_hwmod_setup_one(oh_name); | |
424 | ||
9883f7c8 JH |
425 | if (np) { |
426 | vbase = of_iomap(np, 0); | |
427 | of_node_put(np); | |
428 | } else { | |
429 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
430 | } | |
431 | ||
1fe97c8f VH |
432 | if (!vbase) { |
433 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
434 | return -ENXIO; | |
435 | } | |
436 | ||
437 | ret = omap_hwmod_enable(oh); | |
438 | if (ret) { | |
439 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
440 | __func__, ret); | |
441 | return ret; | |
442 | } | |
443 | ||
444 | ret = omap_init_clocksource_32k(vbase); | |
445 | if (ret) { | |
446 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
447 | __func__, ret); | |
448 | omap_hwmod_idle(oh); | |
449 | } | |
450 | ||
451 | return ret; | |
452 | } | |
453 | ||
454 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
2eb03937 JH |
455 | const char *fck_source, |
456 | const char *property) | |
3d05a3e8 TL |
457 | { |
458 | int res; | |
459 | ||
8f6924dc | 460 | clksrc.id = gptimer_id; |
bfd6d021 JH |
461 | clksrc.errata = omap_dm_timer_get_errata(); |
462 | ||
8f6924dc | 463 | res = omap_dm_timer_init_one(&clksrc, fck_source, property, |
e95ea43a | 464 | &clocksource_gpt.name, |
bfd6d021 | 465 | OMAP_TIMER_NONPOSTED); |
3d05a3e8 | 466 | BUG_ON(res); |
5a3a388f | 467 | |
ee17f114 | 468 | __omap_dm_timer_load_start(&clksrc, |
971d0254 | 469 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
bfd6d021 | 470 | OMAP_TIMER_NONPOSTED); |
2f0778af | 471 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 472 | |
3d05a3e8 TL |
473 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
474 | pr_err("Could not register clocksource %s\n", | |
475 | clocksource_gpt.name); | |
1fe97c8f | 476 | else |
e95ea43a JH |
477 | pr_info("OMAP clocksource: %s at %lu Hz\n", |
478 | clocksource_gpt.name, clksrc.rate); | |
1fe97c8f VH |
479 | } |
480 | ||
fa6d79d2 SS |
481 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
482 | /* | |
483 | * The realtime counter also called master counter, is a free-running | |
484 | * counter, which is related to real time. It produces the count used | |
485 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
486 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
487 | * in different power modes, the master counter shifts operation between | |
488 | * clocks, adjusting the increment per clock in hardware accordingly to | |
489 | * maintain a constant count rate. | |
490 | */ | |
491 | static void __init realtime_counter_init(void) | |
492 | { | |
493 | void __iomem *base; | |
494 | static struct clk *sys_clk; | |
495 | unsigned long rate; | |
496 | unsigned int reg, num, den; | |
497 | ||
498 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
499 | if (!base) { | |
500 | pr_err("%s: ioremap failed\n", __func__); | |
501 | return; | |
502 | } | |
7f585bbf | 503 | sys_clk = clk_get(NULL, "sys_clkin"); |
533b2981 | 504 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
505 | pr_err("%s: failed to get system clock handle\n", __func__); |
506 | iounmap(base); | |
507 | return; | |
508 | } | |
509 | ||
510 | rate = clk_get_rate(sys_clk); | |
511 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
512 | switch (rate) { | |
513 | case 1200000: | |
514 | num = 64; | |
515 | den = 125; | |
516 | break; | |
517 | case 1300000: | |
518 | num = 768; | |
519 | den = 1625; | |
520 | break; | |
521 | case 19200000: | |
522 | num = 8; | |
523 | den = 25; | |
524 | break; | |
38a1981c S |
525 | case 20000000: |
526 | num = 192; | |
527 | den = 625; | |
528 | break; | |
fa6d79d2 SS |
529 | case 2600000: |
530 | num = 384; | |
531 | den = 1625; | |
532 | break; | |
533 | case 2700000: | |
534 | num = 256; | |
535 | den = 1125; | |
536 | break; | |
537 | case 38400000: | |
538 | default: | |
539 | /* Program it for 38.4 MHz */ | |
540 | num = 4; | |
541 | den = 25; | |
542 | break; | |
543 | } | |
544 | ||
545 | /* Program numerator and denumerator registers */ | |
546 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
547 | NUMERATOR_DENUMERATOR_MASK; | |
548 | reg |= num; | |
549 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
550 | ||
42c604ba | 551 | reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & |
fa6d79d2 SS |
552 | NUMERATOR_DENUMERATOR_MASK; |
553 | reg |= den; | |
554 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
555 | ||
5523e409 S |
556 | arch_timer_freq = (rate / den) * num; |
557 | set_cntfreq(); | |
558 | ||
fa6d79d2 SS |
559 | iounmap(base); |
560 | } | |
561 | #else | |
562 | static inline void __init realtime_counter_init(void) | |
563 | {} | |
564 | #endif | |
565 | ||
6f80b3bb | 566 | #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
2eb03937 | 567 | clksrc_nr, clksrc_src, clksrc_prop) \ |
6bb27d73 | 568 | void __init omap##name##_gptimer_timer_init(void) \ |
6f80b3bb | 569 | { \ |
9affd6be LT |
570 | if (omap_clk_init) \ |
571 | omap_clk_init(); \ | |
6f80b3bb IG |
572 | omap_dmtimer_init(); \ |
573 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ | |
2eb03937 JH |
574 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ |
575 | clksrc_prop); \ | |
6f80b3bb IG |
576 | } |
577 | ||
578 | #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ | |
2eb03937 | 579 | clksrc_nr, clksrc_src, clksrc_prop) \ |
6bb27d73 | 580 | void __init omap##name##_sync32k_timer_init(void) \ |
e74984e4 | 581 | { \ |
9affd6be LT |
582 | if (omap_clk_init) \ |
583 | omap_clk_init(); \ | |
ad24bde8 | 584 | omap_dmtimer_init(); \ |
9725f445 | 585 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
6f80b3bb IG |
586 | /* Enable the use of clocksource="gp_timer" kernel parameter */ \ |
587 | if (use_gptimer_clksrc) \ | |
2eb03937 JH |
588 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ |
589 | clksrc_prop); \ | |
6f80b3bb IG |
590 | else \ |
591 | omap2_sync32k_clocksource_init(); \ | |
e74984e4 TL |
592 | } |
593 | ||
e74984e4 | 594 | #ifdef CONFIG_ARCH_OMAP2 |
7bdc83f7 | 595 | OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", |
2eb03937 | 596 | 2, "timer_sys_ck", NULL); |
6f80b3bb | 597 | #endif /* CONFIG_ARCH_OMAP2 */ |
e74984e4 | 598 | |
bb256f80 | 599 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) |
7bdc83f7 | 600 | OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", |
2eb03937 | 601 | 2, "timer_sys_ck", NULL); |
7bdc83f7 | 602 | OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", |
2eb03937 | 603 | 2, "timer_sys_ck", NULL); |
6f80b3bb | 604 | #endif /* CONFIG_ARCH_OMAP3 */ |
e74984e4 | 605 | |
00ea4d56 | 606 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
2eb03937 JH |
607 | OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, |
608 | 1, "timer_sys_ck", "ti,timer-alwon"); | |
00ea4d56 | 609 | #endif |
08f30989 | 610 | |
f18153f9 S |
611 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
612 | defined(CONFIG_SOC_DRA7XX) | |
4615943c JH |
613 | static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", |
614 | 2, "sys_clkin_ck", NULL); | |
00ea4d56 | 615 | #endif |
08f30989 | 616 | |
e74984e4 | 617 | #ifdef CONFIG_ARCH_OMAP4 |
18060f35 | 618 | #ifdef CONFIG_HAVE_ARM_TWD |
6f80b3bb | 619 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); |
6bb27d73 | 620 | void __init omap4_local_timer_init(void) |
a45c983f | 621 | { |
6f80b3bb | 622 | omap4_sync32k_timer_init(); |
a45c983f MZ |
623 | /* Local timers are not supprted on OMAP4430 ES1.0 */ |
624 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
625 | int err; | |
626 | ||
eed0de27 | 627 | if (of_have_populated_dt()) { |
da4a686a | 628 | clocksource_of_init(); |
eed0de27 SS |
629 | return; |
630 | } | |
631 | ||
a45c983f MZ |
632 | err = twd_local_timer_register(&twd_local_timer); |
633 | if (err) | |
634 | pr_err("twd_local_timer_register failed %d\n", err); | |
635 | } | |
1dbae815 | 636 | } |
18060f35 | 637 | #else |
6bb27d73 | 638 | void __init omap4_local_timer_init(void) |
6f80b3bb | 639 | { |
73f14f6d | 640 | omap4_sync32k_timer_init(); |
6f80b3bb | 641 | } |
18060f35 | 642 | #endif /* CONFIG_HAVE_ARM_TWD */ |
6f80b3bb | 643 | #endif /* CONFIG_ARCH_OMAP4 */ |
c345c8b0 | 644 | |
37b3280d | 645 | #ifdef CONFIG_SOC_OMAP5 |
6bb27d73 | 646 | void __init omap5_realtime_timer_init(void) |
fa6d79d2 | 647 | { |
00ea4d56 | 648 | omap4_sync32k_timer_init(); |
fa6d79d2 | 649 | realtime_counter_init(); |
3c7c5dab | 650 | |
405f5e5e | 651 | clocksource_of_init(); |
fa6d79d2 | 652 | } |
6f80b3bb | 653 | #endif /* CONFIG_SOC_OMAP5 */ |
37b3280d | 654 | |
c345c8b0 TKD |
655 | /** |
656 | * omap_timer_init - build and register timer device with an | |
657 | * associated timer hwmod | |
658 | * @oh: timer hwmod pointer to be used to build timer device | |
659 | * @user: parameter that can be passed from calling hwmod API | |
660 | * | |
661 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
662 | * devices present in the system. The number of timer devices is known | |
663 | * by parsing through the hwmod database for a given class name. At the | |
664 | * end of function call memory is allocated for timer device and it is | |
665 | * registered to the framework ready to be proved by the driver. | |
666 | */ | |
667 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
668 | { | |
669 | int id; | |
670 | int ret = 0; | |
671 | char *name = "omap_timer"; | |
672 | struct dmtimer_platform_data *pdata; | |
c541c15f | 673 | struct platform_device *pdev; |
c345c8b0 TKD |
674 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
675 | ||
676 | pr_debug("%s: %s\n", __func__, oh->name); | |
677 | ||
678 | /* on secure device, do not register secure timer */ | |
679 | timer_dev_attr = oh->dev_attr; | |
680 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
681 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
682 | return ret; | |
683 | ||
684 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
685 | if (!pdata) { | |
686 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
687 | return -ENOMEM; | |
688 | } | |
689 | ||
690 | /* | |
691 | * Extract the IDs from name field in hwmod database | |
692 | * and use the same for constructing ids' for the | |
693 | * timer devices. In a way, we are avoiding usage of | |
694 | * static variable witin the function to do the same. | |
695 | * CAUTION: We have to be careful and make sure the | |
696 | * name in hwmod database does not change in which case | |
697 | * we might either make corresponding change here or | |
698 | * switch back static variable mechanism. | |
699 | */ | |
700 | sscanf(oh->name, "timer%2d", &id); | |
701 | ||
d1c1691b JH |
702 | if (timer_dev_attr) |
703 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 704 | |
bfd6d021 | 705 | pdata->timer_errata = omap_dm_timer_get_errata(); |
6e740f9a TL |
706 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; |
707 | ||
c1d1cd59 | 708 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); |
c345c8b0 | 709 | |
c541c15f | 710 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
711 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
712 | __func__, name, oh->name); | |
713 | ret = -EINVAL; | |
714 | } | |
715 | ||
716 | kfree(pdata); | |
717 | ||
718 | return ret; | |
719 | } | |
3392cdd3 TKD |
720 | |
721 | /** | |
722 | * omap2_dm_timer_init - top level regular device initialization | |
723 | * | |
724 | * Uses dedicated hwmod api to parse through hwmod database for | |
725 | * given class name and then build and register the timer device. | |
726 | */ | |
727 | static int __init omap2_dm_timer_init(void) | |
728 | { | |
729 | int ret; | |
730 | ||
9725f445 JH |
731 | /* If dtb is there, the devices will be created dynamically */ |
732 | if (of_have_populated_dt()) | |
733 | return -ENODEV; | |
734 | ||
3392cdd3 TKD |
735 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); |
736 | if (unlikely(ret)) { | |
737 | pr_err("%s: device registration failed.\n", __func__); | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
741 | return 0; | |
742 | } | |
b76c8b19 | 743 | omap_arch_initcall(omap2_dm_timer_init); |
1fe97c8f VH |
744 | |
745 | /** | |
746 | * omap2_override_clocksource - clocksource override with user configuration | |
747 | * | |
748 | * Allows user to override default clocksource, using kernel parameter | |
749 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
750 | * | |
751 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
752 | * and not introducing any OMAP specific interface. | |
753 | */ | |
754 | static int __init omap2_override_clocksource(char *str) | |
755 | { | |
756 | if (!str) | |
757 | return 0; | |
758 | /* | |
759 | * For OMAP architecture, we only have two options | |
760 | * - sync_32k (default) | |
761 | * - gp_timer (sys_clk based) | |
762 | */ | |
763 | if (!strcmp(str, "gp_timer")) | |
764 | use_gptimer_clksrc = true; | |
765 | ||
766 | return 0; | |
767 | } | |
768 | early_param("clocksource", omap2_override_clocksource); |