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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
40fc3bb5 JH |
42 | #include <linux/platform_device.h> |
43 | #include <linux/platform_data/dmtimer-omap.h> | |
f8ce2547 | 44 | |
1dbae815 | 45 | #include <asm/mach/time.h> |
a45c983f | 46 | #include <asm/smp_twd.h> |
cbc94380 | 47 | #include <asm/sched_clock.h> |
7d7e1eba | 48 | |
3c7c5dab | 49 | #include <asm/arch_timer.h> |
2a296c8f | 50 | #include "omap_hwmod.h" |
25c7d49e | 51 | #include "omap_device.h" |
5c2e8852 | 52 | #include <plat/counter-32k.h> |
7d7e1eba | 53 | #include <plat/dmtimer.h> |
1d5aef49 | 54 | #include "omap-pm.h" |
b481113a | 55 | |
dbc04161 | 56 | #include "soc.h" |
7d7e1eba | 57 | #include "common.h" |
b481113a | 58 | #include "powerdomain.h" |
1dbae815 | 59 | |
aa561889 TL |
60 | /* Parent clocks, eventually these will come from the clock framework */ |
61 | ||
62 | #define OMAP2_MPU_SOURCE "sys_ck" | |
63 | #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE | |
64 | #define OMAP4_MPU_SOURCE "sys_clkin_ck" | |
65 | #define OMAP2_32K_SOURCE "func_32k_ck" | |
66 | #define OMAP3_32K_SOURCE "omap_32k_fck" | |
67 | #define OMAP4_32K_SOURCE "sys_32k_ck" | |
68 | ||
69 | #ifdef CONFIG_OMAP_32K_TIMER | |
70 | #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE | |
71 | #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE | |
72 | #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE | |
73 | #define OMAP3_SECURE_TIMER 12 | |
9725f445 | 74 | #define TIMER_PROP_SECURE "ti,timer-secure" |
aa561889 TL |
75 | #else |
76 | #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE | |
77 | #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE | |
78 | #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE | |
79 | #define OMAP3_SECURE_TIMER 1 | |
9725f445 | 80 | #define TIMER_PROP_SECURE "ti,timer-alwon" |
aa561889 | 81 | #endif |
d8328f3b | 82 | |
fa6d79d2 SS |
83 | #define REALTIME_COUNTER_BASE 0x48243200 |
84 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
85 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
86 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
87 | ||
aa561889 TL |
88 | /* Clockevent code */ |
89 | ||
90 | static struct omap_dm_timer clkev; | |
5a3a388f | 91 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 92 | |
0cd61b68 | 93 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 94 | { |
5a3a388f KH |
95 | struct clock_event_device *evt = &clockevent_gpt; |
96 | ||
ee17f114 | 97 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 98 | |
5a3a388f | 99 | evt->event_handler(evt); |
1dbae815 TL |
100 | return IRQ_HANDLED; |
101 | } | |
102 | ||
103 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 104 | .name = "gp_timer", |
b30fabad | 105 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
106 | .handler = omap2_gp_timer_interrupt, |
107 | }; | |
108 | ||
5a3a388f KH |
109 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
110 | struct clock_event_device *evt) | |
1dbae815 | 111 | { |
ee17f114 | 112 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
971d0254 | 113 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
5a3a388f KH |
114 | |
115 | return 0; | |
116 | } | |
117 | ||
118 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
119 | struct clock_event_device *evt) | |
120 | { | |
121 | u32 period; | |
122 | ||
971d0254 | 123 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
5a3a388f KH |
124 | |
125 | switch (mode) { | |
126 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 127 | period = clkev.rate / HZ; |
5a3a388f | 128 | period -= 1; |
aa561889 | 129 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 130 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
971d0254 | 131 | 0xffffffff - period, OMAP_TIMER_POSTED); |
ee17f114 | 132 | __omap_dm_timer_load_start(&clkev, |
aa561889 | 133 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
971d0254 | 134 | 0xffffffff - period, OMAP_TIMER_POSTED); |
5a3a388f KH |
135 | break; |
136 | case CLOCK_EVT_MODE_ONESHOT: | |
137 | break; | |
138 | case CLOCK_EVT_MODE_UNUSED: | |
139 | case CLOCK_EVT_MODE_SHUTDOWN: | |
140 | case CLOCK_EVT_MODE_RESUME: | |
141 | break; | |
142 | } | |
143 | } | |
144 | ||
145 | static struct clock_event_device clockevent_gpt = { | |
f36921be | 146 | .name = "gp_timer", |
5a3a388f KH |
147 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
148 | .shift = 32, | |
11d6ec2e | 149 | .rating = 300, |
5a3a388f KH |
150 | .set_next_event = omap2_gp_timer_set_next_event, |
151 | .set_mode = omap2_gp_timer_set_mode, | |
152 | }; | |
153 | ||
ad24bde8 JH |
154 | static struct property device_disabled = { |
155 | .name = "status", | |
156 | .length = sizeof("disabled"), | |
157 | .value = "disabled", | |
158 | }; | |
159 | ||
160 | static struct of_device_id omap_timer_match[] __initdata = { | |
161 | { .compatible = "ti,omap2-timer", }, | |
162 | { } | |
163 | }; | |
164 | ||
9883f7c8 JH |
165 | static struct of_device_id omap_counter_match[] __initdata = { |
166 | { .compatible = "ti,omap-counter32k", }, | |
167 | { } | |
168 | }; | |
169 | ||
9725f445 JH |
170 | /** |
171 | * omap_get_timer_dt - get a timer using device-tree | |
172 | * @match - device-tree match structure for matching a device type | |
173 | * @property - optional timer property to match | |
174 | * | |
175 | * Helper function to get a timer during early boot using device-tree for use | |
176 | * as kernel system timer. Optionally, the property argument can be used to | |
177 | * select a timer with a specific property. Once a timer is found then mark | |
178 | * the timer node in device-tree as disabled, to prevent the kernel from | |
179 | * registering this timer as a platform device and so no one else can use it. | |
180 | */ | |
181 | static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, | |
182 | const char *property) | |
183 | { | |
184 | struct device_node *np; | |
185 | ||
186 | for_each_matching_node(np, match) { | |
187 | if (!of_device_is_available(np)) { | |
188 | of_node_put(np); | |
189 | continue; | |
190 | } | |
191 | ||
192 | if (property && !of_get_property(np, property, NULL)) { | |
193 | of_node_put(np); | |
194 | continue; | |
195 | } | |
196 | ||
197 | prom_add_property(np, &device_disabled); | |
198 | return np; | |
199 | } | |
200 | ||
201 | return NULL; | |
202 | } | |
203 | ||
ad24bde8 JH |
204 | /** |
205 | * omap_dmtimer_init - initialisation function when device tree is used | |
206 | * | |
207 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
208 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
209 | * kernel registering these devices remove them dynamically from the device | |
210 | * tree on boot. | |
211 | */ | |
212 | void __init omap_dmtimer_init(void) | |
213 | { | |
214 | struct device_node *np; | |
215 | ||
216 | if (!cpu_is_omap34xx()) | |
217 | return; | |
218 | ||
219 | /* If we are a secure device, remove any secure timer nodes */ | |
220 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 JH |
221 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
222 | if (np) | |
223 | of_node_put(np); | |
ad24bde8 JH |
224 | } |
225 | } | |
226 | ||
bfd6d021 JH |
227 | /** |
228 | * omap_dm_timer_get_errata - get errata flags for a timer | |
229 | * | |
230 | * Get the timer errata flags that are specific to the OMAP device being used. | |
231 | */ | |
232 | u32 __init omap_dm_timer_get_errata(void) | |
233 | { | |
234 | if (cpu_is_omap24xx()) | |
235 | return 0; | |
236 | ||
237 | return OMAP_TIMER_ERRATA_I103_I767; | |
238 | } | |
239 | ||
aa561889 TL |
240 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
241 | int gptimer_id, | |
9725f445 | 242 | const char *fck_source, |
bfd6d021 JH |
243 | const char *property, |
244 | int posted) | |
5a3a388f | 245 | { |
aa561889 | 246 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
9725f445 JH |
247 | const char *oh_name; |
248 | struct device_node *np; | |
aa561889 | 249 | struct omap_hwmod *oh; |
61b001c5 | 250 | struct resource irq, mem; |
f88095ba | 251 | int r = 0; |
aa561889 | 252 | |
9725f445 JH |
253 | if (of_have_populated_dt()) { |
254 | np = omap_get_timer_dt(omap_timer_match, NULL); | |
255 | if (!np) | |
256 | return -ENODEV; | |
257 | ||
258 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
259 | if (!oh_name) | |
260 | return -ENODEV; | |
261 | ||
262 | timer->irq = irq_of_parse_and_map(np, 0); | |
263 | if (!timer->irq) | |
264 | return -ENXIO; | |
265 | ||
266 | timer->io_base = of_iomap(np, 0); | |
267 | ||
268 | of_node_put(np); | |
269 | } else { | |
270 | if (omap_dm_timer_reserve_systimer(gptimer_id)) | |
271 | return -ENODEV; | |
272 | ||
273 | sprintf(name, "timer%d", gptimer_id); | |
274 | oh_name = name; | |
275 | } | |
276 | ||
9725f445 | 277 | oh = omap_hwmod_lookup(oh_name); |
aa561889 TL |
278 | if (!oh) |
279 | return -ENODEV; | |
280 | ||
9725f445 JH |
281 | if (!of_have_populated_dt()) { |
282 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | |
61b001c5 | 283 | &irq); |
9725f445 JH |
284 | if (r) |
285 | return -ENXIO; | |
61b001c5 | 286 | timer->irq = irq.start; |
9725f445 JH |
287 | |
288 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, | |
61b001c5 | 289 | &mem); |
9725f445 JH |
290 | if (r) |
291 | return -ENXIO; | |
9725f445 JH |
292 | |
293 | /* Static mapping, never released */ | |
61b001c5 | 294 | timer->io_base = ioremap(mem.start, mem.end - mem.start); |
9725f445 | 295 | } |
aa561889 | 296 | |
aa561889 TL |
297 | if (!timer->io_base) |
298 | return -ENXIO; | |
299 | ||
300 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 301 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 TL |
302 | if (IS_ERR(timer->fclk)) |
303 | return -ENODEV; | |
304 | ||
9725f445 | 305 | /* FIXME: Need to remove hard-coded test on timer ID */ |
aa561889 TL |
306 | if (gptimer_id != 12) { |
307 | struct clk *src; | |
308 | ||
309 | src = clk_get(NULL, fck_source); | |
310 | if (IS_ERR(src)) { | |
f88095ba | 311 | r = -EINVAL; |
aa561889 | 312 | } else { |
f88095ba JH |
313 | r = clk_set_parent(timer->fclk, src); |
314 | if (IS_ERR_VALUE(r)) | |
9725f445 JH |
315 | pr_warn("%s: %s cannot set source\n", |
316 | __func__, oh->name); | |
aa561889 TL |
317 | clk_put(src); |
318 | } | |
319 | } | |
b1538832 JH |
320 | |
321 | omap_hwmod_setup_one(oh_name); | |
322 | omap_hwmod_enable(oh); | |
ee17f114 | 323 | __omap_dm_timer_init_regs(timer); |
aa561889 | 324 | |
bfd6d021 JH |
325 | if (posted) |
326 | __omap_dm_timer_enable_posted(timer); | |
327 | ||
328 | /* Check that the intended posted configuration matches the actual */ | |
329 | if (posted != timer->posted) | |
330 | return -EINVAL; | |
1dbae815 | 331 | |
bfd6d021 | 332 | timer->rate = clk_get_rate(timer->fclk); |
aa561889 | 333 | timer->reserved = 1; |
38698bef | 334 | |
f88095ba | 335 | return r; |
aa561889 | 336 | } |
f248076c | 337 | |
aa561889 | 338 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
339 | const char *fck_source, |
340 | const char *property) | |
aa561889 TL |
341 | { |
342 | int res; | |
f248076c | 343 | |
bfd6d021 JH |
344 | clkev.errata = omap_dm_timer_get_errata(); |
345 | ||
346 | /* | |
347 | * For clock-event timers we never read the timer counter and | |
348 | * so we are not impacted by errata i103 and i767. Therefore, | |
349 | * we can safely ignore this errata for clock-event timers. | |
350 | */ | |
351 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | |
352 | ||
353 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, | |
354 | OMAP_TIMER_POSTED); | |
aa561889 | 355 | BUG_ON(res); |
f248076c | 356 | |
a032d33b | 357 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 358 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 359 | |
ee17f114 | 360 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 TL |
361 | |
362 | clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, | |
5a3a388f KH |
363 | clockevent_gpt.shift); |
364 | clockevent_gpt.max_delta_ns = | |
365 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | |
366 | clockevent_gpt.min_delta_ns = | |
df88acbb AK |
367 | clockevent_delta2ns(3, &clockevent_gpt); |
368 | /* Timer internal resynch latency. */ | |
5a3a388f | 369 | |
11d6ec2e SS |
370 | clockevent_gpt.cpumask = cpu_possible_mask; |
371 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
5a3a388f | 372 | clockevents_register_device(&clockevent_gpt); |
aa561889 TL |
373 | |
374 | pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", | |
375 | gptimer_id, clkev.rate); | |
5a3a388f KH |
376 | } |
377 | ||
f248076c | 378 | /* Clocksource code */ |
3d05a3e8 | 379 | static struct omap_dm_timer clksrc; |
1fe97c8f | 380 | static bool use_gptimer_clksrc; |
3d05a3e8 | 381 | |
5a3a388f KH |
382 | /* |
383 | * clocksource | |
384 | */ | |
8e19608e | 385 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 386 | { |
971d0254 | 387 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 388 | OMAP_TIMER_NONPOSTED); |
5a3a388f KH |
389 | } |
390 | ||
391 | static struct clocksource clocksource_gpt = { | |
f36921be | 392 | .name = "gp_timer", |
5a3a388f KH |
393 | .rating = 300, |
394 | .read = clocksource_read_cycles, | |
395 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
396 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
397 | }; | |
398 | ||
2f0778af | 399 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 400 | { |
3d05a3e8 | 401 | if (clksrc.reserved) |
971d0254 | 402 | return __omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 403 | OMAP_TIMER_NONPOSTED); |
5a3a388f | 404 | |
2f0778af | 405 | return 0; |
3d05a3e8 TL |
406 | } |
407 | ||
45caae74 | 408 | #ifdef CONFIG_OMAP_32K_TIMER |
3d05a3e8 | 409 | /* Setup free-running counter for clocksource */ |
1fe97c8f VH |
410 | static int __init omap2_sync32k_clocksource_init(void) |
411 | { | |
412 | int ret; | |
9883f7c8 | 413 | struct device_node *np = NULL; |
1fe97c8f VH |
414 | struct omap_hwmod *oh; |
415 | void __iomem *vbase; | |
416 | const char *oh_name = "counter_32k"; | |
417 | ||
9883f7c8 JH |
418 | /* |
419 | * If device-tree is present, then search the DT blob | |
420 | * to see if the 32kHz counter is supported. | |
421 | */ | |
422 | if (of_have_populated_dt()) { | |
423 | np = omap_get_timer_dt(omap_counter_match, NULL); | |
424 | if (!np) | |
425 | return -ENODEV; | |
426 | ||
427 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
428 | if (!oh_name) | |
429 | return -ENODEV; | |
430 | } | |
431 | ||
1fe97c8f VH |
432 | /* |
433 | * First check hwmod data is available for sync32k counter | |
434 | */ | |
435 | oh = omap_hwmod_lookup(oh_name); | |
436 | if (!oh || oh->slaves_cnt == 0) | |
437 | return -ENODEV; | |
438 | ||
439 | omap_hwmod_setup_one(oh_name); | |
440 | ||
9883f7c8 JH |
441 | if (np) { |
442 | vbase = of_iomap(np, 0); | |
443 | of_node_put(np); | |
444 | } else { | |
445 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
446 | } | |
447 | ||
1fe97c8f VH |
448 | if (!vbase) { |
449 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
450 | return -ENXIO; | |
451 | } | |
452 | ||
453 | ret = omap_hwmod_enable(oh); | |
454 | if (ret) { | |
455 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
456 | __func__, ret); | |
457 | return ret; | |
458 | } | |
459 | ||
460 | ret = omap_init_clocksource_32k(vbase); | |
461 | if (ret) { | |
462 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
463 | __func__, ret); | |
464 | omap_hwmod_idle(oh); | |
465 | } | |
466 | ||
467 | return ret; | |
468 | } | |
45caae74 IG |
469 | #else |
470 | static inline int omap2_sync32k_clocksource_init(void) | |
471 | { | |
472 | return -ENODEV; | |
473 | } | |
474 | #endif | |
1fe97c8f VH |
475 | |
476 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
3d05a3e8 TL |
477 | const char *fck_source) |
478 | { | |
479 | int res; | |
480 | ||
bfd6d021 JH |
481 | clksrc.errata = omap_dm_timer_get_errata(); |
482 | ||
483 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL, | |
484 | OMAP_TIMER_NONPOSTED); | |
3d05a3e8 | 485 | BUG_ON(res); |
5a3a388f | 486 | |
ee17f114 | 487 | __omap_dm_timer_load_start(&clksrc, |
971d0254 | 488 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
bfd6d021 | 489 | OMAP_TIMER_NONPOSTED); |
2f0778af | 490 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 491 | |
3d05a3e8 TL |
492 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
493 | pr_err("Could not register clocksource %s\n", | |
494 | clocksource_gpt.name); | |
1fe97c8f VH |
495 | else |
496 | pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", | |
497 | gptimer_id, clksrc.rate); | |
498 | } | |
499 | ||
500 | static void __init omap2_clocksource_init(int gptimer_id, | |
501 | const char *fck_source) | |
502 | { | |
503 | /* | |
504 | * First give preference to kernel parameter configuration | |
505 | * by user (clocksource="gp_timer"). | |
506 | * | |
507 | * In case of missing kernel parameter for clocksource, | |
508 | * first check for availability for 32k-sync timer, in case | |
509 | * of failure in finding 32k_counter module or registering | |
510 | * it as clocksource, execution will fallback to gp-timer. | |
511 | */ | |
512 | if (use_gptimer_clksrc == true) | |
513 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
514 | else if (omap2_sync32k_clocksource_init()) | |
515 | /* Fall back to gp-timer code */ | |
516 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
5a3a388f | 517 | } |
5a3a388f | 518 | |
fa6d79d2 SS |
519 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
520 | /* | |
521 | * The realtime counter also called master counter, is a free-running | |
522 | * counter, which is related to real time. It produces the count used | |
523 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
524 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
525 | * in different power modes, the master counter shifts operation between | |
526 | * clocks, adjusting the increment per clock in hardware accordingly to | |
527 | * maintain a constant count rate. | |
528 | */ | |
529 | static void __init realtime_counter_init(void) | |
530 | { | |
531 | void __iomem *base; | |
532 | static struct clk *sys_clk; | |
533 | unsigned long rate; | |
534 | unsigned int reg, num, den; | |
535 | ||
536 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
537 | if (!base) { | |
538 | pr_err("%s: ioremap failed\n", __func__); | |
539 | return; | |
540 | } | |
541 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | |
533b2981 | 542 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
543 | pr_err("%s: failed to get system clock handle\n", __func__); |
544 | iounmap(base); | |
545 | return; | |
546 | } | |
547 | ||
548 | rate = clk_get_rate(sys_clk); | |
549 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
550 | switch (rate) { | |
551 | case 1200000: | |
552 | num = 64; | |
553 | den = 125; | |
554 | break; | |
555 | case 1300000: | |
556 | num = 768; | |
557 | den = 1625; | |
558 | break; | |
559 | case 19200000: | |
560 | num = 8; | |
561 | den = 25; | |
562 | break; | |
563 | case 2600000: | |
564 | num = 384; | |
565 | den = 1625; | |
566 | break; | |
567 | case 2700000: | |
568 | num = 256; | |
569 | den = 1125; | |
570 | break; | |
571 | case 38400000: | |
572 | default: | |
573 | /* Program it for 38.4 MHz */ | |
574 | num = 4; | |
575 | den = 25; | |
576 | break; | |
577 | } | |
578 | ||
579 | /* Program numerator and denumerator registers */ | |
580 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
581 | NUMERATOR_DENUMERATOR_MASK; | |
582 | reg |= num; | |
583 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
584 | ||
585 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
586 | NUMERATOR_DENUMERATOR_MASK; | |
587 | reg |= den; | |
588 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
589 | ||
590 | iounmap(base); | |
591 | } | |
592 | #else | |
593 | static inline void __init realtime_counter_init(void) | |
594 | {} | |
595 | #endif | |
596 | ||
9725f445 | 597 | #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
3d05a3e8 | 598 | clksrc_nr, clksrc_src) \ |
e74984e4 TL |
599 | static void __init omap##name##_timer_init(void) \ |
600 | { \ | |
ad24bde8 | 601 | omap_dmtimer_init(); \ |
9725f445 | 602 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
1fe97c8f | 603 | omap2_clocksource_init((clksrc_nr), clksrc_src); \ |
e74984e4 TL |
604 | } |
605 | ||
606 | #define OMAP_SYS_TIMER(name) \ | |
607 | struct sys_timer omap##name##_timer = { \ | |
608 | .init = omap##name##_timer_init, \ | |
609 | }; | |
610 | ||
611 | #ifdef CONFIG_ARCH_OMAP2 | |
9725f445 JH |
612 | OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon", |
613 | 2, OMAP2_MPU_SOURCE) | |
e74984e4 TL |
614 | OMAP_SYS_TIMER(2) |
615 | #endif | |
616 | ||
617 | #ifdef CONFIG_ARCH_OMAP3 | |
9725f445 JH |
618 | OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon", |
619 | 2, OMAP3_MPU_SOURCE) | |
e74984e4 | 620 | OMAP_SYS_TIMER(3) |
3d05a3e8 | 621 | OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, |
9725f445 | 622 | TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE) |
e74984e4 TL |
623 | OMAP_SYS_TIMER(3_secure) |
624 | #endif | |
625 | ||
08f30989 | 626 | #ifdef CONFIG_SOC_AM33XX |
9725f445 JH |
627 | OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", |
628 | 2, OMAP4_MPU_SOURCE) | |
08f30989 AM |
629 | OMAP_SYS_TIMER(3_am33xx) |
630 | #endif | |
631 | ||
e74984e4 | 632 | #ifdef CONFIG_ARCH_OMAP4 |
39e1d4c1 | 633 | #ifdef CONFIG_LOCAL_TIMERS |
a45c983f | 634 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, |
3f216ef3 | 635 | OMAP44XX_LOCAL_TWD_BASE, 29); |
39e1d4c1 | 636 | #endif |
a45c983f MZ |
637 | |
638 | static void __init omap4_timer_init(void) | |
639 | { | |
9725f445 | 640 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); |
1fe97c8f | 641 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
a45c983f MZ |
642 | #ifdef CONFIG_LOCAL_TIMERS |
643 | /* Local timers are not supprted on OMAP4430 ES1.0 */ | |
644 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
645 | int err; | |
646 | ||
eed0de27 SS |
647 | if (of_have_populated_dt()) { |
648 | twd_local_timer_of_register(); | |
649 | return; | |
650 | } | |
651 | ||
a45c983f MZ |
652 | err = twd_local_timer_register(&twd_local_timer); |
653 | if (err) | |
654 | pr_err("twd_local_timer_register failed %d\n", err); | |
655 | } | |
656 | #endif | |
1dbae815 | 657 | } |
e74984e4 TL |
658 | OMAP_SYS_TIMER(4) |
659 | #endif | |
c345c8b0 | 660 | |
37b3280d | 661 | #ifdef CONFIG_SOC_OMAP5 |
fa6d79d2 SS |
662 | static void __init omap5_timer_init(void) |
663 | { | |
3c7c5dab SS |
664 | int err; |
665 | ||
9725f445 | 666 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); |
fa6d79d2 SS |
667 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
668 | realtime_counter_init(); | |
3c7c5dab SS |
669 | |
670 | err = arch_timer_of_register(); | |
671 | if (err) | |
672 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | |
fa6d79d2 | 673 | } |
37b3280d S |
674 | OMAP_SYS_TIMER(5) |
675 | #endif | |
676 | ||
c345c8b0 TKD |
677 | /** |
678 | * omap_timer_init - build and register timer device with an | |
679 | * associated timer hwmod | |
680 | * @oh: timer hwmod pointer to be used to build timer device | |
681 | * @user: parameter that can be passed from calling hwmod API | |
682 | * | |
683 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
684 | * devices present in the system. The number of timer devices is known | |
685 | * by parsing through the hwmod database for a given class name. At the | |
686 | * end of function call memory is allocated for timer device and it is | |
687 | * registered to the framework ready to be proved by the driver. | |
688 | */ | |
689 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
690 | { | |
691 | int id; | |
692 | int ret = 0; | |
693 | char *name = "omap_timer"; | |
694 | struct dmtimer_platform_data *pdata; | |
c541c15f | 695 | struct platform_device *pdev; |
c345c8b0 TKD |
696 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
697 | ||
698 | pr_debug("%s: %s\n", __func__, oh->name); | |
699 | ||
700 | /* on secure device, do not register secure timer */ | |
701 | timer_dev_attr = oh->dev_attr; | |
702 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
703 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
704 | return ret; | |
705 | ||
706 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
707 | if (!pdata) { | |
708 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
709 | return -ENOMEM; | |
710 | } | |
711 | ||
712 | /* | |
713 | * Extract the IDs from name field in hwmod database | |
714 | * and use the same for constructing ids' for the | |
715 | * timer devices. In a way, we are avoiding usage of | |
716 | * static variable witin the function to do the same. | |
717 | * CAUTION: We have to be careful and make sure the | |
718 | * name in hwmod database does not change in which case | |
719 | * we might either make corresponding change here or | |
720 | * switch back static variable mechanism. | |
721 | */ | |
722 | sscanf(oh->name, "timer%2d", &id); | |
723 | ||
d1c1691b JH |
724 | if (timer_dev_attr) |
725 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 726 | |
bfd6d021 | 727 | pdata->timer_errata = omap_dm_timer_get_errata(); |
6e740f9a TL |
728 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; |
729 | ||
c541c15f | 730 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), |
c16ae1e6 | 731 | NULL, 0, 0); |
c345c8b0 | 732 | |
c541c15f | 733 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
734 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
735 | __func__, name, oh->name); | |
736 | ret = -EINVAL; | |
737 | } | |
738 | ||
739 | kfree(pdata); | |
740 | ||
741 | return ret; | |
742 | } | |
3392cdd3 TKD |
743 | |
744 | /** | |
745 | * omap2_dm_timer_init - top level regular device initialization | |
746 | * | |
747 | * Uses dedicated hwmod api to parse through hwmod database for | |
748 | * given class name and then build and register the timer device. | |
749 | */ | |
750 | static int __init omap2_dm_timer_init(void) | |
751 | { | |
752 | int ret; | |
753 | ||
9725f445 JH |
754 | /* If dtb is there, the devices will be created dynamically */ |
755 | if (of_have_populated_dt()) | |
756 | return -ENODEV; | |
757 | ||
3392cdd3 TKD |
758 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); |
759 | if (unlikely(ret)) { | |
760 | pr_err("%s: device registration failed.\n", __func__); | |
761 | return -EINVAL; | |
762 | } | |
763 | ||
764 | return 0; | |
765 | } | |
766 | arch_initcall(omap2_dm_timer_init); | |
1fe97c8f VH |
767 | |
768 | /** | |
769 | * omap2_override_clocksource - clocksource override with user configuration | |
770 | * | |
771 | * Allows user to override default clocksource, using kernel parameter | |
772 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
773 | * | |
774 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
775 | * and not introducing any OMAP specific interface. | |
776 | */ | |
777 | static int __init omap2_override_clocksource(char *str) | |
778 | { | |
779 | if (!str) | |
780 | return 0; | |
781 | /* | |
782 | * For OMAP architecture, we only have two options | |
783 | * - sync_32k (default) | |
784 | * - gp_timer (sys_clk based) | |
785 | */ | |
786 | if (!strcmp(str, "gp_timer")) | |
787 | use_gptimer_clksrc = true; | |
788 | ||
789 | return 0; | |
790 | } | |
791 | early_param("clocksource", omap2_override_clocksource); |