[deliverable/linux.git] / arch / arm / mach-omap2 / vc.c

/*
 * OMAP Voltage Controller (VC) interface
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/bug.h>

#include <plat/cpu.h>

#include "voltage.h"
#include "vc.h"
#include "prm-regbits-34xx.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"

/**
 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
 * @sa: bit for slave address
 * @rav: bit for voltage configuration register
 * @rac: bit for command configuration register
 * @racen: enable bit for RAC
 * @cmd: bit for command value set selection
 *
 * Channel configuration bits, common for OMAP3+
 * OMAP3 register: PRM_VC_CH_CONF
 * OMAP4 register: PRM_VC_CFG_CHANNEL
 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
 */
struct omap_vc_channel_cfg {
	u8 sa;
	u8 rav;
	u8 rac;
	u8 racen;
	u8 cmd;
};

static struct omap_vc_channel_cfg vc_default_channel_cfg = {
	.sa    = BIT(0),
	.rav   = BIT(1),
	.rac   = BIT(2),
	.racen = BIT(3),
	.cmd   = BIT(4),
};

/*
 * On OMAP3+, all VC channels have the above default bitfield
 * configuration, except the OMAP4 MPU channel.  This appears
 * to be a freak accident as every other VC channel has the
 * default configuration, thus creating a mutant channel config.
 */
static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
	.sa    = BIT(0),
	.rav   = BIT(2),
	.rac   = BIT(3),
	.racen = BIT(4),
	.cmd   = BIT(1),
};

static struct omap_vc_channel_cfg *vc_cfg_bits;
#define CFG_CHANNEL_MASK 0x1f

/**
 * omap_vc_config_channel - configure VC channel to PMIC mappings
 * @voltdm: pointer to voltagdomain defining the desired VC channel
 *
 * Configures the VC channel to PMIC mappings for the following
 * PMIC settings
 * - i2c slave address (SA)
 * - voltage configuration address (RAV)
 * - command configuration address (RAC) and enable bit (RACEN)
 * - command values for ON, ONLP, RET and OFF (CMD)
 *
 * This function currently only allows flexible configuration of the
 * non-default channel.  Starting with OMAP4, there are more than 2
 * channels, with one defined as the default (on OMAP4, it's MPU.)
 * Only the non-default channel can be configured.
 */
static int omap_vc_config_channel(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;

	/*
	 * For default channel, the only configurable bit is RACEN.
	 * All others must stay at zero (see function comment above.)
	 */
	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
		vc->cfg_channel &= vc_cfg_bits->racen;

	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
		    vc->cfg_channel << vc->cfg_channel_sa_shift,
		    vc->cfg_channel_reg);

	return 0;
}

/* Voltage scale and accessory APIs */
int omap_vc_pre_scale(struct voltagedomain *voltdm,
		      unsigned long target_volt,
		      u8 *target_vsel, u8 *current_vsel)
{
	struct omap_vc_channel *vc = voltdm->vc;
	u32 vc_cmdval;

	/* Check if sufficient pmic info is available for this vdd */
	if (!voltdm->pmic) {
		pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
			__func__, voltdm->name);
		return -EINVAL;
	}

	if (!voltdm->pmic->uv_to_vsel) {
		pr_err("%s: PMIC function to convert voltage in uV to"
			"vsel not registered. Hence unable to scale voltage"
			"for vdd_%s\n", __func__, voltdm->name);
		return -ENODATA;
	}

	if (!voltdm->read || !voltdm->write) {
		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
			__func__, voltdm->name);
		return -EINVAL;
	}

	*target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
	*current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);

	/* Setting the ON voltage to the new target voltage */
	vc_cmdval = voltdm->read(vc->cmdval_reg);
	vc_cmdval &= ~vc->common->cmd_on_mask;
	vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
	voltdm->write(vc_cmdval, vc->cmdval_reg);

	omap_vp_update_errorgain(voltdm, target_volt);

	return 0;
}

void omap_vc_post_scale(struct voltagedomain *voltdm,
			unsigned long target_volt,
			u8 target_vsel, u8 current_vsel)
{
	u32 smps_steps = 0, smps_delay = 0;

	smps_steps = abs(target_vsel - current_vsel);
	/* SMPS slew rate / step size. 2us added as buffer. */
	smps_delay = ((smps_steps * voltdm->pmic->step_size) /
			voltdm->pmic->slew_rate) + 2;
	udelay(smps_delay);
}

/* vc_bypass_scale - VC bypass method of voltage scaling */
int omap_vc_bypass_scale(struct voltagedomain *voltdm,
			 unsigned long target_volt)
{
	struct omap_vc_channel *vc = voltdm->vc;
	u32 loop_cnt = 0, retries_cnt = 0;
	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
	u8 target_vsel, current_vsel;
	int ret;

	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
	if (ret)
		return ret;

	vc_valid = vc->common->valid;
	vc_bypass_val_reg = vc->common->bypass_val_reg;
	vc_bypass_value = (target_vsel << vc->common->data_shift) |
		(vc->volt_reg_addr << vc->common->regaddr_shift) |
		(vc->i2c_slave_addr << vc->common->slaveaddr_shift);

	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
	voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);

	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
	/*
	 * Loop till the bypass command is acknowledged from the SMPS.
	 * NOTE: This is legacy code. The loop count and retry count needs
	 * to be revisited.
	 */
	while (!(vc_bypass_value & vc_valid)) {
		loop_cnt++;

		if (retries_cnt > 10) {
			pr_warning("%s: Retry count exceeded\n", __func__);
			return -ETIMEDOUT;
		}

		if (loop_cnt > 50) {
			retries_cnt++;
			loop_cnt = 0;
			udelay(10);
		}
		vc_bypass_value = voltdm->read(vc_bypass_val_reg);
	}

	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
	return 0;
}

static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
{
	/*
	 * Voltage Manager FSM parameters init
	 * XXX This data should be passed in from the board file
	 */
	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
}

static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
{
	static bool is_initialized;

	if (is_initialized)
		return;

	omap3_vfsm_init(voltdm);

	is_initialized = true;
}


/* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{
	static bool is_initialized;
	u32 vc_val;

	if (is_initialized)
		return;

	/* XXX These are magic numbers and do not belong! */
	vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);

	is_initialized = true;
}

/**
 * omap_vc_i2c_init - initialize I2C interface to PMIC
 * @voltdm: voltage domain containing VC data
 *
 * Use PMIC supplied settings for I2C high-speed mode and
 * master code (if set) and program the VC I2C configuration
 * register.
 *
 * The VC I2C configuration is common to all VC channels,
 * so this function only configures I2C for the first VC
 * channel registers.  All other VC channels will use the
 * same configuration.
 */
static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;
	static bool initialized;
	static bool i2c_high_speed;
	u8 mcode;

	if (initialized) {
		if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
			pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
				__func__, voltdm->name, i2c_high_speed);
		return;
	}

	i2c_high_speed = voltdm->pmic->i2c_high_speed;
	if (i2c_high_speed)
		voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
			    vc->common->i2c_cfg_hsen_mask,
			    vc->common->i2c_cfg_reg);

	mcode = voltdm->pmic->i2c_mcode;
	if (mcode)
		voltdm->rmw(vc->common->i2c_mcode_mask,
			    mcode << __ffs(vc->common->i2c_mcode_mask),
			    vc->common->i2c_cfg_reg);

	initialized = true;
}

void __init omap_vc_init_channel(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;
	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
	u32 val;

	if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
		pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
		return;
	}

	if (!voltdm->read || !voltdm->write) {
		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
			__func__, voltdm->name);
		return;
	}

	vc->cfg_channel = 0;
	if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
		vc_cfg_bits = &vc_mutant_channel_cfg;
	else
		vc_cfg_bits = &vc_default_channel_cfg;

	/* get PMIC/board specific settings */
	vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
	vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
	vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
	vc->setup_time = voltdm->pmic->volt_setup_time;

	/* Configure the i2c slave address for this VC */
	voltdm->rmw(vc->smps_sa_mask,
		    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
		    vc->smps_sa_reg);
	vc->cfg_channel |= vc_cfg_bits->sa;

	/*
	 * Configure the PMIC register addresses.
	 */
	voltdm->rmw(vc->smps_volra_mask,
		    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
		    vc->smps_volra_reg);
	vc->cfg_channel |= vc_cfg_bits->rav;

	if (vc->cmd_reg_addr) {
		voltdm->rmw(vc->smps_cmdra_mask,
			    vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
			    vc->smps_cmdra_reg);
		vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
	}

	/* Set up the on, inactive, retention and off voltage */
	on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
	onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
	ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
	off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
	val = ((on_vsel << vc->common->cmd_on_shift) |
	       (onlp_vsel << vc->common->cmd_onlp_shift) |
	       (ret_vsel << vc->common->cmd_ret_shift) |
	       (off_vsel << vc->common->cmd_off_shift));
	voltdm->write(val, vc->cmdval_reg);
	vc->cfg_channel |= vc_cfg_bits->cmd;

	/* Channel configuration */
	omap_vc_config_channel(voltdm);

	/* Configure the setup times */
	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
		    vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
		    voltdm->vfsm->voltsetup_reg);

	omap_vc_i2c_init(voltdm);

	if (cpu_is_omap34xx())
		omap3_vc_init_channel(voltdm);
	else if (cpu_is_omap44xx())
		omap4_vc_init_channel(voltdm);
}
Commit	Line	Data
ccd5ca77 KH	1	/*
	2	* OMAP Voltage Controller (VC) interface
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10	#include <linux/kernel.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
4647ca57	13	#include <linux/bug.h>
ccd5ca77 KH	14
	15	#include <plat/cpu.h>
	16
	17	#include "voltage.h"
	18	#include "vc.h"
	19	#include "prm-regbits-34xx.h"
	20	#include "prm-regbits-44xx.h"
	21	#include "prm44xx.h"
	22
8abc0b58 KH	23	/**
	24	* struct omap_vc_channel_cfg - describe the cfg_channel bitfield
	25	* @sa: bit for slave address
	26	* @rav: bit for voltage configuration register
	27	* @rac: bit for command configuration register
	28	* @racen: enable bit for RAC
	29	* @cmd: bit for command value set selection
	30	*
	31	* Channel configuration bits, common for OMAP3+
24d3194a KH	32	* OMAP3 register: PRM_VC_CH_CONF
24d3194a KH	33	* OMAP4 register: PRM_VC_CFG_CHANNEL
8abc0b58	34	* OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
24d3194a	35	*/
8abc0b58 KH	36	struct omap_vc_channel_cfg {
	37	u8 sa;
	38	u8 rav;
	39	u8 rac;
	40	u8 racen;
	41	u8 cmd;
	42	};
	43
	44	static struct omap_vc_channel_cfg vc_default_channel_cfg = {
	45	.sa = BIT(0),
	46	.rav = BIT(1),
	47	.rac = BIT(2),
	48	.racen = BIT(3),
	49	.cmd = BIT(4),
	50	};
	51
	52	/*
	53	* On OMAP3+, all VC channels have the above default bitfield
	54	* configuration, except the OMAP4 MPU channel. This appears
	55	* to be a freak accident as every other VC channel has the
	56	* default configuration, thus creating a mutant channel config.
	57	*/
	58	static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
	59	.sa = BIT(0),
	60	.rav = BIT(2),
	61	.rac = BIT(3),
	62	.racen = BIT(4),
	63	.cmd = BIT(1),
	64	};
	65
	66	static struct omap_vc_channel_cfg *vc_cfg_bits;
	67	#define CFG_CHANNEL_MASK 0x1f
24d3194a KH	68
	69	/**
	70	* omap_vc_config_channel - configure VC channel to PMIC mappings
	71	* @voltdm: pointer to voltagdomain defining the desired VC channel
	72	*
	73	* Configures the VC channel to PMIC mappings for the following
	74	* PMIC settings
	75	* - i2c slave address (SA)
	76	* - voltage configuration address (RAV)
	77	* - command configuration address (RAC) and enable bit (RACEN)
	78	* - command values for ON, ONLP, RET and OFF (CMD)
	79	*
	80	* This function currently only allows flexible configuration of the
	81	* non-default channel. Starting with OMAP4, there are more than 2
	82	* channels, with one defined as the default (on OMAP4, it's MPU.)
	83	* Only the non-default channel can be configured.
	84	*/
	85	static int omap_vc_config_channel(struct voltagedomain *voltdm)
	86	{
	87	struct omap_vc_channel *vc = voltdm->vc;
	88
	89	/*
	90	* For default channel, the only configurable bit is RACEN.
	91	* All others must stay at zero (see function comment above.)
	92	*/
	93	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
8abc0b58	94	vc->cfg_channel &= vc_cfg_bits->racen;
24d3194a KH	95
	96	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
	97	vc->cfg_channel << vc->cfg_channel_sa_shift,
5876c940	98	vc->cfg_channel_reg);
24d3194a KH	99
	100	return 0;
	101	}
	102
ccd5ca77 KH	103	/* Voltage scale and accessory APIs */
	104	int omap_vc_pre_scale(struct voltagedomain *voltdm,
	105	unsigned long target_volt,
	106	u8 target_vsel, u8 current_vsel)
	107	{
d84adcf4	108	struct omap_vc_channel *vc = voltdm->vc;
76ea7424	109	u32 vc_cmdval;
ccd5ca77	110
ccd5ca77	111	/* Check if sufficient pmic info is available for this vdd */
ce8ebe0d	112	if (!voltdm->pmic) {
ccd5ca77 KH	113	pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
	114	__func__, voltdm->name);
	115	return -EINVAL;
	116	}
	117
ce8ebe0d	118	if (!voltdm->pmic->uv_to_vsel) {
ccd5ca77 KH	119	pr_err("%s: PMIC function to convert voltage in uV to"
	120	"vsel not registered. Hence unable to scale voltage"
	121	"for vdd_%s\n", __func__, voltdm->name);
	122	return -ENODATA;
	123	}
	124
4bcc475e	125	if (!voltdm->read \|\| !voltdm->write) {
ccd5ca77 KH	126	pr_err("%s: No read/write API for accessing vdd_%s regs\n",
	127	__func__, voltdm->name);
	128	return -EINVAL;
	129	}
	130
ce8ebe0d	131	*target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
7590f608	132	*current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
ccd5ca77 KH	133
ccd5ca77 KH	134	/* Setting the ON voltage to the new target voltage */
4bcc475e	135	vc_cmdval = voltdm->read(vc->cmdval_reg);
d84adcf4 KH	136	vc_cmdval &= ~vc->common->cmd_on_mask;
d84adcf4 KH	137	vc_cmdval \|= (*target_vsel << vc->common->cmd_on_shift);
4bcc475e	138	voltdm->write(vc_cmdval, vc->cmdval_reg);
ccd5ca77	139
76ea7424	140	omap_vp_update_errorgain(voltdm, target_volt);
ccd5ca77 KH	141
	142	return 0;
	143	}
	144
	145	void omap_vc_post_scale(struct voltagedomain *voltdm,
	146	unsigned long target_volt,
	147	u8 target_vsel, u8 current_vsel)
	148	{
ccd5ca77 KH	149	u32 smps_steps = 0, smps_delay = 0;
	150
	151	smps_steps = abs(target_vsel - current_vsel);
	152	/* SMPS slew rate / step size. 2us added as buffer. */
ce8ebe0d KH	153	smps_delay = ((smps_steps * voltdm->pmic->step_size) /
ce8ebe0d KH	154	voltdm->pmic->slew_rate) + 2;
ccd5ca77	155	udelay(smps_delay);
ccd5ca77 KH	156	}
ccd5ca77 KH	157
d84adcf4 KH	158	/* vc_bypass_scale - VC bypass method of voltage scaling */
	159	int omap_vc_bypass_scale(struct voltagedomain *voltdm,
	160	unsigned long target_volt)
ccd5ca77	161	{
d84adcf4	162	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77 KH	163	u32 loop_cnt = 0, retries_cnt = 0;
	164	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
	165	u8 target_vsel, current_vsel;
	166	int ret;
	167
	168	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
	169	if (ret)
	170	return ret;
	171
d84adcf4 KH	172	vc_valid = vc->common->valid;
	173	vc_bypass_val_reg = vc->common->bypass_val_reg;
	174	vc_bypass_value = (target_vsel << vc->common->data_shift) \|
78614e0f KH	175	(vc->volt_reg_addr << vc->common->regaddr_shift) \|
78614e0f KH	176	(vc->i2c_slave_addr << vc->common->slaveaddr_shift);
ccd5ca77	177
4bcc475e KH	178	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
4bcc475e KH	179	voltdm->write(vc_bypass_value \| vc_valid, vc_bypass_val_reg);
ccd5ca77	180
4bcc475e	181	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
ccd5ca77 KH	182	/*
	183	* Loop till the bypass command is acknowledged from the SMPS.
	184	* NOTE: This is legacy code. The loop count and retry count needs
	185	* to be revisited.
	186	*/
	187	while (!(vc_bypass_value & vc_valid)) {
	188	loop_cnt++;
	189
	190	if (retries_cnt > 10) {
	191	pr_warning("%s: Retry count exceeded\n", __func__);
	192	return -ETIMEDOUT;
	193	}
	194
	195	if (loop_cnt > 50) {
	196	retries_cnt++;
	197	loop_cnt = 0;
	198	udelay(10);
	199	}
4bcc475e	200	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
ccd5ca77 KH	201	}
	202
	203	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
	204	return 0;
	205	}
	206
	207	static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
	208	{
ccd5ca77 KH	209	/*
	210	* Voltage Manager FSM parameters init
	211	* XXX This data should be passed in from the board file
	212	*/
4bcc475e KH	213	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
	214	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
	215	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
ccd5ca77 KH	216	}
	217
	218	static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
	219	{
ccd5ca77	220	static bool is_initialized;
ccd5ca77 KH	221
	222	if (is_initialized)
	223	return;
	224
ccd5ca77 KH	225	omap3_vfsm_init(voltdm);
	226
	227	is_initialized = true;
	228	}
	229
	230
	231	/* OMAP4 specific voltage init functions */
	232	static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
	233	{
ccd5ca77 KH	234	static bool is_initialized;
	235	u32 vc_val;
	236
	237	if (is_initialized)
	238	return;
	239
ccd5ca77 KH	240	/* XXX These are magic numbers and do not belong! */
ccd5ca77 KH	241	vc_val = (0x60 << OMAP4430_SCLL_SHIFT \| 0x26 << OMAP4430_SCLH_SHIFT);
4bcc475e	242	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
ccd5ca77 KH	243
	244	is_initialized = true;
	245	}
	246
f5395480 KH	247	/**
	248	* omap_vc_i2c_init - initialize I2C interface to PMIC
	249	* @voltdm: voltage domain containing VC data
	250	*
2d5b4790	251	* Use PMIC supplied settings for I2C high-speed mode and
f5395480 KH	252	* master code (if set) and program the VC I2C configuration
	253	* register.
	254	*
	255	* The VC I2C configuration is common to all VC channels,
	256	* so this function only configures I2C for the first VC
	257	* channel registers. All other VC channels will use the
	258	* same configuration.
	259	*/
	260	static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
	261	{
	262	struct omap_vc_channel *vc = voltdm->vc;
	263	static bool initialized;
	264	static bool i2c_high_speed;
	265	u8 mcode;
	266
	267	if (initialized) {
	268	if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
0bf68f53 RK	269	pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
0bf68f53 RK	270	__func__, voltdm->name, i2c_high_speed);
f5395480 KH	271	return;
	272	}
	273
	274	i2c_high_speed = voltdm->pmic->i2c_high_speed;
	275	if (i2c_high_speed)
	276	voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
	277	vc->common->i2c_cfg_hsen_mask,
	278	vc->common->i2c_cfg_reg);
	279
	280	mcode = voltdm->pmic->i2c_mcode;
	281	if (mcode)
	282	voltdm->rmw(vc->common->i2c_mcode_mask,
	283	mcode << __ffs(vc->common->i2c_mcode_mask),
	284	vc->common->i2c_cfg_reg);
	285
	286	initialized = true;
	287	}
	288
ccd5ca77 KH	289	void __init omap_vc_init_channel(struct voltagedomain *voltdm)
ccd5ca77 KH	290	{
d84adcf4	291	struct omap_vc_channel *vc = voltdm->vc;
08d1c9a3 KH	292	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
08d1c9a3 KH	293	u32 val;
ccd5ca77	294
ce8ebe0d	295	if (!voltdm->pmic \|\| !voltdm->pmic->uv_to_vsel) {
2d5b4790	296	pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
ccd5ca77 KH	297	return;
	298	}
	299
4bcc475e	300	if (!voltdm->read \|\| !voltdm->write) {
ccd5ca77 KH	301	pr_err("%s: No read/write API for accessing vdd_%s regs\n",
	302	__func__, voltdm->name);
	303	return;
	304	}
	305
24d3194a	306	vc->cfg_channel = 0;
8abc0b58 KH	307	if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
	308	vc_cfg_bits = &vc_mutant_channel_cfg;
	309	else
	310	vc_cfg_bits = &vc_default_channel_cfg;
24d3194a	311
ba112a4e	312	/* get PMIC/board specific settings */
ce8ebe0d KH	313	vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
	314	vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
	315	vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
	316	vc->setup_time = voltdm->pmic->volt_setup_time;
ba112a4e KH	317
	318	/* Configure the i2c slave address for this VC */
	319	voltdm->rmw(vc->smps_sa_mask,
	320	vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
5876c940	321	vc->smps_sa_reg);
8abc0b58	322	vc->cfg_channel \|= vc_cfg_bits->sa;
ccd5ca77	323
e4e021c5 KH	324	/*
	325	* Configure the PMIC register addresses.
	326	*/
	327	voltdm->rmw(vc->smps_volra_mask,
	328	vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
5876c940	329	vc->smps_volra_reg);
8abc0b58	330	vc->cfg_channel \|= vc_cfg_bits->rav;
24d3194a KH	331
24d3194a KH	332	if (vc->cmd_reg_addr) {
e4e021c5 KH	333	voltdm->rmw(vc->smps_cmdra_mask,
e4e021c5 KH	334	vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
5876c940	335	vc->smps_cmdra_reg);
8abc0b58	336	vc->cfg_channel \|= vc_cfg_bits->rac \| vc_cfg_bits->racen;
24d3194a	337	}
ccd5ca77	338
08d1c9a3	339	/* Set up the on, inactive, retention and off voltage */
ce8ebe0d KH	340	on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
	341	onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
	342	ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
	343	off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
08d1c9a3 KH	344	val = ((on_vsel << vc->common->cmd_on_shift) \|
	345	(onlp_vsel << vc->common->cmd_onlp_shift) \|
	346	(ret_vsel << vc->common->cmd_ret_shift) \|
	347	(off_vsel << vc->common->cmd_off_shift));
	348	voltdm->write(val, vc->cmdval_reg);
8abc0b58	349	vc->cfg_channel \|= vc_cfg_bits->cmd;
24d3194a KH	350
	351	/* Channel configuration */
	352	omap_vc_config_channel(voltdm);
08d1c9a3	353
ccd5ca77	354	/* Configure the setup times */
5892bb1f KH	355	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
	356	vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
	357	voltdm->vfsm->voltsetup_reg);
ccd5ca77	358
f5395480 KH	359	omap_vc_i2c_init(voltdm);
f5395480 KH	360
ccd5ca77 KH	361	if (cpu_is_omap34xx())
	362	omap3_vc_init_channel(voltdm);
	363	else if (cpu_is_omap44xx())
	364	omap4_vc_init_channel(voltdm);
	365	}
	366