[deliverable/linux.git] / arch / arm / mach-omap2 / vc.c

/*
 * OMAP Voltage Controller (VC) interface
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <plat/cpu.h>

#include "voltage.h"
#include "vc.h"
#include "prm-regbits-34xx.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"

/*
 * Channel configuration bits, common for OMAP3 & 4
 * OMAP3 register: PRM_VC_CH_CONF
 * OMAP4 register: PRM_VC_CFG_CHANNEL
 */
#define CFG_CHANNEL_SA    BIT(0)
#define CFG_CHANNEL_RAV   BIT(1)
#define CFG_CHANNEL_RAC   BIT(2)
#define CFG_CHANNEL_RACEN BIT(3)
#define CFG_CHANNEL_CMD   BIT(4)
#define CFG_CHANNEL_MASK 0x3f

/**
 * omap_vc_config_channel - configure VC channel to PMIC mappings
 * @voltdm: pointer to voltagdomain defining the desired VC channel
 *
 * Configures the VC channel to PMIC mappings for the following
 * PMIC settings
 * - i2c slave address (SA)
 * - voltage configuration address (RAV)
 * - command configuration address (RAC) and enable bit (RACEN)
 * - command values for ON, ONLP, RET and OFF (CMD)
 *
 * This function currently only allows flexible configuration of the
 * non-default channel.  Starting with OMAP4, there are more than 2
 * channels, with one defined as the default (on OMAP4, it's MPU.)
 * Only the non-default channel can be configured.
 */
static int omap_vc_config_channel(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;

	/*
	 * For default channel, the only configurable bit is RACEN.
	 * All others must stay at zero (see function comment above.)
	 */
	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
		vc->cfg_channel &= CFG_CHANNEL_RACEN;

	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
		    vc->cfg_channel << vc->cfg_channel_sa_shift,
		    vc->common->cfg_channel_reg);

	return 0;
}

/* Voltage scale and accessory APIs */
int omap_vc_pre_scale(struct voltagedomain *voltdm,
		      unsigned long target_volt,
		      u8 *target_vsel, u8 *current_vsel)
{
	struct omap_vc_channel *vc = voltdm->vc;
	struct omap_vdd_info *vdd = voltdm->vdd;
	struct omap_volt_data *volt_data;
	const struct omap_vp_common_data *vp_common;
	u32 vc_cmdval, vp_errgain_val;

	vp_common = vdd->vp_data->vp_common;

	/* Check if sufficient pmic info is available for this vdd */
	if (!vdd->pmic_info) {
		pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
			__func__, voltdm->name);
		return -EINVAL;
	}

	if (!vdd->pmic_info->uv_to_vsel) {
		pr_err("%s: PMIC function to convert voltage in uV to"
			"vsel not registered. Hence unable to scale voltage"
			"for vdd_%s\n", __func__, voltdm->name);
		return -ENODATA;
	}

	if (!voltdm->read || !voltdm->write) {
		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
			__func__, voltdm->name);
		return -EINVAL;
	}

	/* Get volt_data corresponding to target_volt */
	volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
	if (IS_ERR(volt_data))
		volt_data = NULL;

	*target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
	*current_vsel = voltdm->read(vdd->vp_data->voltage);

	/* Setting the ON voltage to the new target voltage */
	vc_cmdval = voltdm->read(vc->cmdval_reg);
	vc_cmdval &= ~vc->common->cmd_on_mask;
	vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
	voltdm->write(vc_cmdval, vc->cmdval_reg);

	/* Setting vp errorgain based on the voltage */
	if (volt_data) {
		vp_errgain_val = voltdm->read(vdd->vp_data->vpconfig);
		vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
		vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
		vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
			vp_common->vpconfig_errorgain_shift;
		voltdm->write(vp_errgain_val, vdd->vp_data->vpconfig);
	}

	return 0;
}

void omap_vc_post_scale(struct voltagedomain *voltdm,
			unsigned long target_volt,
			u8 target_vsel, u8 current_vsel)
{
	struct omap_vdd_info *vdd = voltdm->vdd;
	u32 smps_steps = 0, smps_delay = 0;

	smps_steps = abs(target_vsel - current_vsel);
	/* SMPS slew rate / step size. 2us added as buffer. */
	smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
			vdd->pmic_info->slew_rate) + 2;
	udelay(smps_delay);

	vdd->curr_volt = target_volt;
}

/* vc_bypass_scale - VC bypass method of voltage scaling */
int omap_vc_bypass_scale(struct voltagedomain *voltdm,
			 unsigned long target_volt)
{
	struct omap_vc_channel *vc = voltdm->vc;
	u32 loop_cnt = 0, retries_cnt = 0;
	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
	u8 target_vsel, current_vsel;
	int ret;

	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
	if (ret)
		return ret;

	vc_valid = vc->common->valid;
	vc_bypass_val_reg = vc->common->bypass_val_reg;
	vc_bypass_value = (target_vsel << vc->common->data_shift) |
		(vc->volt_reg_addr << vc->common->regaddr_shift) |
		(vc->i2c_slave_addr << vc->common->slaveaddr_shift);

	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
	voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);

	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
	/*
	 * Loop till the bypass command is acknowledged from the SMPS.
	 * NOTE: This is legacy code. The loop count and retry count needs
	 * to be revisited.
	 */
	while (!(vc_bypass_value & vc_valid)) {
		loop_cnt++;

		if (retries_cnt > 10) {
			pr_warning("%s: Retry count exceeded\n", __func__);
			return -ETIMEDOUT;
		}

		if (loop_cnt > 50) {
			retries_cnt++;
			loop_cnt = 0;
			udelay(10);
		}
		vc_bypass_value = voltdm->read(vc_bypass_val_reg);
	}

	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
	return 0;
}

static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
{
	/*
	 * Voltage Manager FSM parameters init
	 * XXX This data should be passed in from the board file
	 */
	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
}

static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
{
	static bool is_initialized;

	if (is_initialized)
		return;

	/*
	 * Generic VC parameters init
	 * XXX This data should be abstracted out
	 */
	voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
		       OMAP3_PRM_VC_I2C_CFG_OFFSET);

	omap3_vfsm_init(voltdm);

	is_initialized = true;
}


/* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{
	static bool is_initialized;
	u32 vc_val;

	if (is_initialized)
		return;

	/* XXX These are magic numbers and do not belong! */
	vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);

	is_initialized = true;
}

void __init omap_vc_init_channel(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;
	struct omap_vdd_info *vdd = voltdm->vdd;
	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
	u32 val;

	if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
		pr_err("%s: PMIC info requried to configure vc for"
			"vdd_%s not populated.Hence cannot initialize vc\n",
			__func__, voltdm->name);
		return;
	}

	if (!voltdm->read || !voltdm->write) {
		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
			__func__, voltdm->name);
		return;
	}

	vc->cfg_channel = 0;

	/* get PMIC/board specific settings */
	vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
	vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
	vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
	vc->setup_time = vdd->pmic_info->volt_setup_time;

	/* Configure the i2c slave address for this VC */
	voltdm->rmw(vc->smps_sa_mask,
		    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
		    vc->common->smps_sa_reg);
	vc->cfg_channel |= CFG_CHANNEL_SA;

	/*
	 * Configure the PMIC register addresses.
	 */
	voltdm->rmw(vc->smps_volra_mask,
		    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
		    vc->common->smps_volra_reg);
	vc->cfg_channel |= CFG_CHANNEL_RAV;

	if (vc->cmd_reg_addr) {
		voltdm->rmw(vc->smps_cmdra_mask,
			    vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
			    vc->common->smps_cmdra_reg);
		vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN;
	}

	/* Set up the on, inactive, retention and off voltage */
	on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
	onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
	ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
	off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
	val = ((on_vsel << vc->common->cmd_on_shift) |
	       (onlp_vsel << vc->common->cmd_onlp_shift) |
	       (ret_vsel << vc->common->cmd_ret_shift) |
	       (off_vsel << vc->common->cmd_off_shift));
	voltdm->write(val, vc->cmdval_reg);
	vc->cfg_channel |= CFG_CHANNEL_CMD;

	/* Channel configuration */
	omap_vc_config_channel(voltdm);

	/* Configure the setup times */
	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
		    vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
		    voltdm->vfsm->voltsetup_reg);

	if (cpu_is_omap34xx())
		omap3_vc_init_channel(voltdm);
	else if (cpu_is_omap44xx())
		omap4_vc_init_channel(voltdm);
}
Commit	Line	Data
ccd5ca77 KH	1	/*
	2	* OMAP Voltage Controller (VC) interface
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10	#include <linux/kernel.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13
	14	#include <plat/cpu.h>
	15
	16	#include "voltage.h"
	17	#include "vc.h"
	18	#include "prm-regbits-34xx.h"
	19	#include "prm-regbits-44xx.h"
	20	#include "prm44xx.h"
	21
24d3194a KH	22	/*
	23	* Channel configuration bits, common for OMAP3 & 4
	24	* OMAP3 register: PRM_VC_CH_CONF
	25	* OMAP4 register: PRM_VC_CFG_CHANNEL
	26	*/
	27	#define CFG_CHANNEL_SA BIT(0)
	28	#define CFG_CHANNEL_RAV BIT(1)
	29	#define CFG_CHANNEL_RAC BIT(2)
	30	#define CFG_CHANNEL_RACEN BIT(3)
	31	#define CFG_CHANNEL_CMD BIT(4)
	32	#define CFG_CHANNEL_MASK 0x3f
	33
	34	/**
	35	* omap_vc_config_channel - configure VC channel to PMIC mappings
	36	* @voltdm: pointer to voltagdomain defining the desired VC channel
	37	*
	38	* Configures the VC channel to PMIC mappings for the following
	39	* PMIC settings
	40	* - i2c slave address (SA)
	41	* - voltage configuration address (RAV)
	42	* - command configuration address (RAC) and enable bit (RACEN)
	43	* - command values for ON, ONLP, RET and OFF (CMD)
	44	*
	45	* This function currently only allows flexible configuration of the
	46	* non-default channel. Starting with OMAP4, there are more than 2
	47	* channels, with one defined as the default (on OMAP4, it's MPU.)
	48	* Only the non-default channel can be configured.
	49	*/
	50	static int omap_vc_config_channel(struct voltagedomain *voltdm)
	51	{
	52	struct omap_vc_channel *vc = voltdm->vc;
	53
	54	/*
	55	* For default channel, the only configurable bit is RACEN.
	56	* All others must stay at zero (see function comment above.)
	57	*/
	58	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
	59	vc->cfg_channel &= CFG_CHANNEL_RACEN;
	60
	61	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
	62	vc->cfg_channel << vc->cfg_channel_sa_shift,
	63	vc->common->cfg_channel_reg);
	64
	65	return 0;
	66	}
	67
ccd5ca77 KH	68	/* Voltage scale and accessory APIs */
	69	int omap_vc_pre_scale(struct voltagedomain *voltdm,
	70	unsigned long target_volt,
	71	u8 target_vsel, u8 current_vsel)
	72	{
d84adcf4	73	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77 KH	74	struct omap_vdd_info *vdd = voltdm->vdd;
ccd5ca77 KH	75	struct omap_volt_data *volt_data;
ccd5ca77 KH	76	const struct omap_vp_common_data *vp_common;
	77	u32 vc_cmdval, vp_errgain_val;
	78
ccd5ca77 KH	79	vp_common = vdd->vp_data->vp_common;
	80
	81	/* Check if sufficient pmic info is available for this vdd */
	82	if (!vdd->pmic_info) {
	83	pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
	84	__func__, voltdm->name);
	85	return -EINVAL;
	86	}
	87
	88	if (!vdd->pmic_info->uv_to_vsel) {
	89	pr_err("%s: PMIC function to convert voltage in uV to"
	90	"vsel not registered. Hence unable to scale voltage"
	91	"for vdd_%s\n", __func__, voltdm->name);
	92	return -ENODATA;
	93	}
	94
4bcc475e	95	if (!voltdm->read \|\| !voltdm->write) {
ccd5ca77 KH	96	pr_err("%s: No read/write API for accessing vdd_%s regs\n",
	97	__func__, voltdm->name);
	98	return -EINVAL;
	99	}
	100
	101	/* Get volt_data corresponding to target_volt */
	102	volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
	103	if (IS_ERR(volt_data))
	104	volt_data = NULL;
	105
	106	*target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
4bcc475e	107	*current_vsel = voltdm->read(vdd->vp_data->voltage);
ccd5ca77 KH	108
ccd5ca77 KH	109	/* Setting the ON voltage to the new target voltage */
4bcc475e	110	vc_cmdval = voltdm->read(vc->cmdval_reg);
d84adcf4 KH	111	vc_cmdval &= ~vc->common->cmd_on_mask;
d84adcf4 KH	112	vc_cmdval \|= (*target_vsel << vc->common->cmd_on_shift);
4bcc475e	113	voltdm->write(vc_cmdval, vc->cmdval_reg);
ccd5ca77 KH	114
	115	/* Setting vp errorgain based on the voltage */
	116	if (volt_data) {
4bcc475e	117	vp_errgain_val = voltdm->read(vdd->vp_data->vpconfig);
ccd5ca77 KH	118	vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
	119	vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
	120	vp_errgain_val \|= vdd->vp_rt_data.vpconfig_errorgain <<
	121	vp_common->vpconfig_errorgain_shift;
4bcc475e	122	voltdm->write(vp_errgain_val, vdd->vp_data->vpconfig);
ccd5ca77 KH	123	}
	124
	125	return 0;
	126	}
	127
	128	void omap_vc_post_scale(struct voltagedomain *voltdm,
	129	unsigned long target_volt,
	130	u8 target_vsel, u8 current_vsel)
	131	{
	132	struct omap_vdd_info *vdd = voltdm->vdd;
	133	u32 smps_steps = 0, smps_delay = 0;
	134
	135	smps_steps = abs(target_vsel - current_vsel);
	136	/* SMPS slew rate / step size. 2us added as buffer. */
	137	smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
	138	vdd->pmic_info->slew_rate) + 2;
	139	udelay(smps_delay);
	140
	141	vdd->curr_volt = target_volt;
	142	}
	143
d84adcf4 KH	144	/* vc_bypass_scale - VC bypass method of voltage scaling */
	145	int omap_vc_bypass_scale(struct voltagedomain *voltdm,
	146	unsigned long target_volt)
ccd5ca77	147	{
d84adcf4	148	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77 KH	149	u32 loop_cnt = 0, retries_cnt = 0;
	150	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
	151	u8 target_vsel, current_vsel;
	152	int ret;
	153
	154	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
	155	if (ret)
	156	return ret;
	157
d84adcf4 KH	158	vc_valid = vc->common->valid;
	159	vc_bypass_val_reg = vc->common->bypass_val_reg;
	160	vc_bypass_value = (target_vsel << vc->common->data_shift) \|
78614e0f KH	161	(vc->volt_reg_addr << vc->common->regaddr_shift) \|
78614e0f KH	162	(vc->i2c_slave_addr << vc->common->slaveaddr_shift);
ccd5ca77	163
4bcc475e KH	164	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
4bcc475e KH	165	voltdm->write(vc_bypass_value \| vc_valid, vc_bypass_val_reg);
ccd5ca77	166
4bcc475e	167	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
ccd5ca77 KH	168	/*
	169	* Loop till the bypass command is acknowledged from the SMPS.
	170	* NOTE: This is legacy code. The loop count and retry count needs
	171	* to be revisited.
	172	*/
	173	while (!(vc_bypass_value & vc_valid)) {
	174	loop_cnt++;
	175
	176	if (retries_cnt > 10) {
	177	pr_warning("%s: Retry count exceeded\n", __func__);
	178	return -ETIMEDOUT;
	179	}
	180
	181	if (loop_cnt > 50) {
	182	retries_cnt++;
	183	loop_cnt = 0;
	184	udelay(10);
	185	}
4bcc475e	186	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
ccd5ca77 KH	187	}
	188
	189	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
	190	return 0;
	191	}
	192
	193	static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
	194	{
ccd5ca77 KH	195	/*
	196	* Voltage Manager FSM parameters init
	197	* XXX This data should be passed in from the board file
	198	*/
4bcc475e KH	199	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
	200	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
	201	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
ccd5ca77 KH	202	}
	203
	204	static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
	205	{
ccd5ca77	206	static bool is_initialized;
ccd5ca77 KH	207
	208	if (is_initialized)
	209	return;
	210
ccd5ca77 KH	211	/*
	212	* Generic VC parameters init
	213	* XXX This data should be abstracted out
	214	*/
4bcc475e KH	215	voltdm->write(OMAP3430_MCODE_SHIFT \| OMAP3430_HSEN_MASK,
4bcc475e KH	216	OMAP3_PRM_VC_I2C_CFG_OFFSET);
ccd5ca77 KH	217
	218	omap3_vfsm_init(voltdm);
	219
	220	is_initialized = true;
	221	}
	222
	223
	224	/* OMAP4 specific voltage init functions */
	225	static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
	226	{
ccd5ca77 KH	227	static bool is_initialized;
	228	u32 vc_val;
	229
	230	if (is_initialized)
	231	return;
	232
ccd5ca77 KH	233	/* XXX These are magic numbers and do not belong! */
ccd5ca77 KH	234	vc_val = (0x60 << OMAP4430_SCLL_SHIFT \| 0x26 << OMAP4430_SCLH_SHIFT);
4bcc475e	235	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
ccd5ca77 KH	236
	237	is_initialized = true;
	238	}
	239
	240	void __init omap_vc_init_channel(struct voltagedomain *voltdm)
	241	{
d84adcf4	242	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77	243	struct omap_vdd_info *vdd = voltdm->vdd;
08d1c9a3 KH	244	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
08d1c9a3 KH	245	u32 val;
ccd5ca77 KH	246
	247	if (!vdd->pmic_info \|\| !vdd->pmic_info->uv_to_vsel) {
	248	pr_err("%s: PMIC info requried to configure vc for"
	249	"vdd_%s not populated.Hence cannot initialize vc\n",
	250	__func__, voltdm->name);
	251	return;
	252	}
	253
4bcc475e	254	if (!voltdm->read \|\| !voltdm->write) {
ccd5ca77 KH	255	pr_err("%s: No read/write API for accessing vdd_%s regs\n",
	256	__func__, voltdm->name);
	257	return;
	258	}
	259
24d3194a KH	260	vc->cfg_channel = 0;
24d3194a KH	261
ba112a4e KH	262	/* get PMIC/board specific settings */
ba112a4e KH	263	vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
e4e021c5 KH	264	vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
e4e021c5 KH	265	vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
5892bb1f	266	vc->setup_time = vdd->pmic_info->volt_setup_time;
ba112a4e KH	267
	268	/* Configure the i2c slave address for this VC */
	269	voltdm->rmw(vc->smps_sa_mask,
	270	vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
	271	vc->common->smps_sa_reg);
24d3194a	272	vc->cfg_channel \|= CFG_CHANNEL_SA;
ccd5ca77	273
e4e021c5 KH	274	/*
	275	* Configure the PMIC register addresses.
	276	*/
	277	voltdm->rmw(vc->smps_volra_mask,
	278	vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
	279	vc->common->smps_volra_reg);
24d3194a KH	280	vc->cfg_channel \|= CFG_CHANNEL_RAV;
	281
	282	if (vc->cmd_reg_addr) {
e4e021c5 KH	283	voltdm->rmw(vc->smps_cmdra_mask,
	284	vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
	285	vc->common->smps_cmdra_reg);
24d3194a KH	286	vc->cfg_channel \|= CFG_CHANNEL_RAC \| CFG_CHANNEL_RACEN;
24d3194a KH	287	}
ccd5ca77	288
08d1c9a3 KH	289	/* Set up the on, inactive, retention and off voltage */
	290	on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
	291	onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
	292	ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
	293	off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
	294	val = ((on_vsel << vc->common->cmd_on_shift) \|
	295	(onlp_vsel << vc->common->cmd_onlp_shift) \|
	296	(ret_vsel << vc->common->cmd_ret_shift) \|
	297	(off_vsel << vc->common->cmd_off_shift));
	298	voltdm->write(val, vc->cmdval_reg);
24d3194a KH	299	vc->cfg_channel \|= CFG_CHANNEL_CMD;
	300
	301	/* Channel configuration */
	302	omap_vc_config_channel(voltdm);
08d1c9a3	303
ccd5ca77	304	/* Configure the setup times */
5892bb1f KH	305	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
	306	vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
	307	voltdm->vfsm->voltsetup_reg);
ccd5ca77 KH	308
	309	if (cpu_is_omap34xx())
	310	omap3_vc_init_channel(voltdm);
	311	else if (cpu_is_omap44xx())
	312	omap4_vc_init_channel(voltdm);
	313	}
	314