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ccd5ca77 KH |
1 | /* |
2 | * OMAP Voltage Controller (VC) interface | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
4647ca57 | 13 | #include <linux/bug.h> |
ccd5ca77 | 14 | |
dbc04161 | 15 | #include "soc.h" |
ccd5ca77 KH |
16 | #include "voltage.h" |
17 | #include "vc.h" | |
18 | #include "prm-regbits-34xx.h" | |
19 | #include "prm-regbits-44xx.h" | |
20 | #include "prm44xx.h" | |
21 | ||
8abc0b58 KH |
22 | /** |
23 | * struct omap_vc_channel_cfg - describe the cfg_channel bitfield | |
24 | * @sa: bit for slave address | |
25 | * @rav: bit for voltage configuration register | |
26 | * @rac: bit for command configuration register | |
27 | * @racen: enable bit for RAC | |
28 | * @cmd: bit for command value set selection | |
29 | * | |
30 | * Channel configuration bits, common for OMAP3+ | |
24d3194a KH |
31 | * OMAP3 register: PRM_VC_CH_CONF |
32 | * OMAP4 register: PRM_VC_CFG_CHANNEL | |
8abc0b58 | 33 | * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG |
24d3194a | 34 | */ |
8abc0b58 KH |
35 | struct omap_vc_channel_cfg { |
36 | u8 sa; | |
37 | u8 rav; | |
38 | u8 rac; | |
39 | u8 racen; | |
40 | u8 cmd; | |
41 | }; | |
42 | ||
43 | static struct omap_vc_channel_cfg vc_default_channel_cfg = { | |
44 | .sa = BIT(0), | |
45 | .rav = BIT(1), | |
46 | .rac = BIT(2), | |
47 | .racen = BIT(3), | |
48 | .cmd = BIT(4), | |
49 | }; | |
50 | ||
51 | /* | |
52 | * On OMAP3+, all VC channels have the above default bitfield | |
53 | * configuration, except the OMAP4 MPU channel. This appears | |
54 | * to be a freak accident as every other VC channel has the | |
55 | * default configuration, thus creating a mutant channel config. | |
56 | */ | |
57 | static struct omap_vc_channel_cfg vc_mutant_channel_cfg = { | |
58 | .sa = BIT(0), | |
59 | .rav = BIT(2), | |
60 | .rac = BIT(3), | |
61 | .racen = BIT(4), | |
62 | .cmd = BIT(1), | |
63 | }; | |
64 | ||
65 | static struct omap_vc_channel_cfg *vc_cfg_bits; | |
66 | #define CFG_CHANNEL_MASK 0x1f | |
24d3194a KH |
67 | |
68 | /** | |
69 | * omap_vc_config_channel - configure VC channel to PMIC mappings | |
70 | * @voltdm: pointer to voltagdomain defining the desired VC channel | |
71 | * | |
72 | * Configures the VC channel to PMIC mappings for the following | |
73 | * PMIC settings | |
74 | * - i2c slave address (SA) | |
75 | * - voltage configuration address (RAV) | |
76 | * - command configuration address (RAC) and enable bit (RACEN) | |
77 | * - command values for ON, ONLP, RET and OFF (CMD) | |
78 | * | |
79 | * This function currently only allows flexible configuration of the | |
80 | * non-default channel. Starting with OMAP4, there are more than 2 | |
81 | * channels, with one defined as the default (on OMAP4, it's MPU.) | |
82 | * Only the non-default channel can be configured. | |
83 | */ | |
84 | static int omap_vc_config_channel(struct voltagedomain *voltdm) | |
85 | { | |
86 | struct omap_vc_channel *vc = voltdm->vc; | |
87 | ||
88 | /* | |
89 | * For default channel, the only configurable bit is RACEN. | |
90 | * All others must stay at zero (see function comment above.) | |
91 | */ | |
92 | if (vc->flags & OMAP_VC_CHANNEL_DEFAULT) | |
8abc0b58 | 93 | vc->cfg_channel &= vc_cfg_bits->racen; |
24d3194a KH |
94 | |
95 | voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift, | |
96 | vc->cfg_channel << vc->cfg_channel_sa_shift, | |
5876c940 | 97 | vc->cfg_channel_reg); |
24d3194a KH |
98 | |
99 | return 0; | |
100 | } | |
101 | ||
ccd5ca77 KH |
102 | /* Voltage scale and accessory APIs */ |
103 | int omap_vc_pre_scale(struct voltagedomain *voltdm, | |
104 | unsigned long target_volt, | |
105 | u8 *target_vsel, u8 *current_vsel) | |
106 | { | |
d84adcf4 | 107 | struct omap_vc_channel *vc = voltdm->vc; |
76ea7424 | 108 | u32 vc_cmdval; |
ccd5ca77 | 109 | |
ccd5ca77 | 110 | /* Check if sufficient pmic info is available for this vdd */ |
ce8ebe0d | 111 | if (!voltdm->pmic) { |
ccd5ca77 KH |
112 | pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", |
113 | __func__, voltdm->name); | |
114 | return -EINVAL; | |
115 | } | |
116 | ||
ce8ebe0d | 117 | if (!voltdm->pmic->uv_to_vsel) { |
7852ec05 PW |
118 | pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n", |
119 | __func__, voltdm->name); | |
ccd5ca77 KH |
120 | return -ENODATA; |
121 | } | |
122 | ||
4bcc475e | 123 | if (!voltdm->read || !voltdm->write) { |
ccd5ca77 KH |
124 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", |
125 | __func__, voltdm->name); | |
126 | return -EINVAL; | |
127 | } | |
128 | ||
ce8ebe0d | 129 | *target_vsel = voltdm->pmic->uv_to_vsel(target_volt); |
7590f608 | 130 | *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt); |
ccd5ca77 KH |
131 | |
132 | /* Setting the ON voltage to the new target voltage */ | |
4bcc475e | 133 | vc_cmdval = voltdm->read(vc->cmdval_reg); |
d84adcf4 KH |
134 | vc_cmdval &= ~vc->common->cmd_on_mask; |
135 | vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift); | |
4bcc475e | 136 | voltdm->write(vc_cmdval, vc->cmdval_reg); |
ccd5ca77 | 137 | |
8b5d8c0d TK |
138 | voltdm->vc_param->on = target_volt; |
139 | ||
76ea7424 | 140 | omap_vp_update_errorgain(voltdm, target_volt); |
ccd5ca77 KH |
141 | |
142 | return 0; | |
143 | } | |
144 | ||
145 | void omap_vc_post_scale(struct voltagedomain *voltdm, | |
146 | unsigned long target_volt, | |
147 | u8 target_vsel, u8 current_vsel) | |
148 | { | |
ccd5ca77 KH |
149 | u32 smps_steps = 0, smps_delay = 0; |
150 | ||
151 | smps_steps = abs(target_vsel - current_vsel); | |
152 | /* SMPS slew rate / step size. 2us added as buffer. */ | |
ce8ebe0d KH |
153 | smps_delay = ((smps_steps * voltdm->pmic->step_size) / |
154 | voltdm->pmic->slew_rate) + 2; | |
ccd5ca77 | 155 | udelay(smps_delay); |
ccd5ca77 KH |
156 | } |
157 | ||
d84adcf4 KH |
158 | /* vc_bypass_scale - VC bypass method of voltage scaling */ |
159 | int omap_vc_bypass_scale(struct voltagedomain *voltdm, | |
160 | unsigned long target_volt) | |
ccd5ca77 | 161 | { |
d84adcf4 | 162 | struct omap_vc_channel *vc = voltdm->vc; |
ccd5ca77 KH |
163 | u32 loop_cnt = 0, retries_cnt = 0; |
164 | u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; | |
165 | u8 target_vsel, current_vsel; | |
166 | int ret; | |
167 | ||
168 | ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel); | |
169 | if (ret) | |
170 | return ret; | |
171 | ||
d84adcf4 KH |
172 | vc_valid = vc->common->valid; |
173 | vc_bypass_val_reg = vc->common->bypass_val_reg; | |
174 | vc_bypass_value = (target_vsel << vc->common->data_shift) | | |
78614e0f KH |
175 | (vc->volt_reg_addr << vc->common->regaddr_shift) | |
176 | (vc->i2c_slave_addr << vc->common->slaveaddr_shift); | |
ccd5ca77 | 177 | |
4bcc475e KH |
178 | voltdm->write(vc_bypass_value, vc_bypass_val_reg); |
179 | voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg); | |
ccd5ca77 | 180 | |
4bcc475e | 181 | vc_bypass_value = voltdm->read(vc_bypass_val_reg); |
ccd5ca77 KH |
182 | /* |
183 | * Loop till the bypass command is acknowledged from the SMPS. | |
184 | * NOTE: This is legacy code. The loop count and retry count needs | |
185 | * to be revisited. | |
186 | */ | |
187 | while (!(vc_bypass_value & vc_valid)) { | |
188 | loop_cnt++; | |
189 | ||
190 | if (retries_cnt > 10) { | |
191 | pr_warning("%s: Retry count exceeded\n", __func__); | |
192 | return -ETIMEDOUT; | |
193 | } | |
194 | ||
195 | if (loop_cnt > 50) { | |
196 | retries_cnt++; | |
197 | loop_cnt = 0; | |
198 | udelay(10); | |
199 | } | |
4bcc475e | 200 | vc_bypass_value = voltdm->read(vc_bypass_val_reg); |
ccd5ca77 KH |
201 | } |
202 | ||
203 | omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); | |
204 | return 0; | |
205 | } | |
206 | ||
c589eb38 TK |
207 | /** |
208 | * omap3_set_i2c_timings - sets i2c sleep timings for a channel | |
209 | * @voltdm: channel to configure | |
210 | * @off_mode: select whether retention or off mode values used | |
211 | * | |
212 | * Calculates and sets up voltage controller to use I2C based | |
213 | * voltage scaling for sleep modes. This can be used for either off mode | |
214 | * or retention. Off mode has additionally an option to use sys_off_mode | |
215 | * pad, which uses a global signal to program the whole power IC to | |
216 | * off-mode. | |
217 | */ | |
218 | static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode) | |
ccd5ca77 | 219 | { |
c589eb38 TK |
220 | unsigned long voltsetup1; |
221 | u32 tgt_volt; | |
222 | ||
223 | if (off_mode) | |
224 | tgt_volt = voltdm->vc_param->off; | |
225 | else | |
226 | tgt_volt = voltdm->vc_param->ret; | |
227 | ||
228 | voltsetup1 = (voltdm->vc_param->on - tgt_volt) / | |
229 | voltdm->pmic->slew_rate; | |
230 | ||
231 | voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1; | |
232 | ||
233 | voltdm->rmw(voltdm->vfsm->voltsetup_mask, | |
234 | voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask), | |
235 | voltdm->vfsm->voltsetup_reg); | |
236 | ||
ccd5ca77 | 237 | /* |
c589eb38 TK |
238 | * pmic is not controlling the voltage scaling during retention, |
239 | * thus set voltsetup2 to 0 | |
ccd5ca77 | 240 | */ |
c589eb38 | 241 | voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET); |
ccd5ca77 KH |
242 | } |
243 | ||
c589eb38 TK |
244 | /** |
245 | * omap3_set_off_timings - sets off-mode timings for a channel | |
246 | * @voltdm: channel to configure | |
247 | * | |
248 | * Calculates and sets up off-mode timings for a channel. Off-mode | |
249 | * can use either I2C based voltage scaling, or alternatively | |
250 | * sys_off_mode pad can be used to send a global command to power IC. | |
251 | * This function first checks which mode is being used, and calls | |
252 | * omap3_set_i2c_timings() if the system is using I2C control mode. | |
253 | * sys_off_mode has the additional benefit that voltages can be | |
254 | * scaled to zero volt level with TWL4030 / TWL5030, I2C can only | |
255 | * scale to 600mV. | |
256 | */ | |
257 | static void omap3_set_off_timings(struct voltagedomain *voltdm) | |
ccd5ca77 | 258 | { |
c589eb38 TK |
259 | unsigned long clksetup; |
260 | unsigned long voltsetup2; | |
261 | unsigned long voltsetup2_old; | |
262 | u32 val; | |
ccd5ca77 | 263 | |
c589eb38 TK |
264 | /* check if sys_off_mode is used to control off-mode voltages */ |
265 | val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); | |
266 | if (!(val & OMAP3430_SEL_OFF_MASK)) { | |
267 | /* No, omap is controlling them over I2C */ | |
268 | omap3_set_i2c_timings(voltdm, true); | |
ccd5ca77 | 269 | return; |
c589eb38 | 270 | } |
ccd5ca77 | 271 | |
c589eb38 | 272 | clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET); |
ccd5ca77 | 273 | |
c589eb38 TK |
274 | /* voltsetup 2 in us */ |
275 | voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate; | |
276 | ||
277 | /* convert to 32k clk cycles */ | |
278 | voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000); | |
279 | ||
280 | voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET); | |
281 | ||
282 | /* | |
283 | * Update voltsetup2 if higher than current value (needed because | |
284 | * we have multiple channels with different ramp times), also | |
285 | * update voltoffset always to value recommended by TRM | |
286 | */ | |
287 | if (voltsetup2 > voltsetup2_old) { | |
288 | voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET); | |
289 | voltdm->write(clksetup - voltsetup2, | |
290 | OMAP3_PRM_VOLTOFFSET_OFFSET); | |
291 | } else | |
292 | voltdm->write(clksetup - voltsetup2_old, | |
293 | OMAP3_PRM_VOLTOFFSET_OFFSET); | |
294 | ||
295 | /* | |
296 | * omap is not controlling voltage scaling during off-mode, | |
297 | * thus set voltsetup1 to 0 | |
298 | */ | |
299 | voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0, | |
300 | voltdm->vfsm->voltsetup_reg); | |
301 | ||
302 | /* voltoffset must be clksetup minus voltsetup2 according to TRM */ | |
303 | voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET); | |
ccd5ca77 KH |
304 | } |
305 | ||
c589eb38 TK |
306 | static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) |
307 | { | |
308 | omap3_set_off_timings(voltdm); | |
309 | } | |
ccd5ca77 KH |
310 | |
311 | /* OMAP4 specific voltage init functions */ | |
312 | static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) | |
313 | { | |
ccd5ca77 KH |
314 | static bool is_initialized; |
315 | u32 vc_val; | |
316 | ||
317 | if (is_initialized) | |
318 | return; | |
319 | ||
ccd5ca77 KH |
320 | /* XXX These are magic numbers and do not belong! */ |
321 | vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); | |
4bcc475e | 322 | voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); |
ccd5ca77 KH |
323 | |
324 | is_initialized = true; | |
325 | } | |
326 | ||
f5395480 KH |
327 | /** |
328 | * omap_vc_i2c_init - initialize I2C interface to PMIC | |
329 | * @voltdm: voltage domain containing VC data | |
330 | * | |
2d5b4790 | 331 | * Use PMIC supplied settings for I2C high-speed mode and |
f5395480 KH |
332 | * master code (if set) and program the VC I2C configuration |
333 | * register. | |
334 | * | |
335 | * The VC I2C configuration is common to all VC channels, | |
336 | * so this function only configures I2C for the first VC | |
337 | * channel registers. All other VC channels will use the | |
338 | * same configuration. | |
339 | */ | |
340 | static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) | |
341 | { | |
342 | struct omap_vc_channel *vc = voltdm->vc; | |
343 | static bool initialized; | |
344 | static bool i2c_high_speed; | |
345 | u8 mcode; | |
346 | ||
347 | if (initialized) { | |
348 | if (voltdm->pmic->i2c_high_speed != i2c_high_speed) | |
0bf68f53 RK |
349 | pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).", |
350 | __func__, voltdm->name, i2c_high_speed); | |
f5395480 KH |
351 | return; |
352 | } | |
353 | ||
354 | i2c_high_speed = voltdm->pmic->i2c_high_speed; | |
355 | if (i2c_high_speed) | |
356 | voltdm->rmw(vc->common->i2c_cfg_hsen_mask, | |
357 | vc->common->i2c_cfg_hsen_mask, | |
358 | vc->common->i2c_cfg_reg); | |
359 | ||
360 | mcode = voltdm->pmic->i2c_mcode; | |
361 | if (mcode) | |
362 | voltdm->rmw(vc->common->i2c_mcode_mask, | |
363 | mcode << __ffs(vc->common->i2c_mcode_mask), | |
364 | vc->common->i2c_cfg_reg); | |
365 | ||
366 | initialized = true; | |
367 | } | |
368 | ||
8b5d8c0d TK |
369 | /** |
370 | * omap_vc_calc_vsel - calculate vsel value for a channel | |
371 | * @voltdm: channel to calculate value for | |
372 | * @uvolt: microvolt value to convert to vsel | |
373 | * | |
374 | * Converts a microvolt value to vsel value for the used PMIC. | |
375 | * This checks whether the microvolt value is out of bounds, and | |
376 | * adjusts the value accordingly. If unsupported value detected, | |
377 | * warning is thrown. | |
378 | */ | |
379 | static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt) | |
380 | { | |
381 | if (voltdm->pmic->vddmin > uvolt) | |
382 | uvolt = voltdm->pmic->vddmin; | |
383 | if (voltdm->pmic->vddmax < uvolt) { | |
384 | WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n", | |
385 | __func__, uvolt, voltdm->pmic->vddmax); | |
386 | /* Lets try maximum value anyway */ | |
387 | uvolt = voltdm->pmic->vddmax; | |
388 | } | |
389 | ||
390 | return voltdm->pmic->uv_to_vsel(uvolt); | |
391 | } | |
392 | ||
ccd5ca77 KH |
393 | void __init omap_vc_init_channel(struct voltagedomain *voltdm) |
394 | { | |
d84adcf4 | 395 | struct omap_vc_channel *vc = voltdm->vc; |
08d1c9a3 KH |
396 | u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; |
397 | u32 val; | |
ccd5ca77 | 398 | |
ce8ebe0d | 399 | if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { |
2d5b4790 | 400 | pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); |
ccd5ca77 KH |
401 | return; |
402 | } | |
403 | ||
4bcc475e | 404 | if (!voltdm->read || !voltdm->write) { |
ccd5ca77 KH |
405 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", |
406 | __func__, voltdm->name); | |
407 | return; | |
408 | } | |
409 | ||
24d3194a | 410 | vc->cfg_channel = 0; |
8abc0b58 KH |
411 | if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT) |
412 | vc_cfg_bits = &vc_mutant_channel_cfg; | |
413 | else | |
414 | vc_cfg_bits = &vc_default_channel_cfg; | |
24d3194a | 415 | |
ba112a4e | 416 | /* get PMIC/board specific settings */ |
ce8ebe0d KH |
417 | vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr; |
418 | vc->volt_reg_addr = voltdm->pmic->volt_reg_addr; | |
419 | vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; | |
ba112a4e KH |
420 | |
421 | /* Configure the i2c slave address for this VC */ | |
422 | voltdm->rmw(vc->smps_sa_mask, | |
423 | vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), | |
5876c940 | 424 | vc->smps_sa_reg); |
8abc0b58 | 425 | vc->cfg_channel |= vc_cfg_bits->sa; |
ccd5ca77 | 426 | |
e4e021c5 KH |
427 | /* |
428 | * Configure the PMIC register addresses. | |
429 | */ | |
430 | voltdm->rmw(vc->smps_volra_mask, | |
431 | vc->volt_reg_addr << __ffs(vc->smps_volra_mask), | |
5876c940 | 432 | vc->smps_volra_reg); |
8abc0b58 | 433 | vc->cfg_channel |= vc_cfg_bits->rav; |
24d3194a KH |
434 | |
435 | if (vc->cmd_reg_addr) { | |
e4e021c5 KH |
436 | voltdm->rmw(vc->smps_cmdra_mask, |
437 | vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), | |
5876c940 | 438 | vc->smps_cmdra_reg); |
8abc0b58 | 439 | vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen; |
24d3194a | 440 | } |
ccd5ca77 | 441 | |
08d1c9a3 | 442 | /* Set up the on, inactive, retention and off voltage */ |
8b5d8c0d TK |
443 | on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on); |
444 | onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp); | |
445 | ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret); | |
446 | off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off); | |
447 | ||
08d1c9a3 KH |
448 | val = ((on_vsel << vc->common->cmd_on_shift) | |
449 | (onlp_vsel << vc->common->cmd_onlp_shift) | | |
450 | (ret_vsel << vc->common->cmd_ret_shift) | | |
451 | (off_vsel << vc->common->cmd_off_shift)); | |
452 | voltdm->write(val, vc->cmdval_reg); | |
8abc0b58 | 453 | vc->cfg_channel |= vc_cfg_bits->cmd; |
24d3194a KH |
454 | |
455 | /* Channel configuration */ | |
456 | omap_vc_config_channel(voltdm); | |
08d1c9a3 | 457 | |
f5395480 KH |
458 | omap_vc_i2c_init(voltdm); |
459 | ||
ccd5ca77 KH |
460 | if (cpu_is_omap34xx()) |
461 | omap3_vc_init_channel(voltdm); | |
462 | else if (cpu_is_omap44xx()) | |
463 | omap4_vc_init_channel(voltdm); | |
464 | } | |
465 |