[deliverable/linux.git] / arch / arm / mach-omap2 / vc.c

/*
 * OMAP Voltage Controller (VC) interface
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <plat/cpu.h>

#include "voltage.h"
#include "vc.h"
#include "prm-regbits-34xx.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"

/**
 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
 * @sa: bit for slave address
 * @rav: bit for voltage configuration register
 * @rac: bit for command configuration register
 * @racen: enable bit for RAC
 * @cmd: bit for command value set selection
 *
 * Channel configuration bits, common for OMAP3+
 * OMAP3 register: PRM_VC_CH_CONF
 * OMAP4 register: PRM_VC_CFG_CHANNEL
 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
 */
struct omap_vc_channel_cfg {
	u8 sa;
	u8 rav;
	u8 rac;
	u8 racen;
	u8 cmd;
};

static struct omap_vc_channel_cfg vc_default_channel_cfg = {
	.sa    = BIT(0),
	.rav   = BIT(1),
	.rac   = BIT(2),
	.racen = BIT(3),
	.cmd   = BIT(4),
};

/*
 * On OMAP3+, all VC channels have the above default bitfield
 * configuration, except the OMAP4 MPU channel.  This appears
 * to be a freak accident as every other VC channel has the
 * default configuration, thus creating a mutant channel config.
 */
static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
	.sa    = BIT(0),
	.rav   = BIT(2),
	.rac   = BIT(3),
	.racen = BIT(4),
	.cmd   = BIT(1),
};

static struct omap_vc_channel_cfg *vc_cfg_bits;
#define CFG_CHANNEL_MASK 0x1f

/**
 * omap_vc_config_channel - configure VC channel to PMIC mappings
 * @voltdm: pointer to voltagdomain defining the desired VC channel
 *
 * Configures the VC channel to PMIC mappings for the following
 * PMIC settings
 * - i2c slave address (SA)
 * - voltage configuration address (RAV)
 * - command configuration address (RAC) and enable bit (RACEN)
 * - command values for ON, ONLP, RET and OFF (CMD)
 *
 * This function currently only allows flexible configuration of the
 * non-default channel.  Starting with OMAP4, there are more than 2
 * channels, with one defined as the default (on OMAP4, it's MPU.)
 * Only the non-default channel can be configured.
 */
static int omap_vc_config_channel(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;

	/*
	 * For default channel, the only configurable bit is RACEN.
	 * All others must stay at zero (see function comment above.)
	 */
	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
		vc->cfg_channel &= vc_cfg_bits->racen;

	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
		    vc->cfg_channel << vc->cfg_channel_sa_shift,
		    vc->cfg_channel_reg);

	return 0;
}

/* Voltage scale and accessory APIs */
int omap_vc_pre_scale(struct voltagedomain *voltdm,
		      unsigned long target_volt,
		      u8 *target_vsel, u8 *current_vsel)
{
	struct omap_vc_channel *vc = voltdm->vc;
	u32 vc_cmdval;

	/* Check if sufficient pmic info is available for this vdd */
	if (!voltdm->pmic) {
		pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
			__func__, voltdm->name);
		return -EINVAL;
	}

	if (!voltdm->pmic->uv_to_vsel) {
		pr_err("%s: PMIC function to convert voltage in uV to"
			"vsel not registered. Hence unable to scale voltage"
			"for vdd_%s\n", __func__, voltdm->name);
		return -ENODATA;
	}

	if (!voltdm->read || !voltdm->write) {
		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
			__func__, voltdm->name);
		return -EINVAL;
	}

	*target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
	*current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);

	/* Setting the ON voltage to the new target voltage */
	vc_cmdval = voltdm->read(vc->cmdval_reg);
	vc_cmdval &= ~vc->common->cmd_on_mask;
	vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
	voltdm->write(vc_cmdval, vc->cmdval_reg);

	omap_vp_update_errorgain(voltdm, target_volt);

	return 0;
}

void omap_vc_post_scale(struct voltagedomain *voltdm,
			unsigned long target_volt,
			u8 target_vsel, u8 current_vsel)
{
	u32 smps_steps = 0, smps_delay = 0;

	smps_steps = abs(target_vsel - current_vsel);
	/* SMPS slew rate / step size. 2us added as buffer. */
	smps_delay = ((smps_steps * voltdm->pmic->step_size) /
			voltdm->pmic->slew_rate) + 2;
	udelay(smps_delay);
}

/* vc_bypass_scale - VC bypass method of voltage scaling */
int omap_vc_bypass_scale(struct voltagedomain *voltdm,
			 unsigned long target_volt)
{
	struct omap_vc_channel *vc = voltdm->vc;
	u32 loop_cnt = 0, retries_cnt = 0;
	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
	u8 target_vsel, current_vsel;
	int ret;

	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
	if (ret)
		return ret;

	vc_valid = vc->common->valid;
	vc_bypass_val_reg = vc->common->bypass_val_reg;
	vc_bypass_value = (target_vsel << vc->common->data_shift) |
		(vc->volt_reg_addr << vc->common->regaddr_shift) |
		(vc->i2c_slave_addr << vc->common->slaveaddr_shift);

	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
	voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);

	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
	/*
	 * Loop till the bypass command is acknowledged from the SMPS.
	 * NOTE: This is legacy code. The loop count and retry count needs
	 * to be revisited.
	 */
	while (!(vc_bypass_value & vc_valid)) {
		loop_cnt++;

		if (retries_cnt > 10) {
			pr_warning("%s: Retry count exceeded\n", __func__);
			return -ETIMEDOUT;
		}

		if (loop_cnt > 50) {
			retries_cnt++;
			loop_cnt = 0;
			udelay(10);
		}
		vc_bypass_value = voltdm->read(vc_bypass_val_reg);
	}

	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
	return 0;
}

static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
{
	/*
	 * Voltage Manager FSM parameters init
	 * XXX This data should be passed in from the board file
	 */
	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
}

static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
{
	static bool is_initialized;

	if (is_initialized)
		return;

	omap3_vfsm_init(voltdm);

	is_initialized = true;
}


/* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{
	static bool is_initialized;
	u32 vc_val;

	if (is_initialized)
		return;

	/* XXX These are magic numbers and do not belong! */
	vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);

	is_initialized = true;
}

/**
 * omap_vc_i2c_init - initialize I2C interface to PMIC
 * @voltdm: voltage domain containing VC data
 *
 * Use PMIC supplied settings for I2C high-speed mode and
 * master code (if set) and program the VC I2C configuration
 * register.
 *
 * The VC I2C configuration is common to all VC channels,
 * so this function only configures I2C for the first VC
 * channel registers.  All other VC channels will use the
 * same configuration.
 */
static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;
	static bool initialized;
	static bool i2c_high_speed;
	u8 mcode;

	if (initialized) {
		if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
			pr_warn("%s: I2C config for all channels must match.",
				__func__);
		return;
	}

	i2c_high_speed = voltdm->pmic->i2c_high_speed;
	if (i2c_high_speed)
		voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
			    vc->common->i2c_cfg_hsen_mask,
			    vc->common->i2c_cfg_reg);

	mcode = voltdm->pmic->i2c_mcode;
	if (mcode)
		voltdm->rmw(vc->common->i2c_mcode_mask,
			    mcode << __ffs(vc->common->i2c_mcode_mask),
			    vc->common->i2c_cfg_reg);

	initialized = true;
}

void __init omap_vc_init_channel(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;
	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
	u32 val;

	if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
		pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
		return;
	}

	if (!voltdm->read || !voltdm->write) {
		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
			__func__, voltdm->name);
		return;
	}

	vc->cfg_channel = 0;
	if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
		vc_cfg_bits = &vc_mutant_channel_cfg;
	else
		vc_cfg_bits = &vc_default_channel_cfg;

	/* get PMIC/board specific settings */
	vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
	vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
	vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
	vc->setup_time = voltdm->pmic->volt_setup_time;

	/* Configure the i2c slave address for this VC */
	voltdm->rmw(vc->smps_sa_mask,
		    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
		    vc->smps_sa_reg);
	vc->cfg_channel |= vc_cfg_bits->sa;

	/*
	 * Configure the PMIC register addresses.
	 */
	voltdm->rmw(vc->smps_volra_mask,
		    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
		    vc->smps_volra_reg);
	vc->cfg_channel |= vc_cfg_bits->rav;

	if (vc->cmd_reg_addr) {
		voltdm->rmw(vc->smps_cmdra_mask,
			    vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
			    vc->smps_cmdra_reg);
		vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
	}

	/* Set up the on, inactive, retention and off voltage */
	on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
	onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
	ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
	off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
	val = ((on_vsel << vc->common->cmd_on_shift) |
	       (onlp_vsel << vc->common->cmd_onlp_shift) |
	       (ret_vsel << vc->common->cmd_ret_shift) |
	       (off_vsel << vc->common->cmd_off_shift));
	voltdm->write(val, vc->cmdval_reg);
	vc->cfg_channel |= vc_cfg_bits->cmd;

	/* Channel configuration */
	omap_vc_config_channel(voltdm);

	/* Configure the setup times */
	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
		    vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
		    voltdm->vfsm->voltsetup_reg);

	omap_vc_i2c_init(voltdm);

	if (cpu_is_omap34xx())
		omap3_vc_init_channel(voltdm);
	else if (cpu_is_omap44xx())
		omap4_vc_init_channel(voltdm);
}
Commit	Line	Data
ccd5ca77 KH	1	/*
	2	* OMAP Voltage Controller (VC) interface
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10	#include <linux/kernel.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13
	14	#include <plat/cpu.h>
	15
	16	#include "voltage.h"
	17	#include "vc.h"
	18	#include "prm-regbits-34xx.h"
	19	#include "prm-regbits-44xx.h"
	20	#include "prm44xx.h"
	21
8abc0b58 KH	22	/**
	23	* struct omap_vc_channel_cfg - describe the cfg_channel bitfield
	24	* @sa: bit for slave address
	25	* @rav: bit for voltage configuration register
	26	* @rac: bit for command configuration register
	27	* @racen: enable bit for RAC
	28	* @cmd: bit for command value set selection
	29	*
	30	* Channel configuration bits, common for OMAP3+
24d3194a KH	31	* OMAP3 register: PRM_VC_CH_CONF
24d3194a KH	32	* OMAP4 register: PRM_VC_CFG_CHANNEL
8abc0b58	33	* OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
24d3194a	34	*/
8abc0b58 KH	35	struct omap_vc_channel_cfg {
	36	u8 sa;
	37	u8 rav;
	38	u8 rac;
	39	u8 racen;
	40	u8 cmd;
	41	};
	42
	43	static struct omap_vc_channel_cfg vc_default_channel_cfg = {
	44	.sa = BIT(0),
	45	.rav = BIT(1),
	46	.rac = BIT(2),
	47	.racen = BIT(3),
	48	.cmd = BIT(4),
	49	};
	50
	51	/*
	52	* On OMAP3+, all VC channels have the above default bitfield
	53	* configuration, except the OMAP4 MPU channel. This appears
	54	* to be a freak accident as every other VC channel has the
	55	* default configuration, thus creating a mutant channel config.
	56	*/
	57	static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
	58	.sa = BIT(0),
	59	.rav = BIT(2),
	60	.rac = BIT(3),
	61	.racen = BIT(4),
	62	.cmd = BIT(1),
	63	};
	64
	65	static struct omap_vc_channel_cfg *vc_cfg_bits;
	66	#define CFG_CHANNEL_MASK 0x1f
24d3194a KH	67
	68	/**
	69	* omap_vc_config_channel - configure VC channel to PMIC mappings
	70	* @voltdm: pointer to voltagdomain defining the desired VC channel
	71	*
	72	* Configures the VC channel to PMIC mappings for the following
	73	* PMIC settings
	74	* - i2c slave address (SA)
	75	* - voltage configuration address (RAV)
	76	* - command configuration address (RAC) and enable bit (RACEN)
	77	* - command values for ON, ONLP, RET and OFF (CMD)
	78	*
	79	* This function currently only allows flexible configuration of the
	80	* non-default channel. Starting with OMAP4, there are more than 2
	81	* channels, with one defined as the default (on OMAP4, it's MPU.)
	82	* Only the non-default channel can be configured.
	83	*/
	84	static int omap_vc_config_channel(struct voltagedomain *voltdm)
	85	{
	86	struct omap_vc_channel *vc = voltdm->vc;
	87
	88	/*
	89	* For default channel, the only configurable bit is RACEN.
	90	* All others must stay at zero (see function comment above.)
	91	*/
	92	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
8abc0b58	93	vc->cfg_channel &= vc_cfg_bits->racen;
24d3194a KH	94
	95	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
	96	vc->cfg_channel << vc->cfg_channel_sa_shift,
5876c940	97	vc->cfg_channel_reg);
24d3194a KH	98
	99	return 0;
	100	}
	101
ccd5ca77 KH	102	/* Voltage scale and accessory APIs */
	103	int omap_vc_pre_scale(struct voltagedomain *voltdm,
	104	unsigned long target_volt,
	105	u8 target_vsel, u8 current_vsel)
	106	{
d84adcf4	107	struct omap_vc_channel *vc = voltdm->vc;
76ea7424	108	u32 vc_cmdval;
ccd5ca77	109
ccd5ca77	110	/* Check if sufficient pmic info is available for this vdd */
ce8ebe0d	111	if (!voltdm->pmic) {
ccd5ca77 KH	112	pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
	113	__func__, voltdm->name);
	114	return -EINVAL;
	115	}
	116
ce8ebe0d	117	if (!voltdm->pmic->uv_to_vsel) {
ccd5ca77 KH	118	pr_err("%s: PMIC function to convert voltage in uV to"
	119	"vsel not registered. Hence unable to scale voltage"
	120	"for vdd_%s\n", __func__, voltdm->name);
	121	return -ENODATA;
	122	}
	123
4bcc475e	124	if (!voltdm->read \|\| !voltdm->write) {
ccd5ca77 KH	125	pr_err("%s: No read/write API for accessing vdd_%s regs\n",
	126	__func__, voltdm->name);
	127	return -EINVAL;
	128	}
	129
ce8ebe0d	130	*target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
7590f608	131	*current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
ccd5ca77 KH	132
ccd5ca77 KH	133	/* Setting the ON voltage to the new target voltage */
4bcc475e	134	vc_cmdval = voltdm->read(vc->cmdval_reg);
d84adcf4 KH	135	vc_cmdval &= ~vc->common->cmd_on_mask;
d84adcf4 KH	136	vc_cmdval \|= (*target_vsel << vc->common->cmd_on_shift);
4bcc475e	137	voltdm->write(vc_cmdval, vc->cmdval_reg);
ccd5ca77	138
76ea7424	139	omap_vp_update_errorgain(voltdm, target_volt);
ccd5ca77 KH	140
	141	return 0;
	142	}
	143
	144	void omap_vc_post_scale(struct voltagedomain *voltdm,
	145	unsigned long target_volt,
	146	u8 target_vsel, u8 current_vsel)
	147	{
ccd5ca77 KH	148	u32 smps_steps = 0, smps_delay = 0;
	149
	150	smps_steps = abs(target_vsel - current_vsel);
	151	/* SMPS slew rate / step size. 2us added as buffer. */
ce8ebe0d KH	152	smps_delay = ((smps_steps * voltdm->pmic->step_size) /
ce8ebe0d KH	153	voltdm->pmic->slew_rate) + 2;
ccd5ca77	154	udelay(smps_delay);
ccd5ca77 KH	155	}
ccd5ca77 KH	156
d84adcf4 KH	157	/* vc_bypass_scale - VC bypass method of voltage scaling */
	158	int omap_vc_bypass_scale(struct voltagedomain *voltdm,
	159	unsigned long target_volt)
ccd5ca77	160	{
d84adcf4	161	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77 KH	162	u32 loop_cnt = 0, retries_cnt = 0;
	163	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
	164	u8 target_vsel, current_vsel;
	165	int ret;
	166
	167	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
	168	if (ret)
	169	return ret;
	170
d84adcf4 KH	171	vc_valid = vc->common->valid;
	172	vc_bypass_val_reg = vc->common->bypass_val_reg;
	173	vc_bypass_value = (target_vsel << vc->common->data_shift) \|
78614e0f KH	174	(vc->volt_reg_addr << vc->common->regaddr_shift) \|
78614e0f KH	175	(vc->i2c_slave_addr << vc->common->slaveaddr_shift);
ccd5ca77	176
4bcc475e KH	177	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
4bcc475e KH	178	voltdm->write(vc_bypass_value \| vc_valid, vc_bypass_val_reg);
ccd5ca77	179
4bcc475e	180	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
ccd5ca77 KH	181	/*
	182	* Loop till the bypass command is acknowledged from the SMPS.
	183	* NOTE: This is legacy code. The loop count and retry count needs
	184	* to be revisited.
	185	*/
	186	while (!(vc_bypass_value & vc_valid)) {
	187	loop_cnt++;
	188
	189	if (retries_cnt > 10) {
	190	pr_warning("%s: Retry count exceeded\n", __func__);
	191	return -ETIMEDOUT;
	192	}
	193
	194	if (loop_cnt > 50) {
	195	retries_cnt++;
	196	loop_cnt = 0;
	197	udelay(10);
	198	}
4bcc475e	199	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
ccd5ca77 KH	200	}
	201
	202	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
	203	return 0;
	204	}
	205
	206	static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
	207	{
ccd5ca77 KH	208	/*
	209	* Voltage Manager FSM parameters init
	210	* XXX This data should be passed in from the board file
	211	*/
4bcc475e KH	212	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
	213	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
	214	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
ccd5ca77 KH	215	}
	216
	217	static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
	218	{
ccd5ca77	219	static bool is_initialized;
ccd5ca77 KH	220
	221	if (is_initialized)
	222	return;
	223
ccd5ca77 KH	224	omap3_vfsm_init(voltdm);
	225
	226	is_initialized = true;
	227	}
	228
	229
	230	/* OMAP4 specific voltage init functions */
	231	static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
	232	{
ccd5ca77 KH	233	static bool is_initialized;
	234	u32 vc_val;
	235
	236	if (is_initialized)
	237	return;
	238
ccd5ca77 KH	239	/* XXX These are magic numbers and do not belong! */
ccd5ca77 KH	240	vc_val = (0x60 << OMAP4430_SCLL_SHIFT \| 0x26 << OMAP4430_SCLH_SHIFT);
4bcc475e	241	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
ccd5ca77 KH	242
	243	is_initialized = true;
	244	}
	245
f5395480 KH	246	/**
	247	* omap_vc_i2c_init - initialize I2C interface to PMIC
	248	* @voltdm: voltage domain containing VC data
	249	*
2d5b4790	250	* Use PMIC supplied settings for I2C high-speed mode and
f5395480 KH	251	* master code (if set) and program the VC I2C configuration
	252	* register.
	253	*
	254	* The VC I2C configuration is common to all VC channels,
	255	* so this function only configures I2C for the first VC
	256	* channel registers. All other VC channels will use the
	257	* same configuration.
	258	*/
	259	static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
	260	{
	261	struct omap_vc_channel *vc = voltdm->vc;
	262	static bool initialized;
	263	static bool i2c_high_speed;
	264	u8 mcode;
	265
	266	if (initialized) {
	267	if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
	268	pr_warn("%s: I2C config for all channels must match.",
	269	__func__);
	270	return;
	271	}
	272
	273	i2c_high_speed = voltdm->pmic->i2c_high_speed;
	274	if (i2c_high_speed)
	275	voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
	276	vc->common->i2c_cfg_hsen_mask,
	277	vc->common->i2c_cfg_reg);
	278
	279	mcode = voltdm->pmic->i2c_mcode;
	280	if (mcode)
	281	voltdm->rmw(vc->common->i2c_mcode_mask,
	282	mcode << __ffs(vc->common->i2c_mcode_mask),
	283	vc->common->i2c_cfg_reg);
	284
	285	initialized = true;
	286	}
	287
ccd5ca77 KH	288	void __init omap_vc_init_channel(struct voltagedomain *voltdm)
ccd5ca77 KH	289	{
d84adcf4	290	struct omap_vc_channel *vc = voltdm->vc;
08d1c9a3 KH	291	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
08d1c9a3 KH	292	u32 val;
ccd5ca77	293
ce8ebe0d	294	if (!voltdm->pmic \|\| !voltdm->pmic->uv_to_vsel) {
2d5b4790	295	pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
ccd5ca77 KH	296	return;
	297	}
	298
4bcc475e	299	if (!voltdm->read \|\| !voltdm->write) {
ccd5ca77 KH	300	pr_err("%s: No read/write API for accessing vdd_%s regs\n",
	301	__func__, voltdm->name);
	302	return;
	303	}
	304
24d3194a	305	vc->cfg_channel = 0;
8abc0b58 KH	306	if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
	307	vc_cfg_bits = &vc_mutant_channel_cfg;
	308	else
	309	vc_cfg_bits = &vc_default_channel_cfg;
24d3194a	310
ba112a4e	311	/* get PMIC/board specific settings */
ce8ebe0d KH	312	vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
	313	vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
	314	vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
	315	vc->setup_time = voltdm->pmic->volt_setup_time;
ba112a4e KH	316
	317	/* Configure the i2c slave address for this VC */
	318	voltdm->rmw(vc->smps_sa_mask,
	319	vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
5876c940	320	vc->smps_sa_reg);
8abc0b58	321	vc->cfg_channel \|= vc_cfg_bits->sa;
ccd5ca77	322
e4e021c5 KH	323	/*
	324	* Configure the PMIC register addresses.
	325	*/
	326	voltdm->rmw(vc->smps_volra_mask,
	327	vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
5876c940	328	vc->smps_volra_reg);
8abc0b58	329	vc->cfg_channel \|= vc_cfg_bits->rav;
24d3194a KH	330
24d3194a KH	331	if (vc->cmd_reg_addr) {
e4e021c5 KH	332	voltdm->rmw(vc->smps_cmdra_mask,
e4e021c5 KH	333	vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
5876c940	334	vc->smps_cmdra_reg);
8abc0b58	335	vc->cfg_channel \|= vc_cfg_bits->rac \| vc_cfg_bits->racen;
24d3194a	336	}
ccd5ca77	337
08d1c9a3	338	/* Set up the on, inactive, retention and off voltage */
ce8ebe0d KH	339	on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
	340	onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
	341	ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
	342	off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
08d1c9a3 KH	343	val = ((on_vsel << vc->common->cmd_on_shift) \|
	344	(onlp_vsel << vc->common->cmd_onlp_shift) \|
	345	(ret_vsel << vc->common->cmd_ret_shift) \|
	346	(off_vsel << vc->common->cmd_off_shift));
	347	voltdm->write(val, vc->cmdval_reg);
8abc0b58	348	vc->cfg_channel \|= vc_cfg_bits->cmd;
24d3194a KH	349
	350	/* Channel configuration */
	351	omap_vc_config_channel(voltdm);
08d1c9a3	352
ccd5ca77	353	/* Configure the setup times */
5892bb1f KH	354	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
	355	vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
	356	voltdm->vfsm->voltsetup_reg);
ccd5ca77	357
f5395480 KH	358	omap_vc_i2c_init(voltdm);
f5395480 KH	359
ccd5ca77 KH	360	if (cpu_is_omap34xx())
	361	omap3_vc_init_channel(voltdm);
	362	else if (cpu_is_omap44xx())
	363	omap4_vc_init_channel(voltdm);
	364	}
	365