[deliverable/linux.git] / arch / arm / mach-omap2 / vc.c

/*
 * OMAP Voltage Controller (VC) interface
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>

#include <plat/cpu.h>

#include "voltage.h"
#include "vc.h"
#include "prm-regbits-34xx.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"

/* Voltage scale and accessory APIs */
int omap_vc_pre_scale(struct voltagedomain *voltdm,
		      unsigned long target_volt,
		      u8 *target_vsel, u8 *current_vsel)
{
	struct omap_vc_channel *vc = voltdm->vc;
	struct omap_vdd_info *vdd = voltdm->vdd;
	struct omap_volt_data *volt_data;
	const struct omap_vp_common_data *vp_common;
	u32 vc_cmdval, vp_errgain_val;

	vp_common = vdd->vp_data->vp_common;

	/* Check if sufficient pmic info is available for this vdd */
	if (!vdd->pmic_info) {
		pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
			__func__, voltdm->name);
		return -EINVAL;
	}

	if (!vdd->pmic_info->uv_to_vsel) {
		pr_err("%s: PMIC function to convert voltage in uV to"
			"vsel not registered. Hence unable to scale voltage"
			"for vdd_%s\n", __func__, voltdm->name);
		return -ENODATA;
	}

	if (!voltdm->read || !voltdm->write) {
		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
			__func__, voltdm->name);
		return -EINVAL;
	}

	/* Get volt_data corresponding to target_volt */
	volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
	if (IS_ERR(volt_data))
		volt_data = NULL;

	*target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
	*current_vsel = voltdm->read(vdd->vp_data->voltage);

	/* Setting the ON voltage to the new target voltage */
	vc_cmdval = voltdm->read(vc->cmdval_reg);
	vc_cmdval &= ~vc->common->cmd_on_mask;
	vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
	voltdm->write(vc_cmdval, vc->cmdval_reg);

	/* Setting vp errorgain based on the voltage */
	if (volt_data) {
		vp_errgain_val = voltdm->read(vdd->vp_data->vpconfig);
		vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
		vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
		vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
			vp_common->vpconfig_errorgain_shift;
		voltdm->write(vp_errgain_val, vdd->vp_data->vpconfig);
	}

	return 0;
}

void omap_vc_post_scale(struct voltagedomain *voltdm,
			unsigned long target_volt,
			u8 target_vsel, u8 current_vsel)
{
	struct omap_vdd_info *vdd = voltdm->vdd;
	u32 smps_steps = 0, smps_delay = 0;

	smps_steps = abs(target_vsel - current_vsel);
	/* SMPS slew rate / step size. 2us added as buffer. */
	smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
			vdd->pmic_info->slew_rate) + 2;
	udelay(smps_delay);

	vdd->curr_volt = target_volt;
}

/* vc_bypass_scale - VC bypass method of voltage scaling */
int omap_vc_bypass_scale(struct voltagedomain *voltdm,
			 unsigned long target_volt)
{
	struct omap_vc_channel *vc = voltdm->vc;
	struct omap_vdd_info *vdd = voltdm->vdd;
	u32 loop_cnt = 0, retries_cnt = 0;
	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
	u8 target_vsel, current_vsel;
	int ret;

	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
	if (ret)
		return ret;

	vc_valid = vc->common->valid;
	vc_bypass_val_reg = vc->common->bypass_val_reg;
	vc_bypass_value = (target_vsel << vc->common->data_shift) |
			(vdd->pmic_info->volt_reg_addr <<
			vc->common->regaddr_shift) |
			(vdd->pmic_info->i2c_slave_addr <<
			vc->common->slaveaddr_shift);

	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
	voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);

	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
	/*
	 * Loop till the bypass command is acknowledged from the SMPS.
	 * NOTE: This is legacy code. The loop count and retry count needs
	 * to be revisited.
	 */
	while (!(vc_bypass_value & vc_valid)) {
		loop_cnt++;

		if (retries_cnt > 10) {
			pr_warning("%s: Retry count exceeded\n", __func__);
			return -ETIMEDOUT;
		}

		if (loop_cnt > 50) {
			retries_cnt++;
			loop_cnt = 0;
			udelay(10);
		}
		vc_bypass_value = voltdm->read(vc_bypass_val_reg);
	}

	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
	return 0;
}

static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
{
	/*
	 * Voltage Manager FSM parameters init
	 * XXX This data should be passed in from the board file
	 */
	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
}

static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;
	struct omap_vdd_info *vdd = voltdm->vdd;
	static bool is_initialized;
	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
	u32 vc_val;

	if (is_initialized)
		return;

	/* Set up the on, inactive, retention and off voltage */
	on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
	onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
	ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
	off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
	vc_val	= ((on_vsel << vc->common->cmd_on_shift) |
		(onlp_vsel << vc->common->cmd_onlp_shift) |
		(ret_vsel << vc->common->cmd_ret_shift) |
		(off_vsel << vc->common->cmd_off_shift));
	voltdm->write(vc_val, vc->cmdval_reg);

	/*
	 * Generic VC parameters init
	 * XXX This data should be abstracted out
	 */
	voltdm->write(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK,
		       OMAP3_PRM_VC_CH_CONF_OFFSET);
	voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
		       OMAP3_PRM_VC_I2C_CFG_OFFSET);

	omap3_vfsm_init(voltdm);

	is_initialized = true;
}


/* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{
	static bool is_initialized;
	u32 vc_val;

	if (is_initialized)
		return;

	/* TODO: Configure setup times and CMD_VAL values*/

	/*
	 * Generic VC parameters init
	 * XXX This data should be abstracted out
	 */
	vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
		  OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
		  OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);

	/* XXX These are magic numbers and do not belong! */
	vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);

	is_initialized = true;
}

void __init omap_vc_init_channel(struct voltagedomain *voltdm)
{
	struct omap_vc_channel *vc = voltdm->vc;
	struct omap_vdd_info *vdd = voltdm->vdd;
	u32 vc_val;

	if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
		pr_err("%s: PMIC info requried to configure vc for"
			"vdd_%s not populated.Hence cannot initialize vc\n",
			__func__, voltdm->name);
		return;
	}

	if (!voltdm->read || !voltdm->write) {
		pr_err("%s: No read/write API for accessing vdd_%s regs\n",
			__func__, voltdm->name);
		return;
	}

	/* get PMIC/board specific settings */
	vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
	vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
	vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;

	/* Configure the i2c slave address for this VC */
	voltdm->rmw(vc->smps_sa_mask,
		    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
		    vc->common->smps_sa_reg);

	/*
	 * Configure the PMIC register addresses.
	 */
	voltdm->rmw(vc->smps_volra_mask,
		    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
		    vc->common->smps_volra_reg);
	if (vc->cmd_reg_addr)
		voltdm->rmw(vc->smps_cmdra_mask,
			    vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
			    vc->common->smps_cmdra_reg);

	/* Configure the setup times */
	vc_val = voltdm->read(vdd->vfsm->voltsetup_reg);
	vc_val &= ~vdd->vfsm->voltsetup_mask;
	vc_val |= vdd->pmic_info->volt_setup_time <<
			vdd->vfsm->voltsetup_shift;
	voltdm->write(vc_val, vdd->vfsm->voltsetup_reg);

	if (cpu_is_omap34xx())
		omap3_vc_init_channel(voltdm);
	else if (cpu_is_omap44xx())
		omap4_vc_init_channel(voltdm);
}
Commit	Line	Data
ccd5ca77 KH	1	/*
	2	* OMAP Voltage Controller (VC) interface
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10	#include <linux/kernel.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13
	14	#include <plat/cpu.h>
	15
	16	#include "voltage.h"
	17	#include "vc.h"
	18	#include "prm-regbits-34xx.h"
	19	#include "prm-regbits-44xx.h"
	20	#include "prm44xx.h"
	21
	22	/* Voltage scale and accessory APIs */
	23	int omap_vc_pre_scale(struct voltagedomain *voltdm,
	24	unsigned long target_volt,
	25	u8 target_vsel, u8 current_vsel)
	26	{
d84adcf4	27	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77 KH	28	struct omap_vdd_info *vdd = voltdm->vdd;
ccd5ca77 KH	29	struct omap_volt_data *volt_data;
ccd5ca77 KH	30	const struct omap_vp_common_data *vp_common;
	31	u32 vc_cmdval, vp_errgain_val;
	32
ccd5ca77 KH	33	vp_common = vdd->vp_data->vp_common;
	34
	35	/* Check if sufficient pmic info is available for this vdd */
	36	if (!vdd->pmic_info) {
	37	pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
	38	__func__, voltdm->name);
	39	return -EINVAL;
	40	}
	41
	42	if (!vdd->pmic_info->uv_to_vsel) {
	43	pr_err("%s: PMIC function to convert voltage in uV to"
	44	"vsel not registered. Hence unable to scale voltage"
	45	"for vdd_%s\n", __func__, voltdm->name);
	46	return -ENODATA;
	47	}
	48
4bcc475e	49	if (!voltdm->read \|\| !voltdm->write) {
ccd5ca77 KH	50	pr_err("%s: No read/write API for accessing vdd_%s regs\n",
	51	__func__, voltdm->name);
	52	return -EINVAL;
	53	}
	54
	55	/* Get volt_data corresponding to target_volt */
	56	volt_data = omap_voltage_get_voltdata(voltdm, target_volt);
	57	if (IS_ERR(volt_data))
	58	volt_data = NULL;
	59
	60	*target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
4bcc475e	61	*current_vsel = voltdm->read(vdd->vp_data->voltage);
ccd5ca77 KH	62
ccd5ca77 KH	63	/* Setting the ON voltage to the new target voltage */
4bcc475e	64	vc_cmdval = voltdm->read(vc->cmdval_reg);
d84adcf4 KH	65	vc_cmdval &= ~vc->common->cmd_on_mask;
d84adcf4 KH	66	vc_cmdval \|= (*target_vsel << vc->common->cmd_on_shift);
4bcc475e	67	voltdm->write(vc_cmdval, vc->cmdval_reg);
ccd5ca77 KH	68
	69	/* Setting vp errorgain based on the voltage */
	70	if (volt_data) {
4bcc475e	71	vp_errgain_val = voltdm->read(vdd->vp_data->vpconfig);
ccd5ca77 KH	72	vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
	73	vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
	74	vp_errgain_val \|= vdd->vp_rt_data.vpconfig_errorgain <<
	75	vp_common->vpconfig_errorgain_shift;
4bcc475e	76	voltdm->write(vp_errgain_val, vdd->vp_data->vpconfig);
ccd5ca77 KH	77	}
	78
	79	return 0;
	80	}
	81
	82	void omap_vc_post_scale(struct voltagedomain *voltdm,
	83	unsigned long target_volt,
	84	u8 target_vsel, u8 current_vsel)
	85	{
	86	struct omap_vdd_info *vdd = voltdm->vdd;
	87	u32 smps_steps = 0, smps_delay = 0;
	88
	89	smps_steps = abs(target_vsel - current_vsel);
	90	/* SMPS slew rate / step size. 2us added as buffer. */
	91	smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
	92	vdd->pmic_info->slew_rate) + 2;
	93	udelay(smps_delay);
	94
	95	vdd->curr_volt = target_volt;
	96	}
	97
d84adcf4 KH	98	/* vc_bypass_scale - VC bypass method of voltage scaling */
	99	int omap_vc_bypass_scale(struct voltagedomain *voltdm,
	100	unsigned long target_volt)
ccd5ca77	101	{
d84adcf4	102	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77 KH	103	struct omap_vdd_info *vdd = voltdm->vdd;
	104	u32 loop_cnt = 0, retries_cnt = 0;
	105	u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
	106	u8 target_vsel, current_vsel;
	107	int ret;
	108
	109	ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
	110	if (ret)
	111	return ret;
	112
d84adcf4 KH	113	vc_valid = vc->common->valid;
	114	vc_bypass_val_reg = vc->common->bypass_val_reg;
	115	vc_bypass_value = (target_vsel << vc->common->data_shift) \|
e74e4405	116	(vdd->pmic_info->volt_reg_addr <<
d84adcf4	117	vc->common->regaddr_shift) \|
ccd5ca77	118	(vdd->pmic_info->i2c_slave_addr <<
d84adcf4	119	vc->common->slaveaddr_shift);
ccd5ca77	120
4bcc475e KH	121	voltdm->write(vc_bypass_value, vc_bypass_val_reg);
4bcc475e KH	122	voltdm->write(vc_bypass_value \| vc_valid, vc_bypass_val_reg);
ccd5ca77	123
4bcc475e	124	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
ccd5ca77 KH	125	/*
	126	* Loop till the bypass command is acknowledged from the SMPS.
	127	* NOTE: This is legacy code. The loop count and retry count needs
	128	* to be revisited.
	129	*/
	130	while (!(vc_bypass_value & vc_valid)) {
	131	loop_cnt++;
	132
	133	if (retries_cnt > 10) {
	134	pr_warning("%s: Retry count exceeded\n", __func__);
	135	return -ETIMEDOUT;
	136	}
	137
	138	if (loop_cnt > 50) {
	139	retries_cnt++;
	140	loop_cnt = 0;
	141	udelay(10);
	142	}
4bcc475e	143	vc_bypass_value = voltdm->read(vc_bypass_val_reg);
ccd5ca77 KH	144	}
	145
	146	omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
	147	return 0;
	148	}
	149
	150	static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
	151	{
ccd5ca77 KH	152	/*
	153	* Voltage Manager FSM parameters init
	154	* XXX This data should be passed in from the board file
	155	*/
4bcc475e KH	156	voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
	157	voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
	158	voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
ccd5ca77 KH	159	}
	160
	161	static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
	162	{
d84adcf4	163	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77 KH	164	struct omap_vdd_info *vdd = voltdm->vdd;
	165	static bool is_initialized;
	166	u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
	167	u32 vc_val;
	168
	169	if (is_initialized)
	170	return;
	171
	172	/* Set up the on, inactive, retention and off voltage */
	173	on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
	174	onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
	175	ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
	176	off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
d84adcf4 KH	177	vc_val = ((on_vsel << vc->common->cmd_on_shift) \|
	178	(onlp_vsel << vc->common->cmd_onlp_shift) \|
	179	(ret_vsel << vc->common->cmd_ret_shift) \|
	180	(off_vsel << vc->common->cmd_off_shift));
4bcc475e	181	voltdm->write(vc_val, vc->cmdval_reg);
ccd5ca77 KH	182
	183	/*
	184	* Generic VC parameters init
	185	* XXX This data should be abstracted out
	186	*/
4bcc475e KH	187	voltdm->write(OMAP3430_CMD1_MASK \| OMAP3430_RAV1_MASK,
	188	OMAP3_PRM_VC_CH_CONF_OFFSET);
	189	voltdm->write(OMAP3430_MCODE_SHIFT \| OMAP3430_HSEN_MASK,
	190	OMAP3_PRM_VC_I2C_CFG_OFFSET);
ccd5ca77 KH	191
	192	omap3_vfsm_init(voltdm);
	193
	194	is_initialized = true;
	195	}
	196
	197
	198	/* OMAP4 specific voltage init functions */
	199	static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
	200	{
ccd5ca77 KH	201	static bool is_initialized;
	202	u32 vc_val;
	203
	204	if (is_initialized)
	205	return;
	206
	207	/* TODO: Configure setup times and CMD_VAL values*/
	208
	209	/*
	210	* Generic VC parameters init
	211	* XXX This data should be abstracted out
	212	*/
	213	vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK \| OMAP4430_CMD_VDD_MPU_L_MASK \|
	214	OMAP4430_RAV_VDD_IVA_L_MASK \| OMAP4430_CMD_VDD_IVA_L_MASK \|
	215	OMAP4430_RAV_VDD_CORE_L_MASK \| OMAP4430_CMD_VDD_CORE_L_MASK);
4bcc475e	216	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
ccd5ca77 KH	217
	218	/* XXX These are magic numbers and do not belong! */
	219	vc_val = (0x60 << OMAP4430_SCLL_SHIFT \| 0x26 << OMAP4430_SCLH_SHIFT);
4bcc475e	220	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
ccd5ca77 KH	221
	222	is_initialized = true;
	223	}
	224
	225	void __init omap_vc_init_channel(struct voltagedomain *voltdm)
	226	{
d84adcf4	227	struct omap_vc_channel *vc = voltdm->vc;
ccd5ca77 KH	228	struct omap_vdd_info *vdd = voltdm->vdd;
	229	u32 vc_val;
	230
	231	if (!vdd->pmic_info \|\| !vdd->pmic_info->uv_to_vsel) {
	232	pr_err("%s: PMIC info requried to configure vc for"
	233	"vdd_%s not populated.Hence cannot initialize vc\n",
	234	__func__, voltdm->name);
	235	return;
	236	}
	237
4bcc475e	238	if (!voltdm->read \|\| !voltdm->write) {
ccd5ca77 KH	239	pr_err("%s: No read/write API for accessing vdd_%s regs\n",
	240	__func__, voltdm->name);
	241	return;
	242	}
	243
ba112a4e KH	244	/* get PMIC/board specific settings */
ba112a4e KH	245	vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
e4e021c5 KH	246	vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
e4e021c5 KH	247	vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
ba112a4e KH	248
	249	/* Configure the i2c slave address for this VC */
	250	voltdm->rmw(vc->smps_sa_mask,
	251	vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
	252	vc->common->smps_sa_reg);
ccd5ca77	253
e4e021c5 KH	254	/*
	255	* Configure the PMIC register addresses.
	256	*/
	257	voltdm->rmw(vc->smps_volra_mask,
	258	vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
	259	vc->common->smps_volra_reg);
	260	if (vc->cmd_reg_addr)
	261	voltdm->rmw(vc->smps_cmdra_mask,
	262	vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
	263	vc->common->smps_cmdra_reg);
ccd5ca77 KH	264
ccd5ca77 KH	265	/* Configure the setup times */
4bcc475e	266	vc_val = voltdm->read(vdd->vfsm->voltsetup_reg);
ccd5ca77 KH	267	vc_val &= ~vdd->vfsm->voltsetup_mask;
	268	vc_val \|= vdd->pmic_info->volt_setup_time <<
	269	vdd->vfsm->voltsetup_shift;
4bcc475e	270	voltdm->write(vc_val, vdd->vfsm->voltsetup_reg);
ccd5ca77 KH	271
	272	if (cpu_is_omap34xx())
	273	omap3_vc_init_channel(voltdm);
	274	else if (cpu_is_omap44xx())
	275	omap4_vc_init_channel(voltdm);
	276	}
	277