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c0718df4 PW |
1 | /* |
2 | * OMAP3 Voltage Controller (VC) data | |
3 | * | |
4 | * Copyright (C) 2007, 2010 Texas Instruments, Inc. | |
5 | * Rajendra Nayak <rnayak@ti.com> | |
6 | * Lesly A M <x0080970@ti.com> | |
7 | * Thara Gopinath <thara@ti.com> | |
8 | * | |
9 | * Copyright (C) 2008, 2011 Nokia Corporation | |
10 | * Kalle Jokiniemi | |
11 | * Paul Walmsley | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | #include <linux/io.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/init.h> | |
20 | ||
4e65331c | 21 | #include "common.h" |
c0718df4 PW |
22 | |
23 | #include "prm-regbits-34xx.h" | |
24 | #include "voltage.h" | |
25 | ||
26 | #include "vc.h" | |
27 | ||
28 | /* | |
29 | * VC data common to 34xx/36xx chips | |
30 | * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file. | |
31 | */ | |
d84adcf4 | 32 | static struct omap_vc_common omap3_vc_common = { |
c0718df4 PW |
33 | .bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET, |
34 | .data_shift = OMAP3430_DATA_SHIFT, | |
35 | .slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT, | |
36 | .regaddr_shift = OMAP3430_REGADDR_SHIFT, | |
37 | .valid = OMAP3430_VALID_MASK, | |
38 | .cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT, | |
39 | .cmd_on_mask = OMAP3430_VC_CMD_ON_MASK, | |
40 | .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, | |
41 | .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, | |
42 | .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, | |
f5395480 KH |
43 | .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK, |
44 | .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET, | |
45 | .i2c_mcode_mask = OMAP3430_MCODE_MASK, | |
c0718df4 PW |
46 | }; |
47 | ||
d84adcf4 | 48 | struct omap_vc_channel omap3_vc_mpu = { |
f9d29f16 | 49 | .flags = OMAP_VC_CHANNEL_DEFAULT, |
d84adcf4 | 50 | .common = &omap3_vc_common, |
5876c940 KH |
51 | .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET, |
52 | .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET, | |
53 | .smps_cmdra_reg = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET, | |
54 | .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET, | |
c0718df4 | 55 | .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET, |
c0718df4 | 56 | .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK, |
c0718df4 | 57 | .smps_volra_mask = OMAP3430_VOLRA0_MASK, |
e4e021c5 | 58 | .smps_cmdra_mask = OMAP3430_CMDRA0_MASK, |
24d3194a | 59 | .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT, |
c0718df4 PW |
60 | }; |
61 | ||
d84adcf4 KH |
62 | struct omap_vc_channel omap3_vc_core = { |
63 | .common = &omap3_vc_common, | |
5876c940 KH |
64 | .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET, |
65 | .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET, | |
66 | .smps_cmdra_reg = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET, | |
67 | .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET, | |
c0718df4 | 68 | .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET, |
c0718df4 | 69 | .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK, |
c0718df4 | 70 | .smps_volra_mask = OMAP3430_VOLRA1_MASK, |
e4e021c5 | 71 | .smps_cmdra_mask = OMAP3430_CMDRA1_MASK, |
24d3194a | 72 | .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT, |
c0718df4 | 73 | }; |
8b5d8c0d TK |
74 | |
75 | /* | |
76 | * Voltage levels for different operating modes: on, sleep, retention and off | |
77 | */ | |
78 | #define OMAP3_ON_VOLTAGE_UV 1200000 | |
79 | #define OMAP3_ONLP_VOLTAGE_UV 1000000 | |
80 | #define OMAP3_RET_VOLTAGE_UV 975000 | |
81 | #define OMAP3_OFF_VOLTAGE_UV 600000 | |
82 | ||
83 | struct omap_vc_param omap3_mpu_vc_data = { | |
84 | .on = OMAP3_ON_VOLTAGE_UV, | |
85 | .onlp = OMAP3_ONLP_VOLTAGE_UV, | |
86 | .ret = OMAP3_RET_VOLTAGE_UV, | |
87 | .off = OMAP3_OFF_VOLTAGE_UV, | |
88 | }; | |
89 | ||
90 | struct omap_vc_param omap3_core_vc_data = { | |
91 | .on = OMAP3_ON_VOLTAGE_UV, | |
92 | .onlp = OMAP3_ONLP_VOLTAGE_UV, | |
93 | .ret = OMAP3_RET_VOLTAGE_UV, | |
94 | .off = OMAP3_OFF_VOLTAGE_UV, | |
95 | }; |