[deliverable/linux.git] / arch / arm / mach-orion / pci.c

/*
 * arch/arm/mach-orion/pci.c
 *
 * PCI and PCIe functions for Marvell Orion System On Chip
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <asm/mach/pci.h>
#include <asm/plat-orion/pcie.h>
#include "common.h"

/*****************************************************************************
 * Orion has one PCIe controller and one PCI controller.
 *
 * Note1: The local PCIe bus number is '0'. The local PCI bus number
 * follows the scanned PCIe bridged busses, if any.
 *
 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
 * device bus, Orion registers, etc. However this code only enable the
 * access to DDR banks.
 ****************************************************************************/


/*****************************************************************************
 * PCIe controller
 ****************************************************************************/
#define PCIE_BASE	((void __iomem *)ORION_PCIE_VIRT_BASE)

void __init orion_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_pcie_dev_id(PCIE_BASE);
	*rev = orion_pcie_rev(PCIE_BASE);
}

int orion_pcie_local_bus_nr(void)
{
	return orion_pcie_get_local_bus_nr(PCIE_BASE);
}

static int pcie_valid_config(int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == 0 && dev == 0)
		return 1;

	if (!orion_pcie_link_up(PCIE_BASE))
		return 0;

	if (bus == 0 && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion_pcie_lock);

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&orion_pcie_lock, flags);
	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion_pcie_lock, flags);

	return ret;
}

static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
			   int where, int size, u32 *val)
{
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	/*
	 * We only support access to the non-extended configuration
	 * space when using the WA access method (or we would have to
	 * sacrifice 256M of CPU virtual address space.)
	 */
	if (where >= 0x100) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE,
				    bus, devfn, where, size, val);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&orion_pcie_lock, flags);
	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion_pcie_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};


static int __init pcie_setup(struct pci_sys_data *sys)
{
	struct resource *res;
	int dev;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info);

	/*
	 * Check whether to apply Orion-1/Orion-NAS PCIe config
	 * read transaction workaround.
	 */
	dev = orion_pcie_dev_id(PCIE_BASE);
	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
		printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
				   "read transaction workaround\n");
		pcie_ops.read = pcie_rd_conf_wa;
	}

	/*
	 * Request resources.
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pcie_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCIe I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION_PCIE_IO_BUS_BASE;
	res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCIe IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCIe Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION_PCIE_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCIe Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}

/*****************************************************************************
 * PCI controller
 ****************************************************************************/
#define PCI_MODE		ORION_PCI_REG(0xd00)
#define PCI_CMD			ORION_PCI_REG(0xc00)
#define PCI_P2P_CONF		ORION_PCI_REG(0x1d14)
#define PCI_CONF_ADDR		ORION_PCI_REG(0xc78)
#define PCI_CONF_DATA		ORION_PCI_REG(0xc7c)

/*
 * PCI_MODE bits
 */
#define PCI_MODE_64BIT			(1 << 2)
#define PCI_MODE_PCIX			((1 << 4) | (1 << 5))

/*
 * PCI_CMD bits
 */
#define PCI_CMD_HOST_REORDER		(1 << 29)

/*
 * PCI_P2P_CONF bits
 */
#define PCI_P2P_BUS_OFFS		16
#define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS		24
#define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)

/*
 * PCI_CONF_ADDR bits
 */
#define PCI_CONF_REG(reg)		((reg) & 0xfc)
#define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN		(1 << 31)

/*
 * Internal configuration space
 */
#define PCI_CONF_FUNC_STAT_CMD		0
#define PCI_CONF_REG_STAT_CMD		4
#define PCIX_STAT			0x64
#define PCIX_STAT_BUS_OFFS		8
#define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)

/*
 * PCI Address Decode Windows registers
 */
#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION_PCI_REG(0xc08) : \
				((n) == 1) ? ORION_PCI_REG(0xd08) :  \
				((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
				((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n)	(((n) ==0) ? ORION_PCI_REG(0xc48) :  \
				((n) == 1) ? ORION_PCI_REG(0xd48) :  \
				((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
				((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
#define PCI_BAR_ENABLE		ORION_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL	ORION_PCI_REG(0xd3c)

/*
 * PCI configuration helpers for BAR settings
 */
#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)

/*
 * PCI config cycles are done by programming the PCI_CONF_ADDR register
 * and then reading the PCI_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion_pci_lock);

int orion_pci_local_bus_nr(void)
{
	u32 conf = orion_read(PCI_P2P_CONF);
	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}

static int orion_pci_hw_rd_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 *val)
{
	unsigned long flags;
	spin_lock_irqsave(&orion_pci_lock, flags);

	orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
			PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
			PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);

	*val = orion_read(PCI_CONF_DATA);

	if (size == 1)
		*val = (*val >> (8*(where & 0x3))) & 0xff;
	else if (size == 2)
		*val = (*val >> (8*(where & 0x3))) & 0xffff;

	spin_unlock_irqrestore(&orion_pci_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int orion_pci_hw_wr_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 val)
{
	unsigned long flags;
	int ret = PCIBIOS_SUCCESSFUL;

	spin_lock_irqsave(&orion_pci_lock, flags);

	orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
			PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
			PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);

	if (size == 4) {
		__raw_writel(val, PCI_CONF_DATA);
	} else if (size == 2) {
		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	} else if (size == 1) {
		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	} else {
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

	spin_unlock_irqrestore(&orion_pci_lock, flags);

	return ret;
}

static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 *val)
{
	/*
	 * Don't go out for local device
	 */
	if (bus->number == orion_pci_local_bus_nr() &&
	    PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 val)
{
	if (bus->number == orion_pci_local_bus_nr() &&
	    PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static struct pci_ops pci_ops = {
	.read = orion_pci_rd_conf,
	.write = orion_pci_wr_conf,
};

static void __init orion_pci_set_bus_nr(int nr)
{
	u32 p2p = orion_read(PCI_P2P_CONF);

	if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
		/*
		 * PCI-X mode
		 */
		u32 pcix_status, bus, dev;
		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
		orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
		pcix_status &= ~PCIX_STAT_BUS_MASK;
		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
		orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
	} else {
		/*
		 * PCI Conventional mode
		 */
		p2p &= ~PCI_P2P_BUS_MASK;
		p2p |= (nr << PCI_P2P_BUS_OFFS);
		orion_write(PCI_P2P_CONF, p2p);
	}
}

static void __init orion_pci_master_slave_enable(void)
{
	int bus_nr, func, reg;
	u32 val;

	bus_nr = orion_pci_local_bus_nr();
	func = PCI_CONF_FUNC_STAT_CMD;
	reg = PCI_CONF_REG_STAT_CMD;
	orion_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
	orion_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
}

static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram)
{
	u32 win_enable;
	int bus;
	int i;

	/*
	 * First, disable windows.
	 */
	win_enable = 0xffffffff;
	orion_write(PCI_BAR_ENABLE, win_enable);

	/*
	 * Setup windows for DDR banks.
	 */
	bus = orion_pci_local_bus_nr();

	for (i = 0; i < dram->num_cs; i++) {
		struct mbus_dram_window *cs = dram->cs + i;
		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
		u32 reg;
		u32 val;

		/*
		 * Write DRAM bank base address register.
		 */
		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
		orion_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
		val = (cs->base & 0xfffff000) | (val & 0xfff);
		orion_pci_hw_wr_conf(bus, 0, func, reg, 4, val);

		/*
		 * Write DRAM bank size register.
		 */
		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
		orion_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
		orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
				(cs->size - 1) & 0xfffff000);
		orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
				cs->base & 0xfffff000);

		/*
		 * Enable decode window for this chip select.
		 */
		win_enable &= ~(1 << cs->cs_index);
	}

	/*
	 * Re-enable decode windows.
	 */
	orion_write(PCI_BAR_ENABLE, win_enable);

	/*
	 * Disable automatic update of address remaping when writing to BARs.
	 */
	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
}

static int __init pci_setup(struct pci_sys_data *sys)
{
	struct resource *res;

	/*
	 * Point PCI unit MBUS decode windows to DRAM space.
	 */
	orion_setup_pci_wins(&orion_mbus_dram_info);

	/*
	 * Master + Slave enable
	 */
	orion_pci_master_slave_enable();

	/*
	 * Force ordering
	 */
	orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);

	/*
	 * Request resources
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pci_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCI I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION_PCI_IO_BUS_BASE;
	res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCI IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCI Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION_PCI_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCI Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}


/*****************************************************************************
 * General PCIe + PCI
 ****************************************************************************/
static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;

	if (nr == 0) {
		orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
		ret = pcie_setup(sys);
	} else if (nr == 1) {
		orion_pci_set_bus_nr(sys->busnr);
		ret = pci_setup(sys);
	}

	return ret;
}

struct pci_bus __init *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr == 0) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else if (nr == 1) {
		bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}
Commit	Line	Data
038ee083 TP	1	/*
	2	* arch/arm/mach-orion/pci.c
	3	*
159ffb3a	4	* PCI and PCIe functions for Marvell Orion System On Chip
038ee083 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
038ee083 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
1f2223b1	15	#include <linux/mbus.h>
038ee083	16	#include <asm/mach/pci.h>
abc0197d	17	#include <asm/plat-orion/pcie.h>
038ee083 TP	18	#include "common.h"
	19
	20	/*****************************************************************************
159ffb3a	21	* Orion has one PCIe controller and one PCI controller.
038ee083	22	*
159ffb3a LB	23	* Note1: The local PCIe bus number is '0'. The local PCI bus number
159ffb3a LB	24	* follows the scanned PCIe bridged busses, if any.
038ee083	25	*
159ffb3a	26	* Note2: It is possible for PCI/PCIe agents to access many subsystem's
038ee083 TP	27	* space, by configuring BARs and Address Decode Windows, e.g. flashes on
	28	* device bus, Orion registers, etc. However this code only enable the
	29	* access to DDR banks.
	30	****************************************************************************/
	31
	32
	33	/*****************************************************************************
159ffb3a	34	* PCIe controller
038ee083	35	****************************************************************************/
abc0197d	36	#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE)
038ee083	37
a9984270	38	void __init orion_pcie_id(u32 dev, u32 rev)
038ee083	39	{
abc0197d LB	40	*dev = orion_pcie_dev_id(PCIE_BASE);
abc0197d LB	41	*rev = orion_pcie_rev(PCIE_BASE);
038ee083 TP	42	}
038ee083 TP	43
abc0197d	44	int orion_pcie_local_bus_nr(void)
1f2223b1	45	{
abc0197d	46	return orion_pcie_get_local_bus_nr(PCIE_BASE);
1f2223b1 LB	47	}
1f2223b1 LB	48
abc0197d	49	static int pcie_valid_config(int bus, int dev)
038ee083 TP	50	{
	51	/*
	52	* Don't go out when trying to access --
d50c60a8	53	* 1. nonexisting device on local bus
038ee083	54	* 2. where there's no device connected (no link)
038ee083	55	*/
d50c60a8 LB	56	if (bus == 0 && dev == 0)
d50c60a8 LB	57	return 1;
038ee083	58
abc0197d	59	if (!orion_pcie_link_up(PCIE_BASE))
038ee083 TP	60	return 0;
038ee083 TP	61
d50c60a8 LB	62	if (bus == 0 && dev != 1)
	63	return 0;
	64
038ee083 TP	65	return 1;
	66	}
	67
abc0197d LB	68
abc0197d LB	69	/*
159ffb3a	70	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
abc0197d LB	71	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	72	* transactions are atomic.
	73	*/
	74	static DEFINE_SPINLOCK(orion_pcie_lock);
	75
	76	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	77	int size, u32 *val)
038ee083 TP	78	{
038ee083 TP	79	unsigned long flags;
abc0197d	80	int ret;
038ee083	81
abc0197d	82	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
038ee083 TP	83	*val = 0xffffffff;
	84	return PCIBIOS_DEVICE_NOT_FOUND;
	85	}
	86
	87	spin_lock_irqsave(&orion_pcie_lock, flags);
abc0197d LB	88	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
abc0197d LB	89	spin_unlock_irqrestore(&orion_pcie_lock, flags);
038ee083	90
abc0197d LB	91	return ret;
abc0197d LB	92	}
038ee083	93
abc0197d LB	94	static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
	95	int where, int size, u32 *val)
	96	{
	97	int ret;
038ee083	98
abc0197d LB	99	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
	100	*val = 0xffffffff;
	101	return PCIBIOS_DEVICE_NOT_FOUND;
	102	}
038ee083	103
abc0197d LB	104	/*
	105	* We only support access to the non-extended configuration
	106	* space when using the WA access method (or we would have to
	107	* sacrifice 256M of CPU virtual address space.)
	108	*/
	109	if (where >= 0x100) {
	110	*val = 0xffffffff;
	111	return PCIBIOS_DEVICE_NOT_FOUND;
	112	}
038ee083	113
abc0197d LB	114	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE,
abc0197d LB	115	bus, devfn, where, size, val);
038ee083	116
abc0197d LB	117	return ret;
abc0197d LB	118	}
038ee083	119
abc0197d LB	120	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
abc0197d LB	121	int where, int size, u32 val)
038ee083 TP	122	{
	123	unsigned long flags;
	124	int ret;
	125
abc0197d	126	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
038ee083 TP	127	return PCIBIOS_DEVICE_NOT_FOUND;
	128
	129	spin_lock_irqsave(&orion_pcie_lock, flags);
abc0197d	130	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
038ee083 TP	131	spin_unlock_irqrestore(&orion_pcie_lock, flags);
	132
	133	return ret;
	134	}
	135
159ffb3a	136	static struct pci_ops pcie_ops = {
abc0197d LB	137	.read = pcie_rd_conf,
abc0197d LB	138	.write = pcie_wr_conf,
038ee083 TP	139	};
	140
	141
a9984270	142	static int __init pcie_setup(struct pci_sys_data *sys)
038ee083 TP	143	{
038ee083 TP	144	struct resource *res;
abc0197d	145	int dev;
038ee083	146
1f2223b1	147	/*
abc0197d	148	* Generic PCIe unit setup.
038ee083	149	*/
abc0197d	150	orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info);
038ee083 TP	151
038ee083 TP	152	/*
abc0197d LB	153	* Check whether to apply Orion-1/Orion-NAS PCIe config
abc0197d LB	154	* read transaction workaround.
038ee083	155	*/
abc0197d LB	156	dev = orion_pcie_dev_id(PCIE_BASE);
	157	if (dev == MV88F5181_DEV_ID \|\| dev == MV88F5182_DEV_ID) {
	158	printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
	159	"read transaction workaround\n");
	160	pcie_ops.read = pcie_rd_conf_wa;
	161	}
038ee083 TP	162
038ee083 TP	163	/*
abc0197d	164	* Request resources.
038ee083 TP	165	*/
	166	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	167	if (!res)
abc0197d	168	panic("pcie_setup unable to alloc resources");
038ee083 TP	169
	170	/*
	171	* IORESOURCE_IO
	172	*/
159ffb3a	173	res[0].name = "PCIe I/O Space";
038ee083	174	res[0].flags = IORESOURCE_IO;
7f74c2c7	175	res[0].start = ORION_PCIE_IO_BUS_BASE;
038ee083 TP	176	res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
038ee083 TP	177	if (request_resource(&ioport_resource, &res[0]))
159ffb3a	178	panic("Request PCIe IO resource failed\n");
038ee083 TP	179	sys->resource[0] = &res[0];
	180
	181	/*
	182	* IORESOURCE_MEM
	183	*/
159ffb3a	184	res[1].name = "PCIe Memory Space";
038ee083	185	res[1].flags = IORESOURCE_MEM;
7f74c2c7	186	res[1].start = ORION_PCIE_MEM_PHYS_BASE;
038ee083 TP	187	res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
038ee083 TP	188	if (request_resource(&iomem_resource, &res[1]))
159ffb3a	189	panic("Request PCIe Memory resource failed\n");
038ee083 TP	190	sys->resource[1] = &res[1];
	191
	192	sys->resource[2] = NULL;
	193	sys->io_offset = 0;
	194
	195	return 1;
	196	}
	197
	198	/*****************************************************************************
	199	* PCI controller
	200	****************************************************************************/
	201	#define PCI_MODE ORION_PCI_REG(0xd00)
	202	#define PCI_CMD ORION_PCI_REG(0xc00)
	203	#define PCI_P2P_CONF ORION_PCI_REG(0x1d14)
	204	#define PCI_CONF_ADDR ORION_PCI_REG(0xc78)
	205	#define PCI_CONF_DATA ORION_PCI_REG(0xc7c)
	206
	207	/*
	208	* PCI_MODE bits
	209	*/
	210	#define PCI_MODE_64BIT (1 << 2)
	211	#define PCI_MODE_PCIX ((1 << 4) \| (1 << 5))
	212
	213	/*
	214	* PCI_CMD bits
	215	*/
	216	#define PCI_CMD_HOST_REORDER (1 << 29)
	217
	218	/*
	219	* PCI_P2P_CONF bits
	220	*/
	221	#define PCI_P2P_BUS_OFFS 16
	222	#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
	223	#define PCI_P2P_DEV_OFFS 24
	224	#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
	225
	226	/*
	227	* PCI_CONF_ADDR bits
	228	*/
	229	#define PCI_CONF_REG(reg) ((reg) & 0xfc)
	230	#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
	231	#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
	232	#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
	233	#define PCI_CONF_ADDR_EN (1 << 31)
	234
	235	/*
	236	* Internal configuration space
	237	*/
	238	#define PCI_CONF_FUNC_STAT_CMD 0
	239	#define PCI_CONF_REG_STAT_CMD 4
	240	#define PCIX_STAT 0x64
	241	#define PCIX_STAT_BUS_OFFS 8
	242	#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
	243
1f2223b1 LB	244	/*
	245	* PCI Address Decode Windows registers
	246	*/
	247	#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \
	248	((n) == 1) ? ORION_PCI_REG(0xd08) : \
	249	((n) == 2) ? ORION_PCI_REG(0xc0c) : \
	250	((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
	251	#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
	252	((n) == 1) ? ORION_PCI_REG(0xd48) : \
	253	((n) == 2) ? ORION_PCI_REG(0xc4c) : \
	254	((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
	255	#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c)
	256	#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c)
	257
	258	/*
	259	* PCI configuration helpers for BAR settings
	260	*/
	261	#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
	262	#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
	263	#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
	264
038ee083 TP	265	/*
	266	* PCI config cycles are done by programming the PCI_CONF_ADDR register
	267	* and then reading the PCI_CONF_DATA register. Need to make sure these
	268	* transactions are atomic.
	269	*/
	270	static DEFINE_SPINLOCK(orion_pci_lock);
	271
abc0197d	272	int orion_pci_local_bus_nr(void)
038ee083 TP	273	{
	274	u32 conf = orion_read(PCI_P2P_CONF);
	275	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
	276	}
	277
abc0197d	278	static int orion_pci_hw_rd_conf(int bus, int dev, u32 func,
038ee083 TP	279	u32 where, u32 size, u32 *val)
	280	{
	281	unsigned long flags;
	282	spin_lock_irqsave(&orion_pci_lock, flags);
	283
	284	orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) \|
	285	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	286	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN);
	287
	288	*val = orion_read(PCI_CONF_DATA);
	289
	290	if (size == 1)
	291	val = (val >> (8*(where & 0x3))) & 0xff;
	292	else if (size == 2)
	293	val = (val >> (8*(where & 0x3))) & 0xffff;
	294
	295	spin_unlock_irqrestore(&orion_pci_lock, flags);
	296
	297	return PCIBIOS_SUCCESSFUL;
	298	}
	299
abc0197d	300	static int orion_pci_hw_wr_conf(int bus, int dev, u32 func,
038ee083 TP	301	u32 where, u32 size, u32 val)
	302	{
	303	unsigned long flags;
	304	int ret = PCIBIOS_SUCCESSFUL;
	305
	306	spin_lock_irqsave(&orion_pci_lock, flags);
	307
	308	orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) \|
	309	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	310	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN);
	311
	312	if (size == 4) {
	313	__raw_writel(val, PCI_CONF_DATA);
	314	} else if (size == 2) {
	315	__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	316	} else if (size == 1) {
	317	__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	318	} else {
	319	ret = PCIBIOS_BAD_REGISTER_NUMBER;
	320	}
	321
	322	spin_unlock_irqrestore(&orion_pci_lock, flags);
	323
	324	return ret;
	325	}
	326
	327	static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
	328	int where, int size, u32 *val)
	329	{
	330	/*
	331	* Don't go out for local device
	332	*/
d50c60a8 LB	333	if (bus->number == orion_pci_local_bus_nr() &&
d50c60a8 LB	334	PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
038ee083 TP	335	*val = 0xffffffff;
	336	return PCIBIOS_DEVICE_NOT_FOUND;
	337	}
	338
	339	return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
	340	PCI_FUNC(devfn), where, size, val);
	341	}
	342
	343	static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
	344	int where, int size, u32 val)
	345	{
d50c60a8 LB	346	if (bus->number == orion_pci_local_bus_nr() &&
d50c60a8 LB	347	PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
038ee083 TP	348	return PCIBIOS_DEVICE_NOT_FOUND;
	349
	350	return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
	351	PCI_FUNC(devfn), where, size, val);
	352	}
	353
159ffb3a	354	static struct pci_ops pci_ops = {
038ee083 TP	355	.read = orion_pci_rd_conf,
	356	.write = orion_pci_wr_conf,
	357	};
	358
a9984270	359	static void __init orion_pci_set_bus_nr(int nr)
038ee083 TP	360	{
	361	u32 p2p = orion_read(PCI_P2P_CONF);
	362
	363	if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
	364	/*
	365	* PCI-X mode
	366	*/
	367	u32 pcix_status, bus, dev;
	368	bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
	369	dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
	370	orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
	371	pcix_status &= ~PCIX_STAT_BUS_MASK;
	372	pcix_status \|= (nr << PCIX_STAT_BUS_OFFS);
	373	orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
	374	} else {
	375	/*
	376	* PCI Conventional mode
	377	*/
	378	p2p &= ~PCI_P2P_BUS_MASK;
	379	p2p \|= (nr << PCI_P2P_BUS_OFFS);
	380	orion_write(PCI_P2P_CONF, p2p);
	381	}
	382	}
	383
a9984270	384	static void __init orion_pci_master_slave_enable(void)
038ee083	385	{
d50c60a8	386	int bus_nr, func, reg;
abc0197d	387	u32 val;
038ee083 TP	388
038ee083 TP	389	bus_nr = orion_pci_local_bus_nr();
038ee083 TP	390	func = PCI_CONF_FUNC_STAT_CMD;
038ee083 TP	391	reg = PCI_CONF_REG_STAT_CMD;
d50c60a8	392	orion_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
038ee083	393	val \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
d50c60a8	394	orion_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val \| 0x7);
038ee083 TP	395	}
038ee083 TP	396
a9984270	397	static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram)
1f2223b1 LB	398	{
1f2223b1 LB	399	u32 win_enable;
abc0197d	400	int bus;
1f2223b1 LB	401	int i;
	402
	403	/*
	404	* First, disable windows.
	405	*/
	406	win_enable = 0xffffffff;
	407	orion_write(PCI_BAR_ENABLE, win_enable);
	408
	409	/*
	410	* Setup windows for DDR banks.
	411	*/
	412	bus = orion_pci_local_bus_nr();
1f2223b1 LB	413
	414	for (i = 0; i < dram->num_cs; i++) {
	415	struct mbus_dram_window *cs = dram->cs + i;
	416	u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
	417	u32 reg;
	418	u32 val;
	419
	420	/*
	421	* Write DRAM bank base address register.
	422	*/
	423	reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
d50c60a8	424	orion_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
1f2223b1	425	val = (cs->base & 0xfffff000) \| (val & 0xfff);
d50c60a8	426	orion_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
1f2223b1 LB	427
	428	/*
	429	* Write DRAM bank size register.
	430	*/
	431	reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
d50c60a8	432	orion_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
1f2223b1 LB	433	orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
	434	(cs->size - 1) & 0xfffff000);
	435	orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
	436	cs->base & 0xfffff000);
	437
	438	/*
	439	* Enable decode window for this chip select.
	440	*/
	441	win_enable &= ~(1 << cs->cs_index);
	442	}
	443
	444	/*
	445	* Re-enable decode windows.
	446	*/
	447	orion_write(PCI_BAR_ENABLE, win_enable);
	448
	449	/*
	450	* Disable automatic update of address remaping when writing to BARs.
	451	*/
	452	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
	453	}
	454
a9984270	455	static int __init pci_setup(struct pci_sys_data *sys)
038ee083 TP	456	{
	457	struct resource *res;
	458
1f2223b1 LB	459	/*
	460	* Point PCI unit MBUS decode windows to DRAM space.
	461	*/
	462	orion_setup_pci_wins(&orion_mbus_dram_info);
	463
038ee083 TP	464	/*
	465	* Master + Slave enable
	466	*/
	467	orion_pci_master_slave_enable();
	468
	469	/*
	470	* Force ordering
	471	*/
	472	orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
	473
	474	/*
	475	* Request resources
	476	*/
	477	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	478	if (!res)
abc0197d	479	panic("pci_setup unable to alloc resources");
038ee083 TP	480
	481	/*
	482	* IORESOURCE_IO
	483	*/
	484	res[0].name = "PCI I/O Space";
	485	res[0].flags = IORESOURCE_IO;
7f74c2c7	486	res[0].start = ORION_PCI_IO_BUS_BASE;
038ee083 TP	487	res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
	488	if (request_resource(&ioport_resource, &res[0]))
	489	panic("Request PCI IO resource failed\n");
	490	sys->resource[0] = &res[0];
	491
	492	/*
	493	* IORESOURCE_MEM
	494	*/
	495	res[1].name = "PCI Memory Space";
	496	res[1].flags = IORESOURCE_MEM;
7f74c2c7	497	res[1].start = ORION_PCI_MEM_PHYS_BASE;
038ee083 TP	498	res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
	499	if (request_resource(&iomem_resource, &res[1]))
	500	panic("Request PCI Memory resource failed\n");
	501	sys->resource[1] = &res[1];
	502
	503	sys->resource[2] = NULL;
	504	sys->io_offset = 0;
	505
	506	return 1;
	507	}
	508
	509
	510	/*****************************************************************************
159ffb3a	511	* General PCIe + PCI
038ee083	512	****************************************************************************/
d50c60a8 LB	513	static void __devinit rc_pci_fixup(struct pci_dev *dev)
	514	{
	515	/*
	516	* Prevent enumeration of root complex.
	517	*/
	518	if (dev->bus->parent == NULL && dev->devfn == 0) {
	519	int i;
	520
	521	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	522	dev->resource[i].start = 0;
	523	dev->resource[i].end = 0;
	524	dev->resource[i].flags = 0;
	525	}
	526	}
	527	}
	528	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	529
a9984270	530	int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
038ee083 TP	531	{
	532	int ret = 0;
	533
	534	if (nr == 0) {
abc0197d LB	535	orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
abc0197d LB	536	ret = pcie_setup(sys);
038ee083	537	} else if (nr == 1) {
abc0197d LB	538	orion_pci_set_bus_nr(sys->busnr);
abc0197d LB	539	ret = pci_setup(sys);
038ee083 TP	540	}
	541
	542	return ret;
	543	}
	544
a9984270	545	struct pci_bus __init orion_pci_sys_scan_bus(int nr, struct pci_sys_data sys)
038ee083	546	{
038ee083 TP	547	struct pci_bus *bus;
038ee083 TP	548
038ee083	549	if (nr == 0) {
abc0197d	550	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
038ee083	551	} else if (nr == 1) {
abc0197d	552	bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
038ee083	553	} else {
038ee083	554	bus = NULL;
abc0197d	555	BUG();
038ee083 TP	556	}
	557
	558	return bus;
	559	}