Commit | Line | Data |
---|---|---|
585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 | 15 | #include <linux/platform_device.h> |
ee962723 | 16 | #include <linux/dma-mapping.h> |
ca26f7d3 | 17 | #include <linux/serial_8250.h> |
83b6d822 | 18 | #include <linux/mbus.h> |
144aa3db | 19 | #include <linux/mv643xx_i2c.h> |
15a32632 | 20 | #include <linux/ata_platform.h> |
dcf1cece | 21 | #include <net/dsa.h> |
585cf175 | 22 | #include <asm/page.h> |
be73a347 | 23 | #include <asm/setup.h> |
c67de5b3 | 24 | #include <asm/timex.h> |
be73a347 | 25 | #include <asm/mach/arch.h> |
585cf175 | 26 | #include <asm/mach/map.h> |
2bac1de2 | 27 | #include <asm/mach/time.h> |
4ee1f6b5 | 28 | #include <mach/bridge-regs.h> |
a09e64fb RK |
29 | #include <mach/hardware.h> |
30 | #include <mach/orion5x.h> | |
6f088f1d LB |
31 | #include <plat/orion_nand.h> |
32 | #include <plat/time.h> | |
28a2b450 | 33 | #include <plat/common.h> |
585cf175 TP |
34 | #include "common.h" |
35 | ||
36 | /***************************************************************************** | |
37 | * I/O Address Mapping | |
38 | ****************************************************************************/ | |
9dd0b194 | 39 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 40 | { |
9dd0b194 LB |
41 | .virtual = ORION5X_REGS_VIRT_BASE, |
42 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), | |
43 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 LB |
44 | .type = MT_DEVICE, |
45 | }, { | |
9dd0b194 LB |
46 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
47 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), | |
48 | .length = ORION5X_PCIE_IO_SIZE, | |
e7068ad3 LB |
49 | .type = MT_DEVICE, |
50 | }, { | |
9dd0b194 LB |
51 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
52 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), | |
53 | .length = ORION5X_PCI_IO_SIZE, | |
e7068ad3 LB |
54 | .type = MT_DEVICE, |
55 | }, { | |
9dd0b194 LB |
56 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
57 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), | |
58 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 59 | .type = MT_DEVICE, |
585cf175 TP |
60 | }, |
61 | }; | |
62 | ||
9dd0b194 | 63 | void __init orion5x_map_io(void) |
585cf175 | 64 | { |
9dd0b194 | 65 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 66 | } |
c67de5b3 | 67 | |
044f6c7c | 68 | |
044f6c7c LB |
69 | /***************************************************************************** |
70 | * EHCI0 | |
71 | ****************************************************************************/ | |
044f6c7c LB |
72 | void __init orion5x_ehci0_init(void) |
73 | { | |
4fcd3f37 AL |
74 | orion_ehci_init(&orion5x_mbus_dram_info, |
75 | ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); | |
044f6c7c LB |
76 | } |
77 | ||
78 | ||
79 | /***************************************************************************** | |
80 | * EHCI1 | |
81 | ****************************************************************************/ | |
044f6c7c LB |
82 | void __init orion5x_ehci1_init(void) |
83 | { | |
4fcd3f37 AL |
84 | orion_ehci_1_init(&orion5x_mbus_dram_info, |
85 | ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); | |
044f6c7c LB |
86 | } |
87 | ||
88 | ||
e07c9d85 | 89 | /***************************************************************************** |
5c602551 | 90 | * GE00 |
e07c9d85 | 91 | ****************************************************************************/ |
9dd0b194 | 92 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 93 | { |
7e3819d8 AL |
94 | orion_ge00_init(eth_data, &orion5x_mbus_dram_info, |
95 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, | |
96 | IRQ_ORION5X_ETH_ERR, orion5x_tclk); | |
e07c9d85 TP |
97 | } |
98 | ||
044f6c7c | 99 | |
dcf1cece LB |
100 | /***************************************************************************** |
101 | * Ethernet switch | |
102 | ****************************************************************************/ | |
dcf1cece LB |
103 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) |
104 | { | |
7e3819d8 | 105 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
106 | } |
107 | ||
108 | ||
144aa3db | 109 | /***************************************************************************** |
044f6c7c | 110 | * I2C |
144aa3db | 111 | ****************************************************************************/ |
044f6c7c LB |
112 | void __init orion5x_i2c_init(void) |
113 | { | |
aac7ffa3 AL |
114 | orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); |
115 | ||
044f6c7c LB |
116 | } |
117 | ||
118 | ||
f244baa3 | 119 | /***************************************************************************** |
044f6c7c | 120 | * SATA |
f244baa3 | 121 | ****************************************************************************/ |
9dd0b194 | 122 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 123 | { |
9e613f8a AL |
124 | orion_sata_init(sata_data, &orion5x_mbus_dram_info, |
125 | ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); | |
f244baa3 SB |
126 | } |
127 | ||
044f6c7c | 128 | |
d323ade1 LB |
129 | /***************************************************************************** |
130 | * SPI | |
131 | ****************************************************************************/ | |
d323ade1 LB |
132 | void __init orion5x_spi_init() |
133 | { | |
980f9f60 | 134 | orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); |
d323ade1 LB |
135 | } |
136 | ||
137 | ||
2bac1de2 | 138 | /***************************************************************************** |
044f6c7c LB |
139 | * UART0 |
140 | ****************************************************************************/ | |
044f6c7c LB |
141 | void __init orion5x_uart0_init(void) |
142 | { | |
28a2b450 AL |
143 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
144 | IRQ_ORION5X_UART0, orion5x_tclk); | |
044f6c7c LB |
145 | } |
146 | ||
044f6c7c LB |
147 | /***************************************************************************** |
148 | * UART1 | |
2bac1de2 | 149 | ****************************************************************************/ |
044f6c7c LB |
150 | void __init orion5x_uart1_init(void) |
151 | { | |
28a2b450 AL |
152 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
153 | IRQ_ORION5X_UART1, orion5x_tclk); | |
044f6c7c | 154 | } |
2bac1de2 | 155 | |
1d5a1a6e SB |
156 | /***************************************************************************** |
157 | * XOR engine | |
158 | ****************************************************************************/ | |
1d5a1a6e SB |
159 | void __init orion5x_xor_init(void) |
160 | { | |
ee962723 AL |
161 | orion_xor0_init(&orion5x_mbus_dram_info, |
162 | ORION5X_XOR_PHYS_BASE, | |
163 | ORION5X_XOR_PHYS_BASE + 0x200, | |
164 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); | |
1d5a1a6e SB |
165 | } |
166 | ||
44350061 AL |
167 | /***************************************************************************** |
168 | * Cryptographic Engines and Security Accelerator (CESA) | |
169 | ****************************************************************************/ | |
170 | static void __init orion5x_crypto_init(void) | |
3a8f7441 SAS |
171 | { |
172 | int ret; | |
173 | ||
174 | ret = orion5x_setup_sram_win(); | |
175 | if (ret) | |
44350061 | 176 | return; |
3a8f7441 | 177 | |
44350061 AL |
178 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
179 | SZ_8K, IRQ_ORION5X_CESA); | |
3a8f7441 | 180 | } |
1d5a1a6e | 181 | |
9e058d4f TR |
182 | /***************************************************************************** |
183 | * Watchdog | |
184 | ****************************************************************************/ | |
9e058d4f TR |
185 | void __init orion5x_wdt_init(void) |
186 | { | |
5e00d378 | 187 | orion_wdt_init(orion5x_tclk); |
9e058d4f TR |
188 | } |
189 | ||
190 | ||
044f6c7c LB |
191 | /***************************************************************************** |
192 | * Time handling | |
193 | ****************************************************************************/ | |
4ee1f6b5 LB |
194 | void __init orion5x_init_early(void) |
195 | { | |
196 | orion_time_set_base(TIMER_VIRT_BASE); | |
197 | } | |
198 | ||
ebe35aff LB |
199 | int orion5x_tclk; |
200 | ||
201 | int __init orion5x_find_tclk(void) | |
202 | { | |
d323ade1 LB |
203 | u32 dev, rev; |
204 | ||
205 | orion5x_pcie_id(&dev, &rev); | |
206 | if (dev == MV88F6183_DEV_ID && | |
207 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
208 | return 133333333; | |
209 | ||
ebe35aff LB |
210 | return 166666667; |
211 | } | |
212 | ||
9dd0b194 | 213 | static void orion5x_timer_init(void) |
2bac1de2 | 214 | { |
ebe35aff | 215 | orion5x_tclk = orion5x_find_tclk(); |
4ee1f6b5 LB |
216 | |
217 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
218 | IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
219 | } |
220 | ||
9dd0b194 | 221 | struct sys_timer orion5x_timer = { |
e7068ad3 | 222 | .init = orion5x_timer_init, |
2bac1de2 LB |
223 | }; |
224 | ||
044f6c7c | 225 | |
c67de5b3 TP |
226 | /***************************************************************************** |
227 | * General | |
228 | ****************************************************************************/ | |
c67de5b3 | 229 | /* |
b46926bb | 230 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 231 | */ |
9dd0b194 | 232 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 233 | { |
9dd0b194 | 234 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
235 | |
236 | if (*dev == MV88F5281_DEV_ID) { | |
237 | if (*rev == MV88F5281_REV_D2) { | |
238 | *dev_name = "MV88F5281-D2"; | |
239 | } else if (*rev == MV88F5281_REV_D1) { | |
240 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
241 | } else if (*rev == MV88F5281_REV_D0) { |
242 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
243 | } else { |
244 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
245 | } | |
246 | } else if (*dev == MV88F5182_DEV_ID) { | |
247 | if (*rev == MV88F5182_REV_A2) { | |
248 | *dev_name = "MV88F5182-A2"; | |
249 | } else { | |
250 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
251 | } | |
c9e3de94 HVR |
252 | } else if (*dev == MV88F5181_DEV_ID) { |
253 | if (*rev == MV88F5181_REV_B1) { | |
254 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
255 | } else if (*rev == MV88F5181L_REV_A1) { |
256 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 257 | } else { |
d2b2a6bb | 258 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 259 | } |
d323ade1 LB |
260 | } else if (*dev == MV88F6183_DEV_ID) { |
261 | if (*rev == MV88F6183_REV_B0) { | |
262 | *dev_name = "MV88F6183-Rev-B0"; | |
263 | } else { | |
264 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
265 | } | |
c67de5b3 TP |
266 | } else { |
267 | *dev_name = "Device-Unknown"; | |
268 | } | |
269 | } | |
270 | ||
9dd0b194 | 271 | void __init orion5x_init(void) |
c67de5b3 TP |
272 | { |
273 | char *dev_name; | |
274 | u32 dev, rev; | |
275 | ||
9dd0b194 | 276 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
277 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
278 | ||
c67de5b3 TP |
279 | /* |
280 | * Setup Orion address map | |
281 | */ | |
9dd0b194 | 282 | orion5x_setup_cpu_mbus_bridge(); |
ce72e36e LB |
283 | |
284 | /* | |
285 | * Don't issue "Wait for Interrupt" instruction if we are | |
286 | * running on D0 5281 silicon. | |
287 | */ | |
288 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
289 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
290 | disable_hlt(); | |
291 | } | |
9e058d4f | 292 | |
3fade49b NP |
293 | /* |
294 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | |
295 | * while 5180n/5181/5281 don't have crypto. | |
296 | */ | |
297 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | |
298 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | |
299 | orion5x_crypto_init(); | |
300 | ||
9e058d4f TR |
301 | /* |
302 | * Register watchdog driver | |
303 | */ | |
304 | orion5x_wdt_init(); | |
c67de5b3 | 305 | } |
be73a347 GL |
306 | |
307 | /* | |
308 | * Many orion-based systems have buggy bootloader implementations. | |
309 | * This is a common fixup for bogus memory tags. | |
310 | */ | |
0744a3ee RK |
311 | void __init tag_fixup_mem32(struct tag *t, char **from, |
312 | struct meminfo *meminfo) | |
be73a347 GL |
313 | { |
314 | for (; t->hdr.size; t = tag_next(t)) | |
315 | if (t->hdr.tag == ATAG_MEM && | |
316 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
317 | t->u.mem.start & ~PAGE_MASK)) { | |
318 | printk(KERN_WARNING | |
319 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
320 | t->u.mem.size / 1024, t->u.mem.start); | |
321 | t->hdr.tag = 0; | |
322 | } | |
323 | } |