Commit | Line | Data |
---|---|---|
585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 | 15 | #include <linux/platform_device.h> |
ee962723 | 16 | #include <linux/dma-mapping.h> |
ca26f7d3 | 17 | #include <linux/serial_8250.h> |
144aa3db | 18 | #include <linux/mv643xx_i2c.h> |
15a32632 | 19 | #include <linux/ata_platform.h> |
764cbcc2 | 20 | #include <linux/delay.h> |
2f129bf4 | 21 | #include <linux/clk-provider.h> |
7b2fea1c | 22 | #include <linux/cpu.h> |
dcf1cece | 23 | #include <net/dsa.h> |
585cf175 | 24 | #include <asm/page.h> |
be73a347 | 25 | #include <asm/setup.h> |
9f97da78 | 26 | #include <asm/system_misc.h> |
be73a347 | 27 | #include <asm/mach/arch.h> |
585cf175 | 28 | #include <asm/mach/map.h> |
2bac1de2 | 29 | #include <asm/mach/time.h> |
c02cecb9 AB |
30 | #include <linux/platform_data/mtd-orion_nand.h> |
31 | #include <linux/platform_data/usb-ehci-orion.h> | |
6f088f1d | 32 | #include <plat/time.h> |
28a2b450 | 33 | #include <plat/common.h> |
c22c2c60 AB |
34 | |
35 | #include "bridge-regs.h" | |
585cf175 | 36 | #include "common.h" |
c22c2c60 | 37 | #include "orion5x.h" |
585cf175 TP |
38 | |
39 | /***************************************************************************** | |
40 | * I/O Address Mapping | |
41 | ****************************************************************************/ | |
9dd0b194 | 42 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 43 | { |
3904a393 | 44 | .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, |
9dd0b194 LB |
45 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), |
46 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 | 47 | .type = MT_DEVICE, |
e7068ad3 | 48 | }, { |
3904a393 | 49 | .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, |
9dd0b194 LB |
50 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), |
51 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 52 | .type = MT_DEVICE, |
585cf175 TP |
53 | }, |
54 | }; | |
55 | ||
9dd0b194 | 56 | void __init orion5x_map_io(void) |
585cf175 | 57 | { |
9dd0b194 | 58 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 59 | } |
c67de5b3 | 60 | |
044f6c7c | 61 | |
2f129bf4 AL |
62 | /***************************************************************************** |
63 | * CLK tree | |
64 | ****************************************************************************/ | |
65 | static struct clk *tclk; | |
66 | ||
1bffb4a8 | 67 | void __init clk_init(void) |
2f129bf4 AL |
68 | { |
69 | tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, | |
70 | orion5x_tclk); | |
4574b886 AL |
71 | |
72 | orion_clkdev_init(tclk); | |
2f129bf4 AL |
73 | } |
74 | ||
044f6c7c LB |
75 | /***************************************************************************** |
76 | * EHCI0 | |
77 | ****************************************************************************/ | |
044f6c7c LB |
78 | void __init orion5x_ehci0_init(void) |
79 | { | |
72053353 AL |
80 | orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, |
81 | EHCI_PHY_ORION); | |
044f6c7c LB |
82 | } |
83 | ||
84 | ||
85 | /***************************************************************************** | |
86 | * EHCI1 | |
87 | ****************************************************************************/ | |
044f6c7c LB |
88 | void __init orion5x_ehci1_init(void) |
89 | { | |
db33f4de | 90 | orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); |
044f6c7c LB |
91 | } |
92 | ||
93 | ||
e07c9d85 | 94 | /***************************************************************************** |
5c602551 | 95 | * GE00 |
e07c9d85 | 96 | ****************************************************************************/ |
9dd0b194 | 97 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 98 | { |
db33f4de | 99 | orion_ge00_init(eth_data, |
7e3819d8 | 100 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, |
58569aee APR |
101 | IRQ_ORION5X_ETH_ERR, |
102 | MV643XX_TX_CSUM_DEFAULT_LIMIT); | |
e07c9d85 TP |
103 | } |
104 | ||
044f6c7c | 105 | |
dcf1cece LB |
106 | /***************************************************************************** |
107 | * Ethernet switch | |
108 | ****************************************************************************/ | |
dcf1cece LB |
109 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) |
110 | { | |
7e3819d8 | 111 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
112 | } |
113 | ||
114 | ||
144aa3db | 115 | /***************************************************************************** |
044f6c7c | 116 | * I2C |
144aa3db | 117 | ****************************************************************************/ |
044f6c7c LB |
118 | void __init orion5x_i2c_init(void) |
119 | { | |
aac7ffa3 AL |
120 | orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); |
121 | ||
044f6c7c LB |
122 | } |
123 | ||
124 | ||
f244baa3 | 125 | /***************************************************************************** |
044f6c7c | 126 | * SATA |
f244baa3 | 127 | ****************************************************************************/ |
9dd0b194 | 128 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 129 | { |
db33f4de | 130 | orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); |
f244baa3 SB |
131 | } |
132 | ||
044f6c7c | 133 | |
d323ade1 LB |
134 | /***************************************************************************** |
135 | * SPI | |
136 | ****************************************************************************/ | |
42366666 | 137 | void __init orion5x_spi_init(void) |
d323ade1 | 138 | { |
4574b886 | 139 | orion_spi_init(SPI_PHYS_BASE); |
d323ade1 LB |
140 | } |
141 | ||
142 | ||
2bac1de2 | 143 | /***************************************************************************** |
044f6c7c LB |
144 | * UART0 |
145 | ****************************************************************************/ | |
044f6c7c LB |
146 | void __init orion5x_uart0_init(void) |
147 | { | |
28a2b450 | 148 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
74c33576 | 149 | IRQ_ORION5X_UART0, tclk); |
044f6c7c LB |
150 | } |
151 | ||
044f6c7c LB |
152 | /***************************************************************************** |
153 | * UART1 | |
2bac1de2 | 154 | ****************************************************************************/ |
044f6c7c LB |
155 | void __init orion5x_uart1_init(void) |
156 | { | |
28a2b450 | 157 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
74c33576 | 158 | IRQ_ORION5X_UART1, tclk); |
044f6c7c | 159 | } |
2bac1de2 | 160 | |
1d5a1a6e SB |
161 | /***************************************************************************** |
162 | * XOR engine | |
163 | ****************************************************************************/ | |
1d5a1a6e SB |
164 | void __init orion5x_xor_init(void) |
165 | { | |
db33f4de | 166 | orion_xor0_init(ORION5X_XOR_PHYS_BASE, |
ee962723 AL |
167 | ORION5X_XOR_PHYS_BASE + 0x200, |
168 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); | |
1d5a1a6e SB |
169 | } |
170 | ||
44350061 AL |
171 | /***************************************************************************** |
172 | * Cryptographic Engines and Security Accelerator (CESA) | |
173 | ****************************************************************************/ | |
174 | static void __init orion5x_crypto_init(void) | |
3a8f7441 | 175 | { |
4ca2c040 TP |
176 | mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, |
177 | ORION_MBUS_SRAM_ATTR, | |
178 | ORION5X_SRAM_PHYS_BASE, | |
179 | ORION5X_SRAM_SIZE); | |
44350061 AL |
180 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
181 | SZ_8K, IRQ_ORION5X_CESA); | |
3a8f7441 | 182 | } |
1d5a1a6e | 183 | |
9e058d4f TR |
184 | /***************************************************************************** |
185 | * Watchdog | |
186 | ****************************************************************************/ | |
06f3008a AB |
187 | static struct resource orion_wdt_resource[] = { |
188 | DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), | |
189 | DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), | |
190 | }; | |
191 | ||
192 | static struct platform_device orion_wdt_device = { | |
193 | .name = "orion_wdt", | |
194 | .id = -1, | |
195 | .num_resources = ARRAY_SIZE(orion_wdt_resource), | |
196 | .resource = orion_wdt_resource, | |
197 | }; | |
198 | ||
42366666 | 199 | static void __init orion5x_wdt_init(void) |
9e058d4f | 200 | { |
06f3008a | 201 | platform_device_register(&orion_wdt_device); |
9e058d4f TR |
202 | } |
203 | ||
204 | ||
044f6c7c LB |
205 | /***************************************************************************** |
206 | * Time handling | |
207 | ****************************************************************************/ | |
4ee1f6b5 LB |
208 | void __init orion5x_init_early(void) |
209 | { | |
5d1190ea TP |
210 | u32 rev, dev; |
211 | const char *mbus_soc_name; | |
212 | ||
4ee1f6b5 | 213 | orion_time_set_base(TIMER_VIRT_BASE); |
84d5dfbf | 214 | |
5d1190ea TP |
215 | /* Initialize the MBUS driver */ |
216 | orion5x_pcie_id(&dev, &rev); | |
217 | if (dev == MV88F5281_DEV_ID) | |
218 | mbus_soc_name = "marvell,orion5x-88f5281-mbus"; | |
219 | else if (dev == MV88F5182_DEV_ID) | |
220 | mbus_soc_name = "marvell,orion5x-88f5182-mbus"; | |
221 | else if (dev == MV88F5181_DEV_ID) | |
222 | mbus_soc_name = "marvell,orion5x-88f5181-mbus"; | |
223 | else if (dev == MV88F6183_DEV_ID) | |
224 | mbus_soc_name = "marvell,orion5x-88f6183-mbus"; | |
225 | else | |
226 | mbus_soc_name = NULL; | |
227 | mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, | |
228 | ORION5X_BRIDGE_WINS_SZ, | |
229 | ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); | |
230 | } | |
231 | ||
232 | void orion5x_setup_wins(void) | |
233 | { | |
234 | /* | |
235 | * The PCIe windows will no longer be statically allocated | |
236 | * here once Orion5x is migrated to the pci-mvebu driver. | |
237 | */ | |
4ca2c040 TP |
238 | mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, |
239 | ORION_MBUS_PCIE_IO_ATTR, | |
240 | ORION5X_PCIE_IO_PHYS_BASE, | |
5d1190ea | 241 | ORION5X_PCIE_IO_SIZE, |
4ca2c040 TP |
242 | ORION5X_PCIE_IO_BUS_BASE); |
243 | mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, | |
244 | ORION_MBUS_PCIE_MEM_ATTR, | |
245 | ORION5X_PCIE_MEM_PHYS_BASE, | |
246 | ORION5X_PCIE_MEM_SIZE); | |
247 | mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, | |
248 | ORION_MBUS_PCI_IO_ATTR, | |
249 | ORION5X_PCI_IO_PHYS_BASE, | |
5d1190ea | 250 | ORION5X_PCI_IO_SIZE, |
4ca2c040 TP |
251 | ORION5X_PCI_IO_BUS_BASE); |
252 | mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, | |
253 | ORION_MBUS_PCI_MEM_ATTR, | |
254 | ORION5X_PCI_MEM_PHYS_BASE, | |
255 | ORION5X_PCI_MEM_SIZE); | |
4ee1f6b5 LB |
256 | } |
257 | ||
ebe35aff LB |
258 | int orion5x_tclk; |
259 | ||
42366666 | 260 | static int __init orion5x_find_tclk(void) |
ebe35aff | 261 | { |
d323ade1 LB |
262 | u32 dev, rev; |
263 | ||
264 | orion5x_pcie_id(&dev, &rev); | |
265 | if (dev == MV88F6183_DEV_ID && | |
266 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
267 | return 133333333; | |
268 | ||
ebe35aff LB |
269 | return 166666667; |
270 | } | |
271 | ||
6bb27d73 | 272 | void __init orion5x_timer_init(void) |
2bac1de2 | 273 | { |
ebe35aff | 274 | orion5x_tclk = orion5x_find_tclk(); |
4ee1f6b5 LB |
275 | |
276 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
277 | IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
278 | } |
279 | ||
044f6c7c | 280 | |
c67de5b3 TP |
281 | /***************************************************************************** |
282 | * General | |
283 | ****************************************************************************/ | |
c67de5b3 | 284 | /* |
b46926bb | 285 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 286 | */ |
1bffb4a8 | 287 | void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 288 | { |
9dd0b194 | 289 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
290 | |
291 | if (*dev == MV88F5281_DEV_ID) { | |
292 | if (*rev == MV88F5281_REV_D2) { | |
293 | *dev_name = "MV88F5281-D2"; | |
294 | } else if (*rev == MV88F5281_REV_D1) { | |
295 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
296 | } else if (*rev == MV88F5281_REV_D0) { |
297 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
298 | } else { |
299 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
300 | } | |
301 | } else if (*dev == MV88F5182_DEV_ID) { | |
302 | if (*rev == MV88F5182_REV_A2) { | |
303 | *dev_name = "MV88F5182-A2"; | |
304 | } else { | |
305 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
306 | } | |
c9e3de94 HVR |
307 | } else if (*dev == MV88F5181_DEV_ID) { |
308 | if (*rev == MV88F5181_REV_B1) { | |
309 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
310 | } else if (*rev == MV88F5181L_REV_A1) { |
311 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 312 | } else { |
d2b2a6bb | 313 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 314 | } |
d323ade1 LB |
315 | } else if (*dev == MV88F6183_DEV_ID) { |
316 | if (*rev == MV88F6183_REV_B0) { | |
317 | *dev_name = "MV88F6183-Rev-B0"; | |
318 | } else { | |
319 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
320 | } | |
c67de5b3 TP |
321 | } else { |
322 | *dev_name = "Device-Unknown"; | |
323 | } | |
324 | } | |
325 | ||
9dd0b194 | 326 | void __init orion5x_init(void) |
c67de5b3 TP |
327 | { |
328 | char *dev_name; | |
329 | u32 dev, rev; | |
330 | ||
9dd0b194 | 331 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
332 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
333 | ||
c67de5b3 TP |
334 | /* |
335 | * Setup Orion address map | |
336 | */ | |
5d1190ea | 337 | orion5x_setup_wins(); |
ce72e36e | 338 | |
2f129bf4 AL |
339 | /* Setup root of clk tree */ |
340 | clk_init(); | |
341 | ||
ce72e36e LB |
342 | /* |
343 | * Don't issue "Wait for Interrupt" instruction if we are | |
344 | * running on D0 5281 silicon. | |
345 | */ | |
346 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
347 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
f7b861b7 | 348 | cpu_idle_poll_ctrl(true); |
ce72e36e | 349 | } |
9e058d4f | 350 | |
3fade49b NP |
351 | /* |
352 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | |
353 | * while 5180n/5181/5281 don't have crypto. | |
354 | */ | |
355 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | |
356 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | |
357 | orion5x_crypto_init(); | |
358 | ||
9e058d4f TR |
359 | /* |
360 | * Register watchdog driver | |
361 | */ | |
362 | orion5x_wdt_init(); | |
c67de5b3 | 363 | } |
be73a347 | 364 | |
7b6d864b | 365 | void orion5x_restart(enum reboot_mode mode, const char *cmd) |
764cbcc2 RK |
366 | { |
367 | /* | |
368 | * Enable and issue soft reset | |
369 | */ | |
370 | orion5x_setbits(RSTOUTn_MASK, (1 << 2)); | |
371 | orion5x_setbits(CPU_SOFT_RESET, 1); | |
372 | mdelay(200); | |
373 | orion5x_clrbits(CPU_SOFT_RESET, 1); | |
374 | } | |
375 | ||
be73a347 GL |
376 | /* |
377 | * Many orion-based systems have buggy bootloader implementations. | |
378 | * This is a common fixup for bogus memory tags. | |
379 | */ | |
1c2f87c2 | 380 | void __init tag_fixup_mem32(struct tag *t, char **from) |
be73a347 GL |
381 | { |
382 | for (; t->hdr.size; t = tag_next(t)) | |
383 | if (t->hdr.tag == ATAG_MEM && | |
384 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
385 | t->u.mem.start & ~PAGE_MASK)) { | |
386 | printk(KERN_WARNING | |
387 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
388 | t->u.mem.size / 1024, t->u.mem.start); | |
389 | t->hdr.tag = 0; | |
390 | } | |
391 | } |