[deliverable/linux.git] / arch / arm / mach-orion5x / common.c

/*
 * arch/arm/mach-orion5x/common.c
 *
 * Core functions for Marvell Orion 5x SoCs
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/orion5x.h>
#include <plat/ehci-orion.h>
#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include "common.h"

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc orion5x_io_desc[] __initdata = {
	{
		.virtual	= ORION5X_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
		.length		= ORION5X_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
		.length		= ORION5X_PCIE_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
		.length		= ORION5X_PCI_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
		.length		= ORION5X_PCIE_WA_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init orion5x_map_io(void)
{
	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
}


/*****************************************************************************
 * EHCI
 ****************************************************************************/
static struct orion_ehci_data orion5x_ehci_data = {
	.dram		= &orion5x_mbus_dram_info,
};

static u64 ehci_dmamask = 0xffffffffUL;


/*****************************************************************************
 * EHCI0
 ****************************************************************************/
static struct resource orion5x_ehci0_resources[] = {
	{
		.start	= ORION5X_USB0_PHYS_BASE,
		.end	= ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB0_CTRL,
		.end	= IRQ_ORION5X_USB0_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_ehci0 = {
	.name		= "orion-ehci",
	.id		= 0,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &orion5x_ehci_data,
	},
	.resource	= orion5x_ehci0_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci0_resources),
};

void __init orion5x_ehci0_init(void)
{
	platform_device_register(&orion5x_ehci0);
}


/*****************************************************************************
 * EHCI1
 ****************************************************************************/
static struct resource orion5x_ehci1_resources[] = {
	{
		.start	= ORION5X_USB1_PHYS_BASE,
		.end	= ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB1_CTRL,
		.end	= IRQ_ORION5X_USB1_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_ehci1 = {
	.name		= "orion-ehci",
	.id		= 1,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &orion5x_ehci_data,
	},
	.resource	= orion5x_ehci1_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci1_resources),
};

void __init orion5x_ehci1_init(void)
{
	platform_device_register(&orion5x_ehci1);
}


/*****************************************************************************
 * GigE
 ****************************************************************************/
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
	.dram		= &orion5x_mbus_dram_info,
};

static struct resource orion5x_eth_shared_resources[] = {
	{
		.start	= ORION5X_ETH_PHYS_BASE + 0x2000,
		.end	= ORION5X_ETH_PHYS_BASE + 0x3fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_ETH_ERR,
		.end	= IRQ_ORION5X_ETH_ERR,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_eth_shared = {
	.name		= MV643XX_ETH_SHARED_NAME,
	.id		= 0,
	.dev		= {
		.platform_data	= &orion5x_eth_shared_data,
	},
	.num_resources	= ARRAY_SIZE(orion5x_eth_shared_resources),
	.resource	= orion5x_eth_shared_resources,
};

static struct resource orion5x_eth_resources[] = {
	{
		.name	= "eth irq",
		.start	= IRQ_ORION5X_ETH_SUM,
		.end	= IRQ_ORION5X_ETH_SUM,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_eth = {
	.name		= MV643XX_ETH_NAME,
	.id		= 0,
	.num_resources	= 1,
	.resource	= orion5x_eth_resources,
};

void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
	eth_data->shared = &orion5x_eth_shared;
	orion5x_eth.dev.platform_data = eth_data;

	platform_device_register(&orion5x_eth_shared);
	platform_device_register(&orion5x_eth);
}


/*****************************************************************************
 * I2C
 ****************************************************************************/
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
	.freq_m		= 8, /* assumes 166 MHz TCLK */
	.freq_n		= 3,
	.timeout	= 1000, /* Default timeout of 1 second */
};

static struct resource orion5x_i2c_resources[] = {
	{
		.name	= "i2c base",
		.start	= I2C_PHYS_BASE,
		.end	= I2C_PHYS_BASE + 0x1f,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "i2c irq",
		.start	= IRQ_ORION5X_I2C,
		.end	= IRQ_ORION5X_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_i2c = {
	.name		= MV64XXX_I2C_CTLR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_i2c_resources),
	.resource	= orion5x_i2c_resources,
	.dev		= {
		.platform_data	= &orion5x_i2c_pdata,
	},
};

void __init orion5x_i2c_init(void)
{
	platform_device_register(&orion5x_i2c);
}


/*****************************************************************************
 * SATA
 ****************************************************************************/
static struct resource orion5x_sata_resources[] = {
	{
		.name	= "sata base",
		.start	= ORION5X_SATA_PHYS_BASE,
		.end	= ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "sata irq",
		.start	= IRQ_ORION5X_SATA,
		.end	= IRQ_ORION5X_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_sata = {
	.name		= "sata_mv",
	.id		= 0,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(orion5x_sata_resources),
	.resource	= orion5x_sata_resources,
};

void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
	sata_data->dram = &orion5x_mbus_dram_info;
	orion5x_sata.dev.platform_data = sata_data;
	platform_device_register(&orion5x_sata);
}


/*****************************************************************************
 * UART0
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart0_data[] = {
	{
		.mapbase	= UART0_PHYS_BASE,
		.membase	= (char *)UART0_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART0,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 0,
	}, {
	},
};

static struct resource orion5x_uart0_resources[] = {
	{
		.start		= UART0_PHYS_BASE,
		.end		= UART0_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART0,
		.end		= IRQ_ORION5X_UART0,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart0 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= orion5x_uart0_data,
	},
	.resource		= orion5x_uart0_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart0_resources),
};

void __init orion5x_uart0_init(void)
{
	platform_device_register(&orion5x_uart0);
}


/*****************************************************************************
 * UART1
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart1_data[] = {
	{
		.mapbase	= UART1_PHYS_BASE,
		.membase	= (char *)UART1_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART1,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 0,
	}, {
	},
};

static struct resource orion5x_uart1_resources[] = {
	{
		.start		= UART1_PHYS_BASE,
		.end		= UART1_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART1,
		.end		= IRQ_ORION5X_UART1,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart1 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM1,
	.dev			= {
		.platform_data	= orion5x_uart1_data,
	},
	.resource		= orion5x_uart1_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart1_resources),
};

void __init orion5x_uart1_init(void)
{
	platform_device_register(&orion5x_uart1);
}


/*****************************************************************************
 * XOR engine
 ****************************************************************************/
static struct resource orion5x_xor_shared_resources[] = {
	{
		.name	= "xor low",
		.start	= ORION5X_XOR_PHYS_BASE,
		.end	= ORION5X_XOR_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor high",
		.start	= ORION5X_XOR_PHYS_BASE + 0x200,
		.end	= ORION5X_XOR_PHYS_BASE + 0x2ff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device orion5x_xor_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor_shared_resources),
	.resource	= orion5x_xor_shared_resources,
};

static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;

static struct resource orion5x_xor0_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR0,
		.end	= IRQ_ORION5X_XOR0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor0_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor0_channel = {
	.name		= MV_XOR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor0_resources),
	.resource	= orion5x_xor0_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
		.coherent_dma_mask	= DMA_64BIT_MASK,
		.platform_data		= (void *)&orion5x_xor0_data,
	},
};

static struct resource orion5x_xor1_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR1,
		.end	= IRQ_ORION5X_XOR1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor1_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor1_channel = {
	.name		= MV_XOR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(orion5x_xor1_resources),
	.resource	= orion5x_xor1_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
		.coherent_dma_mask	= DMA_64BIT_MASK,
		.platform_data		= (void *)&orion5x_xor1_data,
	},
};

void __init orion5x_xor_init(void)
{
	platform_device_register(&orion5x_xor_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
	platform_device_register(&orion5x_xor0_channel);

	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
	platform_device_register(&orion5x_xor1_channel);
}


/*****************************************************************************
 * Time handling
 ****************************************************************************/
int orion5x_tclk;

int __init orion5x_find_tclk(void)
{
	return 166666667;
}

static void orion5x_timer_init(void)
{
	orion5x_tclk = orion5x_find_tclk();
	orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
}

struct sys_timer orion5x_timer = {
	.init = orion5x_timer_init,
};


/*****************************************************************************
 * General
 ****************************************************************************/
/*
 * Identify device ID and rev from PCIe configuration header space '0'.
 */
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
{
	orion5x_pcie_id(dev, rev);

	if (*dev == MV88F5281_DEV_ID) {
		if (*rev == MV88F5281_REV_D2) {
			*dev_name = "MV88F5281-D2";
		} else if (*rev == MV88F5281_REV_D1) {
			*dev_name = "MV88F5281-D1";
		} else if (*rev == MV88F5281_REV_D0) {
			*dev_name = "MV88F5281-D0";
		} else {
			*dev_name = "MV88F5281-Rev-Unsupported";
		}
	} else if (*dev == MV88F5182_DEV_ID) {
		if (*rev == MV88F5182_REV_A2) {
			*dev_name = "MV88F5182-A2";
		} else {
			*dev_name = "MV88F5182-Rev-Unsupported";
		}
	} else if (*dev == MV88F5181_DEV_ID) {
		if (*rev == MV88F5181_REV_B1) {
			*dev_name = "MV88F5181-Rev-B1";
		} else if (*rev == MV88F5181L_REV_A1) {
			*dev_name = "MV88F5181L-Rev-A1";
		} else {
			*dev_name = "MV88F5181(L)-Rev-Unsupported";
		}
	} else {
		*dev_name = "Device-Unknown";
	}
}

void __init orion5x_init(void)
{
	char *dev_name;
	u32 dev, rev;

	orion5x_id(&dev, &rev, &dev_name);
	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);

	orion5x_eth_shared_data.t_clk = orion5x_tclk;
	orion5x_uart0_data[0].uartclk = orion5x_tclk;
	orion5x_uart1_data[0].uartclk = orion5x_tclk;

	/*
	 * Setup Orion address map
	 */
	orion5x_setup_cpu_mbus_bridge();

	/*
	 * Don't issue "Wait for Interrupt" instruction if we are
	 * running on D0 5281 silicon.
	 */
	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
		disable_hlt();
	}
}

/*
 * Many orion-based systems have buggy bootloader implementations.
 * This is a common fixup for bogus memory tags.
 */
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
			    char **from, struct meminfo *meminfo)
{
	for (; t->hdr.size; t = tag_next(t))
		if (t->hdr.tag == ATAG_MEM &&
		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
		     t->u.mem.start & ~PAGE_MASK)) {
			printk(KERN_WARNING
			       "Clearing invalid memory bank %dKB@0x%08x\n",
			       t->u.mem.size / 1024, t->u.mem.start);
			t->hdr.tag = 0;
		}
}
Commit	Line	Data
585cf175	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/common.c
585cf175	3	*
9dd0b194	4	* Core functions for Marvell Orion 5x SoCs
585cf175 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
585cf175 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
ca26f7d3 TP	15	#include <linux/platform_device.h>
ca26f7d3 TP	16	#include <linux/serial_8250.h>
83b6d822	17	#include <linux/mbus.h>
e07c9d85	18	#include <linux/mv643xx_eth.h>
144aa3db	19	#include <linux/mv643xx_i2c.h>
15a32632	20	#include <linux/ata_platform.h>
585cf175	21	#include <asm/page.h>
be73a347	22	#include <asm/setup.h>
c67de5b3	23	#include <asm/timex.h>
be73a347	24	#include <asm/mach/arch.h>
585cf175	25	#include <asm/mach/map.h>
2bac1de2	26	#include <asm/mach/time.h>
a09e64fb RK	27	#include <mach/hardware.h>
a09e64fb RK	28	#include <mach/orion5x.h>
6f088f1d	29	#include <plat/ehci-orion.h>
1d5a1a6e	30	#include <plat/mv_xor.h>
6f088f1d LB	31	#include <plat/orion_nand.h>
6f088f1d LB	32	#include <plat/time.h>
585cf175 TP	33	#include "common.h"
	34
	35	/*****************************************************************************
	36	* I/O Address Mapping
	37	****************************************************************************/
9dd0b194	38	static struct map_desc orion5x_io_desc[] __initdata = {
585cf175	39	{
9dd0b194 LB	40	.virtual = ORION5X_REGS_VIRT_BASE,
	41	.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
	42	.length = ORION5X_REGS_SIZE,
e7068ad3 LB	43	.type = MT_DEVICE,
e7068ad3 LB	44	}, {
9dd0b194 LB	45	.virtual = ORION5X_PCIE_IO_VIRT_BASE,
	46	.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
	47	.length = ORION5X_PCIE_IO_SIZE,
e7068ad3 LB	48	.type = MT_DEVICE,
e7068ad3 LB	49	}, {
9dd0b194 LB	50	.virtual = ORION5X_PCI_IO_VIRT_BASE,
	51	.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
	52	.length = ORION5X_PCI_IO_SIZE,
e7068ad3 LB	53	.type = MT_DEVICE,
e7068ad3 LB	54	}, {
9dd0b194 LB	55	.virtual = ORION5X_PCIE_WA_VIRT_BASE,
	56	.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
	57	.length = ORION5X_PCIE_WA_SIZE,
e7068ad3	58	.type = MT_DEVICE,
585cf175 TP	59	},
	60	};
	61
9dd0b194	62	void __init orion5x_map_io(void)
585cf175	63	{
9dd0b194	64	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
585cf175	65	}
c67de5b3	66
044f6c7c	67
ca26f7d3	68	/*****************************************************************************
044f6c7c	69	* EHCI
ca26f7d3	70	****************************************************************************/
044f6c7c LB	71	static struct orion_ehci_data orion5x_ehci_data = {
044f6c7c LB	72	.dram = &orion5x_mbus_dram_info,
ca26f7d3 TP	73	};
ca26f7d3 TP	74
044f6c7c	75	static u64 ehci_dmamask = 0xffffffffUL;
ca26f7d3	76
ca26f7d3	77
044f6c7c LB	78	/*****************************************************************************
	79	* EHCI0
	80	****************************************************************************/
9dd0b194	81	static struct resource orion5x_ehci0_resources[] = {
ca26f7d3	82	{
9dd0b194	83	.start = ORION5X_USB0_PHYS_BASE,
994cab84	84	.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
ca26f7d3	85	.flags = IORESOURCE_MEM,
e7068ad3	86	}, {
9dd0b194 LB	87	.start = IRQ_ORION5X_USB0_CTRL,
9dd0b194 LB	88	.end = IRQ_ORION5X_USB0_CTRL,
ca26f7d3 TP	89	.flags = IORESOURCE_IRQ,
	90	},
	91	};
	92
9dd0b194	93	static struct platform_device orion5x_ehci0 = {
ca26f7d3 TP	94	.name = "orion-ehci",
	95	.id = 0,
	96	.dev = {
	97	.dma_mask = &ehci_dmamask,
	98	.coherent_dma_mask = 0xffffffff,
9dd0b194	99	.platform_data = &orion5x_ehci_data,
ca26f7d3	100	},
9dd0b194 LB	101	.resource = orion5x_ehci0_resources,
9dd0b194 LB	102	.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
ca26f7d3 TP	103	};
ca26f7d3 TP	104
044f6c7c LB	105	void __init orion5x_ehci0_init(void)
	106	{
	107	platform_device_register(&orion5x_ehci0);
	108	}
	109
	110
	111	/*****************************************************************************
	112	* EHCI1
	113	****************************************************************************/
	114	static struct resource orion5x_ehci1_resources[] = {
	115	{
	116	.start = ORION5X_USB1_PHYS_BASE,
	117	.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
	118	.flags = IORESOURCE_MEM,
	119	}, {
	120	.start = IRQ_ORION5X_USB1_CTRL,
	121	.end = IRQ_ORION5X_USB1_CTRL,
	122	.flags = IORESOURCE_IRQ,
	123	},
	124	};
	125
9dd0b194	126	static struct platform_device orion5x_ehci1 = {
ca26f7d3 TP	127	.name = "orion-ehci",
	128	.id = 1,
	129	.dev = {
	130	.dma_mask = &ehci_dmamask,
	131	.coherent_dma_mask = 0xffffffff,
9dd0b194	132	.platform_data = &orion5x_ehci_data,
ca26f7d3	133	},
9dd0b194 LB	134	.resource = orion5x_ehci1_resources,
9dd0b194 LB	135	.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
ca26f7d3 TP	136	};
ca26f7d3 TP	137
044f6c7c LB	138	void __init orion5x_ehci1_init(void)
	139	{
	140	platform_device_register(&orion5x_ehci1);
	141	}
	142
	143
e07c9d85	144	/*****************************************************************************
044f6c7c	145	* GigE
e07c9d85	146	****************************************************************************/
d236f5a5 LB	147	struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
	148	.dram = &orion5x_mbus_dram_info,
	149	};
	150
9dd0b194	151	static struct resource orion5x_eth_shared_resources[] = {
e07c9d85	152	{
9dd0b194 LB	153	.start = ORION5X_ETH_PHYS_BASE + 0x2000,
9dd0b194 LB	154	.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
e07c9d85	155	.flags = IORESOURCE_MEM,
eeff6d86 LB	156	}, {
	157	.start = IRQ_ORION5X_ETH_ERR,
	158	.end = IRQ_ORION5X_ETH_ERR,
	159	.flags = IORESOURCE_IRQ,
e07c9d85 TP	160	},
	161	};
	162
9dd0b194	163	static struct platform_device orion5x_eth_shared = {
e07c9d85 TP	164	.name = MV643XX_ETH_SHARED_NAME,
e07c9d85 TP	165	.id = 0,
d236f5a5 LB	166	.dev = {
	167	.platform_data = &orion5x_eth_shared_data,
	168	},
eeff6d86	169	.num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
9dd0b194	170	.resource = orion5x_eth_shared_resources,
e07c9d85 TP	171	};
e07c9d85 TP	172
9dd0b194	173	static struct resource orion5x_eth_resources[] = {
e07c9d85 TP	174	{
e07c9d85 TP	175	.name = "eth irq",
9dd0b194 LB	176	.start = IRQ_ORION5X_ETH_SUM,
9dd0b194 LB	177	.end = IRQ_ORION5X_ETH_SUM,
e07c9d85	178	.flags = IORESOURCE_IRQ,
e7068ad3	179	},
e07c9d85 TP	180	};
e07c9d85 TP	181
9dd0b194	182	static struct platform_device orion5x_eth = {
e07c9d85 TP	183	.name = MV643XX_ETH_NAME,
	184	.id = 0,
	185	.num_resources = 1,
9dd0b194	186	.resource = orion5x_eth_resources,
e07c9d85 TP	187	};
e07c9d85 TP	188
9dd0b194	189	void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
e07c9d85	190	{
fa3959f4	191	eth_data->shared = &orion5x_eth_shared;
9dd0b194	192	orion5x_eth.dev.platform_data = eth_data;
fa3959f4	193
9dd0b194 LB	194	platform_device_register(&orion5x_eth_shared);
9dd0b194 LB	195	platform_device_register(&orion5x_eth);
e07c9d85 TP	196	}
e07c9d85 TP	197
044f6c7c	198
144aa3db	199	/*****************************************************************************
044f6c7c	200	* I2C
144aa3db	201	****************************************************************************/
9dd0b194	202	static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
144aa3db HVR	203	.freq_m = 8, /* assumes 166 MHz TCLK */
	204	.freq_n = 3,
	205	.timeout = 1000, /* Default timeout of 1 second */
	206	};
	207
9dd0b194	208	static struct resource orion5x_i2c_resources[] = {
144aa3db	209	{
e7068ad3 LB	210	.name = "i2c base",
e7068ad3 LB	211	.start = I2C_PHYS_BASE,
044f6c7c	212	.end = I2C_PHYS_BASE + 0x1f,
e7068ad3 LB	213	.flags = IORESOURCE_MEM,
	214	}, {
	215	.name = "i2c irq",
	216	.start = IRQ_ORION5X_I2C,
	217	.end = IRQ_ORION5X_I2C,
	218	.flags = IORESOURCE_IRQ,
144aa3db HVR	219	},
	220	};
	221
9dd0b194	222	static struct platform_device orion5x_i2c = {
144aa3db HVR	223	.name = MV64XXX_I2C_CTLR_NAME,
144aa3db HVR	224	.id = 0,
9dd0b194 LB	225	.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
9dd0b194 LB	226	.resource = orion5x_i2c_resources,
144aa3db	227	.dev = {
e7068ad3	228	.platform_data = &orion5x_i2c_pdata,
144aa3db HVR	229	},
	230	};
	231
044f6c7c LB	232	void __init orion5x_i2c_init(void)
	233	{
	234	platform_device_register(&orion5x_i2c);
	235	}
	236
	237
f244baa3	238	/*****************************************************************************
044f6c7c	239	* SATA
f244baa3	240	****************************************************************************/
9dd0b194	241	static struct resource orion5x_sata_resources[] = {
f244baa3	242	{
e7068ad3 LB	243	.name = "sata base",
	244	.start = ORION5X_SATA_PHYS_BASE,
	245	.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
	246	.flags = IORESOURCE_MEM,
	247	}, {
	248	.name = "sata irq",
	249	.start = IRQ_ORION5X_SATA,
	250	.end = IRQ_ORION5X_SATA,
	251	.flags = IORESOURCE_IRQ,
	252	},
f244baa3 SB	253	};
f244baa3 SB	254
9dd0b194	255	static struct platform_device orion5x_sata = {
e7068ad3 LB	256	.name = "sata_mv",
e7068ad3 LB	257	.id = 0,
f244baa3 SB	258	.dev = {
	259	.coherent_dma_mask = 0xffffffff,
	260	},
e7068ad3 LB	261	.num_resources = ARRAY_SIZE(orion5x_sata_resources),
e7068ad3 LB	262	.resource = orion5x_sata_resources,
f244baa3 SB	263	};
f244baa3 SB	264
9dd0b194	265	void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
f244baa3	266	{
9dd0b194 LB	267	sata_data->dram = &orion5x_mbus_dram_info;
	268	orion5x_sata.dev.platform_data = sata_data;
	269	platform_device_register(&orion5x_sata);
f244baa3 SB	270	}
f244baa3 SB	271
044f6c7c	272
2bac1de2	273	/*****************************************************************************
044f6c7c LB	274	* UART0
	275	****************************************************************************/
	276	static struct plat_serial8250_port orion5x_uart0_data[] = {
	277	{
	278	.mapbase = UART0_PHYS_BASE,
	279	.membase = (char *)UART0_VIRT_BASE,
	280	.irq = IRQ_ORION5X_UART0,
	281	.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
	282	.iotype = UPIO_MEM,
	283	.regshift = 2,
ebe35aff	284	.uartclk = 0,
044f6c7c LB	285	}, {
	286	},
	287	};
	288
	289	static struct resource orion5x_uart0_resources[] = {
	290	{
	291	.start = UART0_PHYS_BASE,
	292	.end = UART0_PHYS_BASE + 0xff,
	293	.flags = IORESOURCE_MEM,
	294	}, {
	295	.start = IRQ_ORION5X_UART0,
	296	.end = IRQ_ORION5X_UART0,
	297	.flags = IORESOURCE_IRQ,
	298	},
	299	};
	300
	301	static struct platform_device orion5x_uart0 = {
	302	.name = "serial8250",
	303	.id = PLAT8250_DEV_PLATFORM,
	304	.dev = {
	305	.platform_data = orion5x_uart0_data,
	306	},
	307	.resource = orion5x_uart0_resources,
	308	.num_resources = ARRAY_SIZE(orion5x_uart0_resources),
	309	};
	310
	311	void __init orion5x_uart0_init(void)
	312	{
	313	platform_device_register(&orion5x_uart0);
	314	}
	315
	316
	317	/*****************************************************************************
	318	* UART1
2bac1de2	319	****************************************************************************/
044f6c7c LB	320	static struct plat_serial8250_port orion5x_uart1_data[] = {
	321	{
	322	.mapbase = UART1_PHYS_BASE,
	323	.membase = (char *)UART1_VIRT_BASE,
	324	.irq = IRQ_ORION5X_UART1,
	325	.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
	326	.iotype = UPIO_MEM,
	327	.regshift = 2,
ebe35aff	328	.uartclk = 0,
044f6c7c LB	329	}, {
	330	},
	331	};
	332
	333	static struct resource orion5x_uart1_resources[] = {
	334	{
	335	.start = UART1_PHYS_BASE,
	336	.end = UART1_PHYS_BASE + 0xff,
	337	.flags = IORESOURCE_MEM,
	338	}, {
	339	.start = IRQ_ORION5X_UART1,
	340	.end = IRQ_ORION5X_UART1,
	341	.flags = IORESOURCE_IRQ,
	342	},
	343	};
	344
	345	static struct platform_device orion5x_uart1 = {
	346	.name = "serial8250",
	347	.id = PLAT8250_DEV_PLATFORM1,
	348	.dev = {
	349	.platform_data = orion5x_uart1_data,
	350	},
	351	.resource = orion5x_uart1_resources,
	352	.num_resources = ARRAY_SIZE(orion5x_uart1_resources),
	353	};
	354
	355	void __init orion5x_uart1_init(void)
	356	{
	357	platform_device_register(&orion5x_uart1);
	358	}
2bac1de2	359
044f6c7c	360
1d5a1a6e SB	361	/*****************************************************************************
	362	* XOR engine
	363	****************************************************************************/
	364	static struct resource orion5x_xor_shared_resources[] = {
	365	{
	366	.name = "xor low",
	367	.start = ORION5X_XOR_PHYS_BASE,
	368	.end = ORION5X_XOR_PHYS_BASE + 0xff,
	369	.flags = IORESOURCE_MEM,
	370	}, {
	371	.name = "xor high",
	372	.start = ORION5X_XOR_PHYS_BASE + 0x200,
	373	.end = ORION5X_XOR_PHYS_BASE + 0x2ff,
	374	.flags = IORESOURCE_MEM,
	375	},
	376	};
	377
	378	static struct platform_device orion5x_xor_shared = {
	379	.name = MV_XOR_SHARED_NAME,
	380	.id = 0,
	381	.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
	382	.resource = orion5x_xor_shared_resources,
	383	};
	384
	385	static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;
	386
	387	static struct resource orion5x_xor0_resources[] = {
	388	[0] = {
	389	.start = IRQ_ORION5X_XOR0,
	390	.end = IRQ_ORION5X_XOR0,
	391	.flags = IORESOURCE_IRQ,
	392	},
	393	};
	394
	395	static struct mv_xor_platform_data orion5x_xor0_data = {
	396	.shared = &orion5x_xor_shared,
	397	.hw_id = 0,
	398	.pool_size = PAGE_SIZE,
	399	};
	400
	401	static struct platform_device orion5x_xor0_channel = {
	402	.name = MV_XOR_NAME,
	403	.id = 0,
	404	.num_resources = ARRAY_SIZE(orion5x_xor0_resources),
	405	.resource = orion5x_xor0_resources,
	406	.dev = {
	407	.dma_mask = &orion5x_xor_dmamask,
	408	.coherent_dma_mask = DMA_64BIT_MASK,
	409	.platform_data = (void *)&orion5x_xor0_data,
	410	},
	411	};
	412
	413	static struct resource orion5x_xor1_resources[] = {
	414	[0] = {
	415	.start = IRQ_ORION5X_XOR1,
	416	.end = IRQ_ORION5X_XOR1,
	417	.flags = IORESOURCE_IRQ,
	418	},
	419	};
	420
	421	static struct mv_xor_platform_data orion5x_xor1_data = {
	422	.shared = &orion5x_xor_shared,
	423	.hw_id = 1,
	424	.pool_size = PAGE_SIZE,
425	};
426
427	static struct platform_device orion5x_xor1_channel = {
428	.name = MV_XOR_NAME,
429	.id = 1,
430	.num_resources = ARRAY_SIZE(orion5x_xor1_resources),
431	.resource = orion5x_xor1_resources,
432	.dev = {
433	.dma_mask = &orion5x_xor_dmamask,
434	.coherent_dma_mask = DMA_64BIT_MASK,
435	.platform_data = (void *)&orion5x_xor1_data,
436	},
437	};
438
439	void __init orion5x_xor_init(void)
440	{
441	platform_device_register(&orion5x_xor_shared);
442
443	/*
444	* two engines can't do memset simultaneously, this limitation
445	* satisfied by removing memset support from one of the engines.
446	*/
447	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
448	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
449	platform_device_register(&orion5x_xor0_channel);
450
451	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
452	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
453	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
454	platform_device_register(&orion5x_xor1_channel);
455	}
456
457
044f6c7c LB	458	/*****************************************************************************
	459	* Time handling
	460	****************************************************************************/
ebe35aff LB	461	int orion5x_tclk;
	462
	463	int __init orion5x_find_tclk(void)
	464	{
	465	return 166666667;
	466	}
	467
9dd0b194	468	static void orion5x_timer_init(void)
2bac1de2	469	{
ebe35aff LB	470	orion5x_tclk = orion5x_find_tclk();
ebe35aff LB	471	orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
2bac1de2 LB	472	}
2bac1de2 LB	473
9dd0b194	474	struct sys_timer orion5x_timer = {
e7068ad3	475	.init = orion5x_timer_init,
2bac1de2 LB	476	};
2bac1de2 LB	477
044f6c7c	478
c67de5b3 TP	479	/*****************************************************************************
	480	* General
	481	****************************************************************************/
c67de5b3	482	/*
b46926bb	483	* Identify device ID and rev from PCIe configuration header space '0'.
c67de5b3	484	*/
9dd0b194	485	static void __init orion5x_id(u32 dev, u32 rev, char **dev_name)
c67de5b3	486	{
9dd0b194	487	orion5x_pcie_id(dev, rev);
c67de5b3 TP	488
	489	if (*dev == MV88F5281_DEV_ID) {
	490	if (*rev == MV88F5281_REV_D2) {
	491	*dev_name = "MV88F5281-D2";
	492	} else if (*rev == MV88F5281_REV_D1) {
	493	*dev_name = "MV88F5281-D1";
ce72e36e LB	494	} else if (*rev == MV88F5281_REV_D0) {
ce72e36e LB	495	*dev_name = "MV88F5281-D0";
c67de5b3 TP	496	} else {
	497	*dev_name = "MV88F5281-Rev-Unsupported";
	498	}
	499	} else if (*dev == MV88F5182_DEV_ID) {
	500	if (*rev == MV88F5182_REV_A2) {
	501	*dev_name = "MV88F5182-A2";
	502	} else {
	503	*dev_name = "MV88F5182-Rev-Unsupported";
	504	}
c9e3de94 HVR	505	} else if (*dev == MV88F5181_DEV_ID) {
	506	if (*rev == MV88F5181_REV_B1) {
	507	*dev_name = "MV88F5181-Rev-B1";
d2b2a6bb LB	508	} else if (*rev == MV88F5181L_REV_A1) {
d2b2a6bb LB	509	*dev_name = "MV88F5181L-Rev-A1";
c9e3de94	510	} else {
d2b2a6bb	511	*dev_name = "MV88F5181(L)-Rev-Unsupported";
c9e3de94	512	}
c67de5b3 TP	513	} else {
	514	*dev_name = "Device-Unknown";
	515	}
	516	}
	517
9dd0b194	518	void __init orion5x_init(void)
c67de5b3 TP	519	{
	520	char *dev_name;
	521	u32 dev, rev;
	522
9dd0b194	523	orion5x_id(&dev, &rev, &dev_name);
ebe35aff LB	524	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
	525
	526	orion5x_eth_shared_data.t_clk = orion5x_tclk;
	527	orion5x_uart0_data[0].uartclk = orion5x_tclk;
	528	orion5x_uart1_data[0].uartclk = orion5x_tclk;
c67de5b3 TP	529
	530	/*
	531	* Setup Orion address map
	532	*/
9dd0b194	533	orion5x_setup_cpu_mbus_bridge();
ce72e36e LB	534
	535	/*
	536	* Don't issue "Wait for Interrupt" instruction if we are
	537	* running on D0 5281 silicon.
	538	*/
	539	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
	540	printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
	541	disable_hlt();
	542	}
c67de5b3	543	}
be73a347 GL	544
	545	/*
	546	* Many orion-based systems have buggy bootloader implementations.
	547	* This is a common fixup for bogus memory tags.
	548	*/
	549	void __init tag_fixup_mem32(struct machine_desc mdesc, struct tag t,
	550	char *from, struct meminfo meminfo)
	551	{
	552	for (; t->hdr.size; t = tag_next(t))
	553	if (t->hdr.tag == ATAG_MEM &&
	554	(!t->u.mem.size \|\| t->u.mem.size & ~PAGE_MASK \|\|
	555	t->u.mem.start & ~PAGE_MASK)) {
	556	printk(KERN_WARNING
	557	"Clearing invalid memory bank %dKB@0x%08x\n",
	558	t->u.mem.size / 1024, t->u.mem.start);
	559	t->hdr.tag = 0;
	560	}
	561	}