Commit | Line | Data |
---|---|---|
585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 | 15 | #include <linux/platform_device.h> |
ee962723 | 16 | #include <linux/dma-mapping.h> |
ca26f7d3 | 17 | #include <linux/serial_8250.h> |
83b6d822 | 18 | #include <linux/mbus.h> |
144aa3db | 19 | #include <linux/mv643xx_i2c.h> |
15a32632 | 20 | #include <linux/ata_platform.h> |
764cbcc2 | 21 | #include <linux/delay.h> |
dcf1cece | 22 | #include <net/dsa.h> |
585cf175 | 23 | #include <asm/page.h> |
be73a347 | 24 | #include <asm/setup.h> |
c67de5b3 | 25 | #include <asm/timex.h> |
be73a347 | 26 | #include <asm/mach/arch.h> |
585cf175 | 27 | #include <asm/mach/map.h> |
2bac1de2 | 28 | #include <asm/mach/time.h> |
4ee1f6b5 | 29 | #include <mach/bridge-regs.h> |
a09e64fb RK |
30 | #include <mach/hardware.h> |
31 | #include <mach/orion5x.h> | |
6f088f1d LB |
32 | #include <plat/orion_nand.h> |
33 | #include <plat/time.h> | |
28a2b450 | 34 | #include <plat/common.h> |
585cf175 TP |
35 | #include "common.h" |
36 | ||
37 | /***************************************************************************** | |
38 | * I/O Address Mapping | |
39 | ****************************************************************************/ | |
9dd0b194 | 40 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 41 | { |
9dd0b194 LB |
42 | .virtual = ORION5X_REGS_VIRT_BASE, |
43 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), | |
44 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 LB |
45 | .type = MT_DEVICE, |
46 | }, { | |
9dd0b194 LB |
47 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
48 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), | |
49 | .length = ORION5X_PCIE_IO_SIZE, | |
e7068ad3 LB |
50 | .type = MT_DEVICE, |
51 | }, { | |
9dd0b194 LB |
52 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
53 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), | |
54 | .length = ORION5X_PCI_IO_SIZE, | |
e7068ad3 LB |
55 | .type = MT_DEVICE, |
56 | }, { | |
9dd0b194 LB |
57 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
58 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), | |
59 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 60 | .type = MT_DEVICE, |
585cf175 TP |
61 | }, |
62 | }; | |
63 | ||
9dd0b194 | 64 | void __init orion5x_map_io(void) |
585cf175 | 65 | { |
9dd0b194 | 66 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 67 | } |
c67de5b3 | 68 | |
044f6c7c | 69 | |
044f6c7c LB |
70 | /***************************************************************************** |
71 | * EHCI0 | |
72 | ****************************************************************************/ | |
044f6c7c LB |
73 | void __init orion5x_ehci0_init(void) |
74 | { | |
4fcd3f37 AL |
75 | orion_ehci_init(&orion5x_mbus_dram_info, |
76 | ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); | |
044f6c7c LB |
77 | } |
78 | ||
79 | ||
80 | /***************************************************************************** | |
81 | * EHCI1 | |
82 | ****************************************************************************/ | |
044f6c7c LB |
83 | void __init orion5x_ehci1_init(void) |
84 | { | |
4fcd3f37 AL |
85 | orion_ehci_1_init(&orion5x_mbus_dram_info, |
86 | ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); | |
044f6c7c LB |
87 | } |
88 | ||
89 | ||
e07c9d85 | 90 | /***************************************************************************** |
5c602551 | 91 | * GE00 |
e07c9d85 | 92 | ****************************************************************************/ |
9dd0b194 | 93 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 94 | { |
7e3819d8 AL |
95 | orion_ge00_init(eth_data, &orion5x_mbus_dram_info, |
96 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, | |
97 | IRQ_ORION5X_ETH_ERR, orion5x_tclk); | |
e07c9d85 TP |
98 | } |
99 | ||
044f6c7c | 100 | |
dcf1cece LB |
101 | /***************************************************************************** |
102 | * Ethernet switch | |
103 | ****************************************************************************/ | |
dcf1cece LB |
104 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) |
105 | { | |
7e3819d8 | 106 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
107 | } |
108 | ||
109 | ||
144aa3db | 110 | /***************************************************************************** |
044f6c7c | 111 | * I2C |
144aa3db | 112 | ****************************************************************************/ |
044f6c7c LB |
113 | void __init orion5x_i2c_init(void) |
114 | { | |
aac7ffa3 AL |
115 | orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); |
116 | ||
044f6c7c LB |
117 | } |
118 | ||
119 | ||
f244baa3 | 120 | /***************************************************************************** |
044f6c7c | 121 | * SATA |
f244baa3 | 122 | ****************************************************************************/ |
9dd0b194 | 123 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 124 | { |
9e613f8a AL |
125 | orion_sata_init(sata_data, &orion5x_mbus_dram_info, |
126 | ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); | |
f244baa3 SB |
127 | } |
128 | ||
044f6c7c | 129 | |
d323ade1 LB |
130 | /***************************************************************************** |
131 | * SPI | |
132 | ****************************************************************************/ | |
d323ade1 LB |
133 | void __init orion5x_spi_init() |
134 | { | |
980f9f60 | 135 | orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); |
d323ade1 LB |
136 | } |
137 | ||
138 | ||
2bac1de2 | 139 | /***************************************************************************** |
044f6c7c LB |
140 | * UART0 |
141 | ****************************************************************************/ | |
044f6c7c LB |
142 | void __init orion5x_uart0_init(void) |
143 | { | |
28a2b450 AL |
144 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
145 | IRQ_ORION5X_UART0, orion5x_tclk); | |
044f6c7c LB |
146 | } |
147 | ||
044f6c7c LB |
148 | /***************************************************************************** |
149 | * UART1 | |
2bac1de2 | 150 | ****************************************************************************/ |
044f6c7c LB |
151 | void __init orion5x_uart1_init(void) |
152 | { | |
28a2b450 AL |
153 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
154 | IRQ_ORION5X_UART1, orion5x_tclk); | |
044f6c7c | 155 | } |
2bac1de2 | 156 | |
1d5a1a6e SB |
157 | /***************************************************************************** |
158 | * XOR engine | |
159 | ****************************************************************************/ | |
1d5a1a6e SB |
160 | void __init orion5x_xor_init(void) |
161 | { | |
ee962723 AL |
162 | orion_xor0_init(&orion5x_mbus_dram_info, |
163 | ORION5X_XOR_PHYS_BASE, | |
164 | ORION5X_XOR_PHYS_BASE + 0x200, | |
165 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); | |
1d5a1a6e SB |
166 | } |
167 | ||
44350061 AL |
168 | /***************************************************************************** |
169 | * Cryptographic Engines and Security Accelerator (CESA) | |
170 | ****************************************************************************/ | |
171 | static void __init orion5x_crypto_init(void) | |
3a8f7441 SAS |
172 | { |
173 | int ret; | |
174 | ||
175 | ret = orion5x_setup_sram_win(); | |
176 | if (ret) | |
44350061 | 177 | return; |
3a8f7441 | 178 | |
44350061 AL |
179 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
180 | SZ_8K, IRQ_ORION5X_CESA); | |
3a8f7441 | 181 | } |
1d5a1a6e | 182 | |
9e058d4f TR |
183 | /***************************************************************************** |
184 | * Watchdog | |
185 | ****************************************************************************/ | |
9e058d4f TR |
186 | void __init orion5x_wdt_init(void) |
187 | { | |
5e00d378 | 188 | orion_wdt_init(orion5x_tclk); |
9e058d4f TR |
189 | } |
190 | ||
191 | ||
044f6c7c LB |
192 | /***************************************************************************** |
193 | * Time handling | |
194 | ****************************************************************************/ | |
4ee1f6b5 LB |
195 | void __init orion5x_init_early(void) |
196 | { | |
197 | orion_time_set_base(TIMER_VIRT_BASE); | |
198 | } | |
199 | ||
ebe35aff LB |
200 | int orion5x_tclk; |
201 | ||
202 | int __init orion5x_find_tclk(void) | |
203 | { | |
d323ade1 LB |
204 | u32 dev, rev; |
205 | ||
206 | orion5x_pcie_id(&dev, &rev); | |
207 | if (dev == MV88F6183_DEV_ID && | |
208 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
209 | return 133333333; | |
210 | ||
ebe35aff LB |
211 | return 166666667; |
212 | } | |
213 | ||
9dd0b194 | 214 | static void orion5x_timer_init(void) |
2bac1de2 | 215 | { |
ebe35aff | 216 | orion5x_tclk = orion5x_find_tclk(); |
4ee1f6b5 LB |
217 | |
218 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
219 | IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
220 | } |
221 | ||
9dd0b194 | 222 | struct sys_timer orion5x_timer = { |
e7068ad3 | 223 | .init = orion5x_timer_init, |
2bac1de2 LB |
224 | }; |
225 | ||
044f6c7c | 226 | |
c67de5b3 TP |
227 | /***************************************************************************** |
228 | * General | |
229 | ****************************************************************************/ | |
c67de5b3 | 230 | /* |
b46926bb | 231 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 232 | */ |
9dd0b194 | 233 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 234 | { |
9dd0b194 | 235 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
236 | |
237 | if (*dev == MV88F5281_DEV_ID) { | |
238 | if (*rev == MV88F5281_REV_D2) { | |
239 | *dev_name = "MV88F5281-D2"; | |
240 | } else if (*rev == MV88F5281_REV_D1) { | |
241 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
242 | } else if (*rev == MV88F5281_REV_D0) { |
243 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
244 | } else { |
245 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
246 | } | |
247 | } else if (*dev == MV88F5182_DEV_ID) { | |
248 | if (*rev == MV88F5182_REV_A2) { | |
249 | *dev_name = "MV88F5182-A2"; | |
250 | } else { | |
251 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
252 | } | |
c9e3de94 HVR |
253 | } else if (*dev == MV88F5181_DEV_ID) { |
254 | if (*rev == MV88F5181_REV_B1) { | |
255 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
256 | } else if (*rev == MV88F5181L_REV_A1) { |
257 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 258 | } else { |
d2b2a6bb | 259 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 260 | } |
d323ade1 LB |
261 | } else if (*dev == MV88F6183_DEV_ID) { |
262 | if (*rev == MV88F6183_REV_B0) { | |
263 | *dev_name = "MV88F6183-Rev-B0"; | |
264 | } else { | |
265 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
266 | } | |
c67de5b3 TP |
267 | } else { |
268 | *dev_name = "Device-Unknown"; | |
269 | } | |
270 | } | |
271 | ||
9dd0b194 | 272 | void __init orion5x_init(void) |
c67de5b3 TP |
273 | { |
274 | char *dev_name; | |
275 | u32 dev, rev; | |
276 | ||
9dd0b194 | 277 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
278 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
279 | ||
c67de5b3 TP |
280 | /* |
281 | * Setup Orion address map | |
282 | */ | |
9dd0b194 | 283 | orion5x_setup_cpu_mbus_bridge(); |
ce72e36e LB |
284 | |
285 | /* | |
286 | * Don't issue "Wait for Interrupt" instruction if we are | |
287 | * running on D0 5281 silicon. | |
288 | */ | |
289 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
290 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
291 | disable_hlt(); | |
292 | } | |
9e058d4f | 293 | |
3fade49b NP |
294 | /* |
295 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | |
296 | * while 5180n/5181/5281 don't have crypto. | |
297 | */ | |
298 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | |
299 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | |
300 | orion5x_crypto_init(); | |
301 | ||
9e058d4f TR |
302 | /* |
303 | * Register watchdog driver | |
304 | */ | |
305 | orion5x_wdt_init(); | |
c67de5b3 | 306 | } |
be73a347 | 307 | |
764cbcc2 RK |
308 | void orion5x_restart(char mode, const char *cmd) |
309 | { | |
310 | /* | |
311 | * Enable and issue soft reset | |
312 | */ | |
313 | orion5x_setbits(RSTOUTn_MASK, (1 << 2)); | |
314 | orion5x_setbits(CPU_SOFT_RESET, 1); | |
315 | mdelay(200); | |
316 | orion5x_clrbits(CPU_SOFT_RESET, 1); | |
317 | } | |
318 | ||
be73a347 GL |
319 | /* |
320 | * Many orion-based systems have buggy bootloader implementations. | |
321 | * This is a common fixup for bogus memory tags. | |
322 | */ | |
0744a3ee RK |
323 | void __init tag_fixup_mem32(struct tag *t, char **from, |
324 | struct meminfo *meminfo) | |
be73a347 GL |
325 | { |
326 | for (; t->hdr.size; t = tag_next(t)) | |
327 | if (t->hdr.tag == ATAG_MEM && | |
328 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
329 | t->u.mem.start & ~PAGE_MASK)) { | |
330 | printk(KERN_WARNING | |
331 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
332 | t->u.mem.size / 1024, t->u.mem.start); | |
333 | t->hdr.tag = 0; | |
334 | } | |
335 | } |