[ARM] Orion: fix various whitespace and coding style issues
[deliverable/linux.git] / arch / arm / mach-orion5x / common.c
CommitLineData
585cf175 1/*
9dd0b194 2 * arch/arm/mach-orion5x/common.c
585cf175 3 *
9dd0b194 4 * Core functions for Marvell Orion 5x SoCs
585cf175
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5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
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8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
585cf175
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10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
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15#include <linux/platform_device.h>
16#include <linux/serial_8250.h>
83b6d822 17#include <linux/mbus.h>
e07c9d85 18#include <linux/mv643xx_eth.h>
144aa3db 19#include <linux/mv643xx_i2c.h>
15a32632 20#include <linux/ata_platform.h>
585cf175 21#include <asm/page.h>
be73a347 22#include <asm/setup.h>
c67de5b3 23#include <asm/timex.h>
be73a347 24#include <asm/mach/arch.h>
585cf175 25#include <asm/mach/map.h>
2bac1de2 26#include <asm/mach/time.h>
f244baa3 27#include <asm/arch/hardware.h>
9dd0b194 28#include <asm/arch/orion5x.h>
705a7521 29#include <asm/plat-orion/ehci-orion.h>
5d4294c5 30#include <asm/plat-orion/orion_nand.h>
2bac1de2 31#include <asm/plat-orion/time.h>
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32#include "common.h"
33
34/*****************************************************************************
35 * I/O Address Mapping
36 ****************************************************************************/
9dd0b194 37static struct map_desc orion5x_io_desc[] __initdata = {
585cf175 38 {
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39 .virtual = ORION5X_REGS_VIRT_BASE,
40 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
41 .length = ORION5X_REGS_SIZE,
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42 .type = MT_DEVICE,
43 }, {
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44 .virtual = ORION5X_PCIE_IO_VIRT_BASE,
45 .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
46 .length = ORION5X_PCIE_IO_SIZE,
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47 .type = MT_DEVICE,
48 }, {
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49 .virtual = ORION5X_PCI_IO_VIRT_BASE,
50 .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
51 .length = ORION5X_PCI_IO_SIZE,
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52 .type = MT_DEVICE,
53 }, {
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54 .virtual = ORION5X_PCIE_WA_VIRT_BASE,
55 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
56 .length = ORION5X_PCIE_WA_SIZE,
e7068ad3 57 .type = MT_DEVICE,
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58 },
59};
60
9dd0b194 61void __init orion5x_map_io(void)
585cf175 62{
9dd0b194 63 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
585cf175 64}
c67de5b3 65
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66/*****************************************************************************
67 * UART
68 ****************************************************************************/
69
9dd0b194 70static struct resource orion5x_uart_resources[] = {
ca26f7d3 71 {
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72 .start = UART0_PHYS_BASE,
73 .end = UART0_PHYS_BASE + 0xff,
ca26f7d3 74 .flags = IORESOURCE_MEM,
e7068ad3 75 }, {
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76 .start = IRQ_ORION5X_UART0,
77 .end = IRQ_ORION5X_UART0,
ca26f7d3 78 .flags = IORESOURCE_IRQ,
e7068ad3 79 }, {
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80 .start = UART1_PHYS_BASE,
81 .end = UART1_PHYS_BASE + 0xff,
ca26f7d3 82 .flags = IORESOURCE_MEM,
e7068ad3 83 }, {
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84 .start = IRQ_ORION5X_UART1,
85 .end = IRQ_ORION5X_UART1,
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86 .flags = IORESOURCE_IRQ,
87 },
88};
89
9dd0b194 90static struct plat_serial8250_port orion5x_uart_data[] = {
ca26f7d3 91 {
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92 .mapbase = UART0_PHYS_BASE,
93 .membase = (char *)UART0_VIRT_BASE,
9dd0b194 94 .irq = IRQ_ORION5X_UART0,
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95 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
96 .iotype = UPIO_MEM,
97 .regshift = 2,
9dd0b194 98 .uartclk = ORION5X_TCLK,
e7068ad3 99 }, {
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100 .mapbase = UART1_PHYS_BASE,
101 .membase = (char *)UART1_VIRT_BASE,
9dd0b194 102 .irq = IRQ_ORION5X_UART1,
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103 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
104 .iotype = UPIO_MEM,
105 .regshift = 2,
9dd0b194 106 .uartclk = ORION5X_TCLK,
e7068ad3 107 }, {
ca26f7d3 108 },
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109};
110
9dd0b194 111static struct platform_device orion5x_uart = {
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112 .name = "serial8250",
113 .id = PLAT8250_DEV_PLATFORM,
114 .dev = {
9dd0b194 115 .platform_data = orion5x_uart_data,
ca26f7d3 116 },
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117 .resource = orion5x_uart_resources,
118 .num_resources = ARRAY_SIZE(orion5x_uart_resources),
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119};
120
121/*******************************************************************************
122 * USB Controller - 2 interfaces
123 ******************************************************************************/
124
9dd0b194 125static struct resource orion5x_ehci0_resources[] = {
ca26f7d3 126 {
9dd0b194 127 .start = ORION5X_USB0_PHYS_BASE,
994cab84 128 .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
ca26f7d3 129 .flags = IORESOURCE_MEM,
e7068ad3 130 }, {
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131 .start = IRQ_ORION5X_USB0_CTRL,
132 .end = IRQ_ORION5X_USB0_CTRL,
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133 .flags = IORESOURCE_IRQ,
134 },
135};
136
9dd0b194 137static struct resource orion5x_ehci1_resources[] = {
ca26f7d3 138 {
9dd0b194 139 .start = ORION5X_USB1_PHYS_BASE,
994cab84 140 .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
ca26f7d3 141 .flags = IORESOURCE_MEM,
e7068ad3 142 }, {
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143 .start = IRQ_ORION5X_USB1_CTRL,
144 .end = IRQ_ORION5X_USB1_CTRL,
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145 .flags = IORESOURCE_IRQ,
146 },
147};
148
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149static struct orion_ehci_data orion5x_ehci_data = {
150 .dram = &orion5x_mbus_dram_info,
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151};
152
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153static u64 ehci_dmamask = 0xffffffffUL;
154
9dd0b194 155static struct platform_device orion5x_ehci0 = {
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156 .name = "orion-ehci",
157 .id = 0,
158 .dev = {
159 .dma_mask = &ehci_dmamask,
160 .coherent_dma_mask = 0xffffffff,
9dd0b194 161 .platform_data = &orion5x_ehci_data,
ca26f7d3 162 },
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163 .resource = orion5x_ehci0_resources,
164 .num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
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165};
166
9dd0b194 167static struct platform_device orion5x_ehci1 = {
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168 .name = "orion-ehci",
169 .id = 1,
170 .dev = {
171 .dma_mask = &ehci_dmamask,
172 .coherent_dma_mask = 0xffffffff,
9dd0b194 173 .platform_data = &orion5x_ehci_data,
ca26f7d3 174 },
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175 .resource = orion5x_ehci1_resources,
176 .num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
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177};
178
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179/*****************************************************************************
180 * Gigabit Ethernet port
181 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
182 ****************************************************************************/
183
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184struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
185 .dram = &orion5x_mbus_dram_info,
b8c15a60 186 .t_clk = ORION5X_TCLK,
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187};
188
9dd0b194 189static struct resource orion5x_eth_shared_resources[] = {
e07c9d85 190 {
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191 .start = ORION5X_ETH_PHYS_BASE + 0x2000,
192 .end = ORION5X_ETH_PHYS_BASE + 0x3fff,
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193 .flags = IORESOURCE_MEM,
194 },
195};
196
9dd0b194 197static struct platform_device orion5x_eth_shared = {
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198 .name = MV643XX_ETH_SHARED_NAME,
199 .id = 0,
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200 .dev = {
201 .platform_data = &orion5x_eth_shared_data,
202 },
e07c9d85 203 .num_resources = 1,
9dd0b194 204 .resource = orion5x_eth_shared_resources,
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205};
206
9dd0b194 207static struct resource orion5x_eth_resources[] = {
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208 {
209 .name = "eth irq",
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210 .start = IRQ_ORION5X_ETH_SUM,
211 .end = IRQ_ORION5X_ETH_SUM,
e07c9d85 212 .flags = IORESOURCE_IRQ,
e7068ad3 213 },
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214};
215
9dd0b194 216static struct platform_device orion5x_eth = {
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217 .name = MV643XX_ETH_NAME,
218 .id = 0,
219 .num_resources = 1,
9dd0b194 220 .resource = orion5x_eth_resources,
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221};
222
9dd0b194 223void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
e07c9d85 224{
fa3959f4 225 eth_data->shared = &orion5x_eth_shared;
9dd0b194 226 orion5x_eth.dev.platform_data = eth_data;
fa3959f4 227
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228 platform_device_register(&orion5x_eth_shared);
229 platform_device_register(&orion5x_eth);
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230}
231
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232/*****************************************************************************
233 * I2C controller
234 * (The Orion and Discovery (MV643xx) families share the same I2C controller)
235 ****************************************************************************/
236
9dd0b194 237static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
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238 .freq_m = 8, /* assumes 166 MHz TCLK */
239 .freq_n = 3,
240 .timeout = 1000, /* Default timeout of 1 second */
241};
242
9dd0b194 243static struct resource orion5x_i2c_resources[] = {
144aa3db 244 {
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245 .name = "i2c base",
246 .start = I2C_PHYS_BASE,
247 .end = I2C_PHYS_BASE + 0x20 -1,
248 .flags = IORESOURCE_MEM,
249 }, {
250 .name = "i2c irq",
251 .start = IRQ_ORION5X_I2C,
252 .end = IRQ_ORION5X_I2C,
253 .flags = IORESOURCE_IRQ,
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254 },
255};
256
9dd0b194 257static struct platform_device orion5x_i2c = {
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258 .name = MV64XXX_I2C_CTLR_NAME,
259 .id = 0,
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260 .num_resources = ARRAY_SIZE(orion5x_i2c_resources),
261 .resource = orion5x_i2c_resources,
144aa3db 262 .dev = {
e7068ad3 263 .platform_data = &orion5x_i2c_pdata,
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264 },
265};
266
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267/*****************************************************************************
268 * Sata port
269 ****************************************************************************/
9dd0b194 270static struct resource orion5x_sata_resources[] = {
f244baa3 271 {
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272 .name = "sata base",
273 .start = ORION5X_SATA_PHYS_BASE,
274 .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
275 .flags = IORESOURCE_MEM,
276 }, {
277 .name = "sata irq",
278 .start = IRQ_ORION5X_SATA,
279 .end = IRQ_ORION5X_SATA,
280 .flags = IORESOURCE_IRQ,
281 },
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282};
283
9dd0b194 284static struct platform_device orion5x_sata = {
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285 .name = "sata_mv",
286 .id = 0,
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287 .dev = {
288 .coherent_dma_mask = 0xffffffff,
289 },
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290 .num_resources = ARRAY_SIZE(orion5x_sata_resources),
291 .resource = orion5x_sata_resources,
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292};
293
9dd0b194 294void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
f244baa3 295{
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296 sata_data->dram = &orion5x_mbus_dram_info;
297 orion5x_sata.dev.platform_data = sata_data;
298 platform_device_register(&orion5x_sata);
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299}
300
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301/*****************************************************************************
302 * Time handling
303 ****************************************************************************/
304
9dd0b194 305static void orion5x_timer_init(void)
2bac1de2 306{
9dd0b194 307 orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
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LB
308}
309
9dd0b194 310struct sys_timer orion5x_timer = {
e7068ad3 311 .init = orion5x_timer_init,
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312};
313
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314/*****************************************************************************
315 * General
316 ****************************************************************************/
317
318/*
b46926bb 319 * Identify device ID and rev from PCIe configuration header space '0'.
c67de5b3 320 */
9dd0b194 321static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
c67de5b3 322{
9dd0b194 323 orion5x_pcie_id(dev, rev);
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TP
324
325 if (*dev == MV88F5281_DEV_ID) {
326 if (*rev == MV88F5281_REV_D2) {
327 *dev_name = "MV88F5281-D2";
328 } else if (*rev == MV88F5281_REV_D1) {
329 *dev_name = "MV88F5281-D1";
330 } else {
331 *dev_name = "MV88F5281-Rev-Unsupported";
332 }
333 } else if (*dev == MV88F5182_DEV_ID) {
334 if (*rev == MV88F5182_REV_A2) {
335 *dev_name = "MV88F5182-A2";
336 } else {
337 *dev_name = "MV88F5182-Rev-Unsupported";
338 }
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339 } else if (*dev == MV88F5181_DEV_ID) {
340 if (*rev == MV88F5181_REV_B1) {
341 *dev_name = "MV88F5181-Rev-B1";
342 } else {
343 *dev_name = "MV88F5181-Rev-Unsupported";
344 }
c67de5b3
TP
345 } else {
346 *dev_name = "Device-Unknown";
347 }
348}
349
9dd0b194 350void __init orion5x_init(void)
c67de5b3
TP
351{
352 char *dev_name;
353 u32 dev, rev;
354
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LB
355 orion5x_id(&dev, &rev, &dev_name);
356 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);
c67de5b3
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357
358 /*
359 * Setup Orion address map
360 */
9dd0b194 361 orion5x_setup_cpu_mbus_bridge();
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362
363 /*
159ffb3a 364 * Register devices.
ca26f7d3 365 */
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366 platform_device_register(&orion5x_uart);
367 platform_device_register(&orion5x_ehci0);
ca26f7d3 368 if (dev == MV88F5182_DEV_ID)
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369 platform_device_register(&orion5x_ehci1);
370 platform_device_register(&orion5x_i2c);
c67de5b3 371}
be73a347
GL
372
373/*
374 * Many orion-based systems have buggy bootloader implementations.
375 * This is a common fixup for bogus memory tags.
376 */
377void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
378 char **from, struct meminfo *meminfo)
379{
380 for (; t->hdr.size; t = tag_next(t))
381 if (t->hdr.tag == ATAG_MEM &&
382 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
383 t->u.mem.start & ~PAGE_MASK)) {
384 printk(KERN_WARNING
385 "Clearing invalid memory bank %dKB@0x%08x\n",
386 t->u.mem.size / 1024, t->u.mem.start);
387 t->hdr.tag = 0;
388 }
389}
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