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[ARM] Orion: move setting up PCIe WA window into PCIe setup path
[deliverable/linux.git] / arch / arm / mach-orion5x / db88f5281-setup.c
CommitLineData
e448b12c 1/*
9dd0b194 2 * arch/arm/mach-orion5x/db88f5281-setup.c
e448b12c
TP		 3 *
4 * Marvell Orion-2 Development Board Setup
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
159ffb3a
LB		 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
e448b12c
TP		 10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mtd/nand.h>
20#include <linux/timer.h>
21#include <linux/mv643xx_eth.h>
22#include <linux/i2c.h>
23#include <asm/mach-types.h>
24#include <asm/gpio.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/pci.h>
9dd0b194 27#include <asm/arch/orion5x.h>
5d4294c5 28#include <asm/plat-orion/orion_nand.h>
e448b12c
TP		 29#include "common.h"
30
31/*****************************************************************************
32 * DB-88F5281 on board devices
33 ****************************************************************************/
34
35/*
36 * 512K NOR flash Device bus boot chip select
37 */
38
39#define DB88F5281_NOR_BOOT_BASE 0xf4000000
40#define DB88F5281_NOR_BOOT_SIZE SZ_512K
41
42/*
43 * 7-Segment on Device bus chip select 0
44 */
45
46#define DB88F5281_7SEG_BASE 0xfa000000
47#define DB88F5281_7SEG_SIZE SZ_1K
48
49/*
50 * 32M NOR flash on Device bus chip select 1
51 */
52
53#define DB88F5281_NOR_BASE 0xfc000000
54#define DB88F5281_NOR_SIZE SZ_32M
55
56/*
57 * 32M NAND flash on Device bus chip select 2
58 */
59
60#define DB88F5281_NAND_BASE 0xfa800000
61#define DB88F5281_NAND_SIZE SZ_1K
62
63/*
64 * PCI
65 */
66
67#define DB88F5281_PCI_SLOT0_OFFS 7
68#define DB88F5281_PCI_SLOT0_IRQ_PIN 12
69#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
70
71/*****************************************************************************
72 * 512M NOR Flash on Device bus Boot CS
73 ****************************************************************************/
74
75static struct physmap_flash_data db88f5281_boot_flash_data = {
76 .width = 1, /* 8 bit bus width */
77};
78
79static struct resource db88f5281_boot_flash_resource = {
80 .flags = IORESOURCE_MEM,
81 .start = DB88F5281_NOR_BOOT_BASE,
82 .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
83};
84
85static struct platform_device db88f5281_boot_flash = {
86 .name = "physmap-flash",
87 .id = 0,
88 .dev = {
e7068ad3 89 .platform_data = &db88f5281_boot_flash_data,
e448b12c
TP		 90 },
91 .num_resources = 1,
92 .resource = &db88f5281_boot_flash_resource,
93};
94
95/*****************************************************************************
96 * 32M NOR Flash on Device bus CS1
97 ****************************************************************************/
98
99static struct physmap_flash_data db88f5281_nor_flash_data = {
100 .width = 4, /* 32 bit bus width */
101};
102
103static struct resource db88f5281_nor_flash_resource = {
104 .flags = IORESOURCE_MEM,
105 .start = DB88F5281_NOR_BASE,
106 .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
107};
108
109static struct platform_device db88f5281_nor_flash = {
110 .name = "physmap-flash",
111 .id = 1,
112 .dev = {
e7068ad3 113 .platform_data = &db88f5281_nor_flash_data,
e448b12c
TP		 114 },
115 .num_resources = 1,
116 .resource = &db88f5281_nor_flash_resource,
117};
118
119/*****************************************************************************
120 * 32M NAND Flash on Device bus CS2
121 ****************************************************************************/
122
123static struct mtd_partition db88f5281_nand_parts[] = {
124 {
125 .name = "kernel",
126 .offset = 0,
127 .size = SZ_2M,
e7068ad3 128 }, {
e448b12c
TP		 129 .name = "root",
130 .offset = SZ_2M,
131 .size = (SZ_16M - SZ_2M),
e7068ad3 132 }, {
e448b12c
TP		 133 .name = "user",
134 .offset = SZ_16M,
135 .size = SZ_8M,
e7068ad3 136 }, {
e448b12c
TP		 137 .name = "recovery",
138 .offset = (SZ_16M + SZ_8M),
139 .size = SZ_8M,
140 },
141};
142
143static struct resource db88f5281_nand_resource = {
144 .flags = IORESOURCE_MEM,
145 .start = DB88F5281_NAND_BASE,
146 .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
147};
148
149static struct orion_nand_data db88f5281_nand_data = {
150 .parts = db88f5281_nand_parts,
151 .nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
152 .cle = 0,
153 .ale = 1,
154 .width = 8,
155};
156
157static struct platform_device db88f5281_nand_flash = {
158 .name = "orion_nand",
159 .id = -1,
160 .dev = {
161 .platform_data = &db88f5281_nand_data,
162 },
163 .resource = &db88f5281_nand_resource,
164 .num_resources = 1,
165};
166
167/*****************************************************************************
168 * 7-Segment on Device bus CS0
169 * Dummy counter every 2 sec
170 ****************************************************************************/
171
172static void __iomem *db88f5281_7seg;
173static struct timer_list db88f5281_timer;
174
175static void db88f5281_7seg_event(unsigned long data)
176{
177 static int count = 0;
178 writel(0, db88f5281_7seg + (count << 4));
179 count = (count + 1) & 7;
180 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
181}
182
183static int __init db88f5281_7seg_init(void)
184{
185 if (machine_is_db88f5281()) {
186 db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
187 DB88F5281_7SEG_SIZE);
188 if (!db88f5281_7seg) {
189 printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
190 return -EIO;
191 }
192 setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
193 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
194 }
195
196 return 0;
197}
198
199__initcall(db88f5281_7seg_init);
200
201/*****************************************************************************
202 * PCI
203 ****************************************************************************/
204
205void __init db88f5281_pci_preinit(void)
206{
207 int pin;
208
209 /*
210 * Configure PCI GPIO IRQ pins
211 */
212 pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
213 if (gpio_request(pin, "PCI Int1") == 0) {
214 if (gpio_direction_input(pin) == 0) {
215 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
216 } else {
217 printk(KERN_ERR "db88f5281_pci_preinit faield to "
218 "set_irq_type pin %d\n", pin);
219 gpio_free(pin);
220 }
221 } else {
222 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
223 }
224
225 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
226 if (gpio_request(pin, "PCI Int2") == 0) {
227 if (gpio_direction_input(pin) == 0) {
228 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
229 } else {
230 printk(KERN_ERR "db88f5281_pci_preinit faield "
231 "to set_irq_type pin %d\n", pin);
232 gpio_free(pin);
233 }
234 } else {
235 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
236 }
237}
238
239static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
240{
92b913b0
LB		 241 int irq;
242
e448b12c 243 /*
92b913b0 244 * Check for devices with hard-wired IRQs.
e448b12c 245 */
92b913b0
LB		 246 irq = orion5x_pci_map_irq(dev, slot, pin);
247 if (irq != -1)
248 return irq;
e448b12c
TP		 249
250 /*
92b913b0 251 * PCI IRQs are connected via GPIOs.
e448b12c
TP		 252 */
253 switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
254 case 0:
255 return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
256 case 1:
257 case 2:
258 return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
259 default:
260 return -1;
261 }
262}
263
264static struct hw_pci db88f5281_pci __initdata = {
265 .nr_controllers = 2,
266 .preinit = db88f5281_pci_preinit,
267 .swizzle = pci_std_swizzle,
9dd0b194
LB		 268 .setup = orion5x_pci_sys_setup,
269 .scan = orion5x_pci_sys_scan_bus,
e448b12c
TP		 270 .map_irq = db88f5281_pci_map_irq,
271};
272
273static int __init db88f5281_pci_init(void)
274{
275 if (machine_is_db88f5281())
276 pci_common_init(&db88f5281_pci);
277
278 return 0;
279}
280
281subsys_initcall(db88f5281_pci_init);
282
283/*****************************************************************************
284 * Ethernet
285 ****************************************************************************/
286static struct mv643xx_eth_platform_data db88f5281_eth_data = {
287 .phy_addr = 8,
288 .force_phy_addr = 1,
289};
290
291/*****************************************************************************
292 * RTC DS1339 on I2C bus
293 ****************************************************************************/
294static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
3760f736 295 I2C_BOARD_INFO("ds1339", 0x68),
e448b12c
TP		 296};
297
298/*****************************************************************************
299 * General Setup
300 ****************************************************************************/
e448b12c
TP		 301static void __init db88f5281_init(void)
302{
303 /*
304 * Basic Orion setup. Need to be called early.
305 */
9dd0b194 306 orion5x_init();
e448b12c 307
e448b12c
TP		 308 /*
309 * Setup Multiplexing Pins:
310 * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input)
311 * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2]
312 * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3]
313 * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1)
314 * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3)
315 * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator)
316 * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2)
317 * MPP14: NAND_REn[2] MPP15: NAND_WEn[2]
318 * MPP16: UART1_RX MPP17: UART1_TX
319 * MPP18: UART1_CTS MPP19: UART1_RTS
320 * MPP-DEV: DEV_D[16:31]
321 */
9dd0b194
LB		 322 orion5x_write(MPP_0_7_CTRL, 0x00222203);
323 orion5x_write(MPP_8_15_CTRL, 0x44000000);
324 orion5x_write(MPP_16_19_CTRL, 0);
325 orion5x_write(MPP_DEV_CTRL, 0);
e448b12c 326
9dd0b194 327 orion5x_gpio_set_valid_pins(0x00003fc3);
e448b12c 328
044f6c7c
LB		 329 /*
330 * Configure peripherals.
331 */
332 orion5x_ehci0_init();
9dd0b194 333 orion5x_eth_init(&db88f5281_eth_data);
044f6c7c
LB		 334 orion5x_i2c_init();
335 orion5x_uart0_init();
336 orion5x_uart1_init();
337
338 orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
339 DB88F5281_NOR_BOOT_SIZE);
340 platform_device_register(&db88f5281_boot_flash);
341
342 orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
343
344 orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
345 platform_device_register(&db88f5281_nor_flash);
346
347 orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
348 platform_device_register(&db88f5281_nand_flash);
349
350 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
e448b12c
TP		 351}
352
353MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
354 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
9dd0b194
LB		 355 .phys_io = ORION5X_REGS_PHYS_BASE,
356 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
e448b12c
TP		 357 .boot_params = 0x00000100,
358 .init_machine = db88f5281_init,
9dd0b194
LB		 359 .map_io = orion5x_map_io,
360 .init_irq = orion5x_init_irq,
361 .timer = &orion5x_timer,
e448b12c 362MACHINE_END
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