[deliverable/linux.git] / arch / arm / mach-orion5x / db88f5281-setup.c

/*
 * arch/arm/mach-orion5x/db88f5281-setup.c
 *
 * Marvell Orion-2 Development Board Setup
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/timer.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion5x.h>
#include <asm/plat-orion/orion_nand.h>
#include "common.h"

/*****************************************************************************
 * DB-88F5281 on board devices
 ****************************************************************************/

/*
 * 512K NOR flash Device bus boot chip select
 */

#define DB88F5281_NOR_BOOT_BASE		0xf4000000
#define DB88F5281_NOR_BOOT_SIZE		SZ_512K

/*
 * 7-Segment on Device bus chip select 0
 */

#define DB88F5281_7SEG_BASE		0xfa000000
#define DB88F5281_7SEG_SIZE		SZ_1K

/*
 * 32M NOR flash on Device bus chip select 1
 */

#define DB88F5281_NOR_BASE		0xfc000000
#define DB88F5281_NOR_SIZE		SZ_32M

/*
 * 32M NAND flash on Device bus chip select 2
 */

#define DB88F5281_NAND_BASE		0xfa800000
#define DB88F5281_NAND_SIZE		SZ_1K

/*
 * PCI
 */

#define DB88F5281_PCI_SLOT0_OFFS		7
#define DB88F5281_PCI_SLOT0_IRQ_PIN		12
#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN	13

/*****************************************************************************
 * 512M NOR Flash on Device bus Boot CS
 ****************************************************************************/

static struct physmap_flash_data db88f5281_boot_flash_data = {
	.width		= 1,	/* 8 bit bus width */
};

static struct resource db88f5281_boot_flash_resource = {
	.flags		= IORESOURCE_MEM,
	.start		= DB88F5281_NOR_BOOT_BASE,
	.end		= DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
};

static struct platform_device db88f5281_boot_flash = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &db88f5281_boot_flash_data,
	},
	.num_resources	= 1,
	.resource	= &db88f5281_boot_flash_resource,
};

/*****************************************************************************
 * 32M NOR Flash on Device bus CS1
 ****************************************************************************/

static struct physmap_flash_data db88f5281_nor_flash_data = {
	.width		= 4,	/* 32 bit bus width */
};

static struct resource db88f5281_nor_flash_resource = {
	.flags		= IORESOURCE_MEM,
	.start		= DB88F5281_NOR_BASE,
	.end		= DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
};

static struct platform_device db88f5281_nor_flash = {
	.name		= "physmap-flash",
	.id		= 1,
	.dev		= {
		.platform_data	= &db88f5281_nor_flash_data,
	},
	.num_resources	= 1,
	.resource	= &db88f5281_nor_flash_resource,
};

/*****************************************************************************
 * 32M NAND Flash on Device bus CS2
 ****************************************************************************/

static struct mtd_partition db88f5281_nand_parts[] = {
	{
		.name = "kernel",
		.offset = 0,
		.size = SZ_2M,
	}, {
		.name = "root",
		.offset = SZ_2M,
		.size = (SZ_16M - SZ_2M),
	}, {
		.name = "user",
		.offset = SZ_16M,
		.size = SZ_8M,
	}, {
		.name = "recovery",
		.offset = (SZ_16M + SZ_8M),
		.size = SZ_8M,
	},
};

static struct resource db88f5281_nand_resource = {
	.flags		= IORESOURCE_MEM,
	.start		= DB88F5281_NAND_BASE,
	.end		= DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
};

static struct orion_nand_data db88f5281_nand_data = {
	.parts		= db88f5281_nand_parts,
	.nr_parts	= ARRAY_SIZE(db88f5281_nand_parts),
	.cle		= 0,
	.ale		= 1,
	.width		= 8,
};

static struct platform_device db88f5281_nand_flash = {
	.name		= "orion_nand",
	.id		= -1,
	.dev		= {
		.platform_data	= &db88f5281_nand_data,
	},
	.resource	= &db88f5281_nand_resource,
	.num_resources	= 1,
};

/*****************************************************************************
 * 7-Segment on Device bus CS0
 * Dummy counter every 2 sec
 ****************************************************************************/

static void __iomem *db88f5281_7seg;
static struct timer_list db88f5281_timer;

static void db88f5281_7seg_event(unsigned long data)
{
	static int count = 0;
	writel(0, db88f5281_7seg + (count << 4));
	count = (count + 1) & 7;
	mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
}

static int __init db88f5281_7seg_init(void)
{
	if (machine_is_db88f5281()) {
		db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
					DB88F5281_7SEG_SIZE);
		if (!db88f5281_7seg) {
			printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
			return -EIO;
		}
		setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
		mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
	}

	return 0;
}

__initcall(db88f5281_7seg_init);

/*****************************************************************************
 * PCI
 ****************************************************************************/

void __init db88f5281_pci_preinit(void)
{
	int pin;

	/*
	 * Configure PCI GPIO IRQ pins
	 */
	pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
	if (gpio_request(pin, "PCI Int1") == 0) {
		if (gpio_direction_input(pin) == 0) {
			set_irq_type(gpio_to_irq(pin), IRQT_LOW);
		} else {
			printk(KERN_ERR "db88f5281_pci_preinit faield to "
					"set_irq_type pin %d\n", pin);
			gpio_free(pin);
		}
	} else {
		printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
	}

	pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
	if (gpio_request(pin, "PCI Int2") == 0) {
		if (gpio_direction_input(pin) == 0) {
			set_irq_type(gpio_to_irq(pin), IRQT_LOW);
		} else {
			printk(KERN_ERR "db88f5281_pci_preinit faield "
					"to set_irq_type pin %d\n", pin);
			gpio_free(pin);
		}
	} else {
		printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
	}
}

static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	/*
	 * Check for devices with hard-wired IRQs.
	 */
	irq = orion5x_pci_map_irq(dev, slot, pin);
	if (irq != -1)
		return irq;

	/*
	 * PCI IRQs are connected via GPIOs.
	 */
	switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
	case 0:
		return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
	case 1:
	case 2:
		return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
	default:
		return -1;
	}
}

static struct hw_pci db88f5281_pci __initdata = {
	.nr_controllers	= 2,
	.preinit	= db88f5281_pci_preinit,
	.swizzle	= pci_std_swizzle,
	.setup		= orion5x_pci_sys_setup,
	.scan		= orion5x_pci_sys_scan_bus,
	.map_irq	= db88f5281_pci_map_irq,
};

static int __init db88f5281_pci_init(void)
{
	if (machine_is_db88f5281())
		pci_common_init(&db88f5281_pci);

	return 0;
}

subsys_initcall(db88f5281_pci_init);

/*****************************************************************************
 * Ethernet
 ****************************************************************************/
static struct mv643xx_eth_platform_data db88f5281_eth_data = {
	.phy_addr	= 8,
	.force_phy_addr = 1,
};

/*****************************************************************************
 * RTC DS1339 on I2C bus
 ****************************************************************************/
static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
	I2C_BOARD_INFO("ds1339", 0x68),
};

/*****************************************************************************
 * General Setup
 ****************************************************************************/

static struct platform_device *db88f5281_devs[] __initdata = {
	&db88f5281_boot_flash,
	&db88f5281_nor_flash,
	&db88f5281_nand_flash,
};

static void __init db88f5281_init(void)
{
	/*
	 * Basic Orion setup. Need to be called early.
	 */
	orion5x_init();

	/*
	 * Setup the CPU address decode windows for our on-board devices
	 */
	orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
				DB88F5281_NOR_BOOT_SIZE);
	orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
	orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
	orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);

	/*
	 * Setup Multiplexing Pins:
	 * MPP0: GPIO (USB Over Current)	MPP1: GPIO (USB Vbat input)
	 * MPP2: PCI_REQn[2]			MPP3: PCI_GNTn[2]
	 * MPP4: PCI_REQn[3]			MPP5: PCI_GNTn[3]
	 * MPP6: GPIO (JP0, CON17.2)		MPP7: GPIO (JP1, CON17.1)
	 * MPP8: GPIO (JP2, CON11.2)		MPP9: GPIO (JP3, CON11.3)
	 * MPP10: GPIO (RTC int)		MPP11: GPIO (Baud Rate Generator)
	 * MPP12: GPIO (PCI int 1)		MPP13: GPIO (PCI int 2)
	 * MPP14: NAND_REn[2]			MPP15: NAND_WEn[2]
	 * MPP16: UART1_RX			MPP17: UART1_TX
	 * MPP18: UART1_CTS			MPP19: UART1_RTS
	 * MPP-DEV: DEV_D[16:31]
	 */
	orion5x_write(MPP_0_7_CTRL, 0x00222203);
	orion5x_write(MPP_8_15_CTRL, 0x44000000);
	orion5x_write(MPP_16_19_CTRL, 0);
	orion5x_write(MPP_DEV_CTRL, 0);

	orion5x_gpio_set_valid_pins(0x00003fc3);

	platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
	i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
	orion5x_eth_init(&db88f5281_eth_data);
}

MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
	/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
	.phys_io	= ORION5X_REGS_PHYS_BASE,
	.io_pg_offst	= ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
	.boot_params	= 0x00000100,
	.init_machine	= db88f5281_init,
	.map_io		= orion5x_map_io,
	.init_irq	= orion5x_init_irq,
	.timer		= &orion5x_timer,
MACHINE_END
Commit	Line	Data
e448b12c	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/db88f5281-setup.c
e448b12c TP	3	*
	4	* Marvell Orion-2 Development Board Setup
	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
e448b12c TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/pci.h>
	17	#include <linux/irq.h>
	18	#include <linux/mtd/physmap.h>
	19	#include <linux/mtd/nand.h>
	20	#include <linux/timer.h>
	21	#include <linux/mv643xx_eth.h>
	22	#include <linux/i2c.h>
	23	#include <asm/mach-types.h>
	24	#include <asm/gpio.h>
	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/pci.h>
9dd0b194	27	#include <asm/arch/orion5x.h>
5d4294c5	28	#include <asm/plat-orion/orion_nand.h>
e448b12c TP	29	#include "common.h"
	30
	31	/*****************************************************************************
	32	* DB-88F5281 on board devices
	33	****************************************************************************/
	34
	35	/*
	36	* 512K NOR flash Device bus boot chip select
	37	*/
	38
	39	#define DB88F5281_NOR_BOOT_BASE 0xf4000000
	40	#define DB88F5281_NOR_BOOT_SIZE SZ_512K
	41
	42	/*
	43	* 7-Segment on Device bus chip select 0
	44	*/
	45
	46	#define DB88F5281_7SEG_BASE 0xfa000000
	47	#define DB88F5281_7SEG_SIZE SZ_1K
	48
	49	/*
	50	* 32M NOR flash on Device bus chip select 1
	51	*/
	52
	53	#define DB88F5281_NOR_BASE 0xfc000000
	54	#define DB88F5281_NOR_SIZE SZ_32M
	55
	56	/*
	57	* 32M NAND flash on Device bus chip select 2
	58	*/
	59
	60	#define DB88F5281_NAND_BASE 0xfa800000
	61	#define DB88F5281_NAND_SIZE SZ_1K
	62
	63	/*
	64	* PCI
	65	*/
	66
	67	#define DB88F5281_PCI_SLOT0_OFFS 7
	68	#define DB88F5281_PCI_SLOT0_IRQ_PIN 12
	69	#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
	70
	71	/*****************************************************************************
	72	* 512M NOR Flash on Device bus Boot CS
	73	****************************************************************************/
	74
	75	static struct physmap_flash_data db88f5281_boot_flash_data = {
	76	.width = 1, /* 8 bit bus width */
	77	};
	78
	79	static struct resource db88f5281_boot_flash_resource = {
	80	.flags = IORESOURCE_MEM,
	81	.start = DB88F5281_NOR_BOOT_BASE,
	82	.end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
	83	};
	84
	85	static struct platform_device db88f5281_boot_flash = {
	86	.name = "physmap-flash",
	87	.id = 0,
	88	.dev = {
e7068ad3	89	.platform_data = &db88f5281_boot_flash_data,
e448b12c TP	90	},
	91	.num_resources = 1,
	92	.resource = &db88f5281_boot_flash_resource,
	93	};
	94
	95	/*****************************************************************************
	96	* 32M NOR Flash on Device bus CS1
	97	****************************************************************************/
	98
	99	static struct physmap_flash_data db88f5281_nor_flash_data = {
	100	.width = 4, /* 32 bit bus width */
	101	};
	102
	103	static struct resource db88f5281_nor_flash_resource = {
	104	.flags = IORESOURCE_MEM,
	105	.start = DB88F5281_NOR_BASE,
	106	.end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
	107	};
	108
	109	static struct platform_device db88f5281_nor_flash = {
	110	.name = "physmap-flash",
	111	.id = 1,
	112	.dev = {
e7068ad3	113	.platform_data = &db88f5281_nor_flash_data,
e448b12c TP	114	},
	115	.num_resources = 1,
	116	.resource = &db88f5281_nor_flash_resource,
	117	};
	118
	119	/*****************************************************************************
	120	* 32M NAND Flash on Device bus CS2
	121	****************************************************************************/
	122
	123	static struct mtd_partition db88f5281_nand_parts[] = {
	124	{
	125	.name = "kernel",
	126	.offset = 0,
	127	.size = SZ_2M,
e7068ad3	128	}, {
e448b12c TP	129	.name = "root",
	130	.offset = SZ_2M,
	131	.size = (SZ_16M - SZ_2M),
e7068ad3	132	}, {
e448b12c TP	133	.name = "user",
	134	.offset = SZ_16M,
	135	.size = SZ_8M,
e7068ad3	136	}, {
e448b12c TP	137	.name = "recovery",
	138	.offset = (SZ_16M + SZ_8M),
	139	.size = SZ_8M,
	140	},
	141	};
	142
	143	static struct resource db88f5281_nand_resource = {
	144	.flags = IORESOURCE_MEM,
	145	.start = DB88F5281_NAND_BASE,
	146	.end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
	147	};
	148
	149	static struct orion_nand_data db88f5281_nand_data = {
	150	.parts = db88f5281_nand_parts,
	151	.nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
	152	.cle = 0,
	153	.ale = 1,
	154	.width = 8,
	155	};
	156
	157	static struct platform_device db88f5281_nand_flash = {
	158	.name = "orion_nand",
	159	.id = -1,
	160	.dev = {
	161	.platform_data = &db88f5281_nand_data,
	162	},
	163	.resource = &db88f5281_nand_resource,
	164	.num_resources = 1,
	165	};
	166
	167	/*****************************************************************************
	168	* 7-Segment on Device bus CS0
	169	* Dummy counter every 2 sec
	170	****************************************************************************/
	171
	172	static void __iomem *db88f5281_7seg;
	173	static struct timer_list db88f5281_timer;
	174
	175	static void db88f5281_7seg_event(unsigned long data)
	176	{
	177	static int count = 0;
	178	writel(0, db88f5281_7seg + (count << 4));
	179	count = (count + 1) & 7;
	180	mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
	181	}
	182
	183	static int __init db88f5281_7seg_init(void)
	184	{
	185	if (machine_is_db88f5281()) {
	186	db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
	187	DB88F5281_7SEG_SIZE);
	188	if (!db88f5281_7seg) {
	189	printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
	190	return -EIO;
	191	}
	192	setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
	193	mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
	194	}
	195
	196	return 0;
	197	}
	198
	199	__initcall(db88f5281_7seg_init);
	200
201	/*****************************************************************************
202	* PCI
203	****************************************************************************/
204
205	void __init db88f5281_pci_preinit(void)
206	{
207	int pin;
208
209	/*
210	* Configure PCI GPIO IRQ pins
211	*/
212	pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
213	if (gpio_request(pin, "PCI Int1") == 0) {
214	if (gpio_direction_input(pin) == 0) {
215	set_irq_type(gpio_to_irq(pin), IRQT_LOW);
216	} else {
217	printk(KERN_ERR "db88f5281_pci_preinit faield to "
218	"set_irq_type pin %d\n", pin);
219	gpio_free(pin);
220	}
221	} else {
222	printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
223	}
224
225	pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
226	if (gpio_request(pin, "PCI Int2") == 0) {
227	if (gpio_direction_input(pin) == 0) {
228	set_irq_type(gpio_to_irq(pin), IRQT_LOW);
229	} else {
230	printk(KERN_ERR "db88f5281_pci_preinit faield "
231	"to set_irq_type pin %d\n", pin);
232	gpio_free(pin);
233	}
234	} else {
235	printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
236	}
237	}
238
239	static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
240	{
92b913b0 LB	241	int irq;
92b913b0 LB	242
e448b12c	243	/*
92b913b0	244	* Check for devices with hard-wired IRQs.
e448b12c	245	*/
92b913b0 LB	246	irq = orion5x_pci_map_irq(dev, slot, pin);
	247	if (irq != -1)
	248	return irq;
e448b12c TP	249
e448b12c TP	250	/*
92b913b0	251	* PCI IRQs are connected via GPIOs.
e448b12c TP	252	*/
	253	switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
	254	case 0:
	255	return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
	256	case 1:
	257	case 2:
	258	return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
	259	default:
	260	return -1;
	261	}
	262	}
	263
	264	static struct hw_pci db88f5281_pci __initdata = {
	265	.nr_controllers = 2,
	266	.preinit = db88f5281_pci_preinit,
	267	.swizzle = pci_std_swizzle,
9dd0b194 LB	268	.setup = orion5x_pci_sys_setup,
9dd0b194 LB	269	.scan = orion5x_pci_sys_scan_bus,
e448b12c TP	270	.map_irq = db88f5281_pci_map_irq,
	271	};
	272
	273	static int __init db88f5281_pci_init(void)
	274	{
	275	if (machine_is_db88f5281())
	276	pci_common_init(&db88f5281_pci);
	277
	278	return 0;
	279	}
	280
	281	subsys_initcall(db88f5281_pci_init);
	282
	283	/*****************************************************************************
	284	* Ethernet
	285	****************************************************************************/
	286	static struct mv643xx_eth_platform_data db88f5281_eth_data = {
	287	.phy_addr = 8,
	288	.force_phy_addr = 1,
	289	};
	290
	291	/*****************************************************************************
	292	* RTC DS1339 on I2C bus
	293	****************************************************************************/
	294	static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
3760f736	295	I2C_BOARD_INFO("ds1339", 0x68),
e448b12c TP	296	};
	297
	298	/*****************************************************************************
	299	* General Setup
	300	****************************************************************************/
	301
	302	static struct platform_device *db88f5281_devs[] __initdata = {
	303	&db88f5281_boot_flash,
	304	&db88f5281_nor_flash,
	305	&db88f5281_nand_flash,
	306	};
	307
	308	static void __init db88f5281_init(void)
	309	{
	310	/*
	311	* Basic Orion setup. Need to be called early.
	312	*/
9dd0b194	313	orion5x_init();
e448b12c TP	314
	315	/*
	316	* Setup the CPU address decode windows for our on-board devices
	317	*/
9dd0b194	318	orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
98f79d1e	319	DB88F5281_NOR_BOOT_SIZE);
9dd0b194 LB	320	orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
	321	orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
	322	orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
e448b12c TP	323
	324	/*
	325	* Setup Multiplexing Pins:
	326	* MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input)
	327	* MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2]
	328	* MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3]
	329	* MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1)
	330	* MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3)
	331	* MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator)
	332	* MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2)
	333	* MPP14: NAND_REn[2] MPP15: NAND_WEn[2]
	334	* MPP16: UART1_RX MPP17: UART1_TX
	335	* MPP18: UART1_CTS MPP19: UART1_RTS
	336	* MPP-DEV: DEV_D[16:31]
	337	*/
9dd0b194 LB	338	orion5x_write(MPP_0_7_CTRL, 0x00222203);
	339	orion5x_write(MPP_8_15_CTRL, 0x44000000);
	340	orion5x_write(MPP_16_19_CTRL, 0);
	341	orion5x_write(MPP_DEV_CTRL, 0);
e448b12c	342
9dd0b194	343	orion5x_gpio_set_valid_pins(0x00003fc3);
e448b12c TP	344
	345	platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
	346	i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
9dd0b194	347	orion5x_eth_init(&db88f5281_eth_data);
e448b12c TP	348	}
	349
	350	MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
	351	/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
9dd0b194 LB	352	.phys_io = ORION5X_REGS_PHYS_BASE,
9dd0b194 LB	353	.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
e448b12c TP	354	.boot_params = 0x00000100,
e448b12c TP	355	.init_machine = db88f5281_init,
9dd0b194 LB	356	.map_io = orion5x_map_io,
	357	.init_irq = orion5x_init_irq,
	358	.timer = &orion5x_timer,
e448b12c	359	MACHINE_END