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ARM: gpio: at91: remove redundant include of mach/gpio.h
[deliverable/linux.git] / arch / arm / mach-orion5x / db88f5281-setup.c
CommitLineData
e448b12c 1/*
9dd0b194 2 * arch/arm/mach-orion5x/db88f5281-setup.c
e448b12c
TP		 3 *
4 * Marvell Orion-2 Development Board Setup
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
159ffb3a
LB		 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
e448b12c
TP		 10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mtd/nand.h>
20#include <linux/timer.h>
21#include <linux/mv643xx_eth.h>
22#include <linux/i2c.h>
23#include <asm/mach-types.h>
24#include <asm/gpio.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/pci.h>
a09e64fb 27#include <mach/orion5x.h>
6f088f1d 28#include <plat/orion_nand.h>
e448b12c 29#include "common.h"
19cfd5c0 30#include "mpp.h"
e448b12c
TP		 31
32/*****************************************************************************
33 * DB-88F5281 on board devices
34 ****************************************************************************/
35
36/*
37 * 512K NOR flash Device bus boot chip select
38 */
39
40#define DB88F5281_NOR_BOOT_BASE 0xf4000000
41#define DB88F5281_NOR_BOOT_SIZE SZ_512K
42
43/*
44 * 7-Segment on Device bus chip select 0
45 */
46
47#define DB88F5281_7SEG_BASE 0xfa000000
48#define DB88F5281_7SEG_SIZE SZ_1K
49
50/*
51 * 32M NOR flash on Device bus chip select 1
52 */
53
54#define DB88F5281_NOR_BASE 0xfc000000
55#define DB88F5281_NOR_SIZE SZ_32M
56
57/*
58 * 32M NAND flash on Device bus chip select 2
59 */
60
61#define DB88F5281_NAND_BASE 0xfa800000
62#define DB88F5281_NAND_SIZE SZ_1K
63
64/*
65 * PCI
66 */
67
68#define DB88F5281_PCI_SLOT0_OFFS 7
69#define DB88F5281_PCI_SLOT0_IRQ_PIN 12
70#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
71
72/*****************************************************************************
73 * 512M NOR Flash on Device bus Boot CS
74 ****************************************************************************/
75
76static struct physmap_flash_data db88f5281_boot_flash_data = {
77 .width = 1, /* 8 bit bus width */
78};
79
80static struct resource db88f5281_boot_flash_resource = {
81 .flags = IORESOURCE_MEM,
82 .start = DB88F5281_NOR_BOOT_BASE,
83 .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
84};
85
86static struct platform_device db88f5281_boot_flash = {
87 .name = "physmap-flash",
88 .id = 0,
89 .dev = {
e7068ad3 90 .platform_data = &db88f5281_boot_flash_data,
e448b12c
TP		 91 },
92 .num_resources = 1,
93 .resource = &db88f5281_boot_flash_resource,
94};
95
96/*****************************************************************************
97 * 32M NOR Flash on Device bus CS1
98 ****************************************************************************/
99
100static struct physmap_flash_data db88f5281_nor_flash_data = {
101 .width = 4, /* 32 bit bus width */
102};
103
104static struct resource db88f5281_nor_flash_resource = {
105 .flags = IORESOURCE_MEM,
106 .start = DB88F5281_NOR_BASE,
107 .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
108};
109
110static struct platform_device db88f5281_nor_flash = {
111 .name = "physmap-flash",
112 .id = 1,
113 .dev = {
e7068ad3 114 .platform_data = &db88f5281_nor_flash_data,
e448b12c
TP		 115 },
116 .num_resources = 1,
117 .resource = &db88f5281_nor_flash_resource,
118};
119
120/*****************************************************************************
121 * 32M NAND Flash on Device bus CS2
122 ****************************************************************************/
123
124static struct mtd_partition db88f5281_nand_parts[] = {
125 {
126 .name = "kernel",
127 .offset = 0,
128 .size = SZ_2M,
e7068ad3 129 }, {
e448b12c
TP		 130 .name = "root",
131 .offset = SZ_2M,
132 .size = (SZ_16M - SZ_2M),
e7068ad3 133 }, {
e448b12c
TP		 134 .name = "user",
135 .offset = SZ_16M,
136 .size = SZ_8M,
e7068ad3 137 }, {
e448b12c
TP		 138 .name = "recovery",
139 .offset = (SZ_16M + SZ_8M),
140 .size = SZ_8M,
141 },
142};
143
144static struct resource db88f5281_nand_resource = {
145 .flags = IORESOURCE_MEM,
146 .start = DB88F5281_NAND_BASE,
147 .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
148};
149
150static struct orion_nand_data db88f5281_nand_data = {
151 .parts = db88f5281_nand_parts,
152 .nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
153 .cle = 0,
154 .ale = 1,
155 .width = 8,
156};
157
158static struct platform_device db88f5281_nand_flash = {
159 .name = "orion_nand",
160 .id = -1,
161 .dev = {
162 .platform_data = &db88f5281_nand_data,
163 },
164 .resource = &db88f5281_nand_resource,
165 .num_resources = 1,
166};
167
168/*****************************************************************************
169 * 7-Segment on Device bus CS0
170 * Dummy counter every 2 sec
171 ****************************************************************************/
172
173static void __iomem *db88f5281_7seg;
174static struct timer_list db88f5281_timer;
175
176static void db88f5281_7seg_event(unsigned long data)
177{
178 static int count = 0;
179 writel(0, db88f5281_7seg + (count << 4));
180 count = (count + 1) & 7;
181 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
182}
183
184static int __init db88f5281_7seg_init(void)
185{
186 if (machine_is_db88f5281()) {
187 db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
188 DB88F5281_7SEG_SIZE);
189 if (!db88f5281_7seg) {
190 printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
191 return -EIO;
192 }
193 setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
194 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
195 }
196
197 return 0;
198}
199
200__initcall(db88f5281_7seg_init);
201
202/*****************************************************************************
203 * PCI
204 ****************************************************************************/
205
206void __init db88f5281_pci_preinit(void)
207{
208 int pin;
209
210 /*
211 * Configure PCI GPIO IRQ pins
212 */
213 pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
214 if (gpio_request(pin, "PCI Int1") == 0) {
215 if (gpio_direction_input(pin) == 0) {
6845664a 216 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
e448b12c
TP		 217 } else {
218 printk(KERN_ERR "db88f5281_pci_preinit faield to "
219 "set_irq_type pin %d\n", pin);
220 gpio_free(pin);
221 }
222 } else {
223 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
224 }
225
226 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
227 if (gpio_request(pin, "PCI Int2") == 0) {
228 if (gpio_direction_input(pin) == 0) {
6845664a 229 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
e448b12c
TP		 230 } else {
231 printk(KERN_ERR "db88f5281_pci_preinit faield "
232 "to set_irq_type pin %d\n", pin);
233 gpio_free(pin);
234 }
235 } else {
236 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
237 }
238}
239
d5341942
RB		 240static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot,
241 u8 pin)
e448b12c 242{
92b913b0
LB		 243 int irq;
244
e448b12c 245 /*
92b913b0 246 * Check for devices with hard-wired IRQs.
e448b12c 247 */
92b913b0
LB		 248 irq = orion5x_pci_map_irq(dev, slot, pin);
249 if (irq != -1)
250 return irq;
e448b12c
TP		 251
252 /*
92b913b0 253 * PCI IRQs are connected via GPIOs.
e448b12c
TP		 254 */
255 switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
256 case 0:
257 return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
258 case 1:
259 case 2:
260 return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
261 default:
262 return -1;
263 }
264}
265
266static struct hw_pci db88f5281_pci __initdata = {
267 .nr_controllers = 2,
268 .preinit = db88f5281_pci_preinit,
269 .swizzle = pci_std_swizzle,
9dd0b194
LB		 270 .setup = orion5x_pci_sys_setup,
271 .scan = orion5x_pci_sys_scan_bus,
e448b12c
TP		 272 .map_irq = db88f5281_pci_map_irq,
273};
274
275static int __init db88f5281_pci_init(void)
276{
277 if (machine_is_db88f5281())
278 pci_common_init(&db88f5281_pci);
279
280 return 0;
281}
282
283subsys_initcall(db88f5281_pci_init);
284
285/*****************************************************************************
286 * Ethernet
287 ****************************************************************************/
288static struct mv643xx_eth_platform_data db88f5281_eth_data = {
ac840605 289 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
e448b12c
TP		 290};
291
292/*****************************************************************************
293 * RTC DS1339 on I2C bus
294 ****************************************************************************/
295static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
3760f736 296 I2C_BOARD_INFO("ds1339", 0x68),
e448b12c
TP		 297};
298
299/*****************************************************************************
300 * General Setup
301 ****************************************************************************/
554cdaef
AL		 302static unsigned int db88f5281_mpp_modes[] __initdata = {
303 MPP0_GPIO, /* USB Over Current */
304 MPP1_GPIO, /* USB Vbat input */
305 MPP2_PCI_ARB, /* PCI_REQn[2] */
306 MPP3_PCI_ARB, /* PCI_GNTn[2] */
307 MPP4_PCI_ARB, /* PCI_REQn[3] */
308 MPP5_PCI_ARB, /* PCI_GNTn[3] */
309 MPP6_GPIO, /* JP0, CON17.2 */
310 MPP7_GPIO, /* JP1, CON17.1 */
311 MPP8_GPIO, /* JP2, CON11.2 */
312 MPP9_GPIO, /* JP3, CON11.3 */
313 MPP10_GPIO, /* RTC int */
314 MPP11_GPIO, /* Baud Rate Generator */
315 MPP12_GPIO, /* PCI int 1 */
316 MPP13_GPIO, /* PCI int 2 */
317 MPP14_NAND, /* NAND_REn[2] */
318 MPP15_NAND, /* NAND_WEn[2] */
319 MPP16_UART, /* UART1_RX */
320 MPP17_UART, /* UART1_TX */
321 MPP18_UART, /* UART1_CTSn */
322 MPP19_UART, /* UART1_RTSn */
323 0,
19cfd5c0
LB		 324};
325
e448b12c
TP		 326static void __init db88f5281_init(void)
327{
328 /*
329 * Basic Orion setup. Need to be called early.
330 */
9dd0b194 331 orion5x_init();
e448b12c 332
19cfd5c0 333 orion5x_mpp_conf(db88f5281_mpp_modes);
79e90dd5 334 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
e448b12c 335
044f6c7c
LB		 336 /*
337 * Configure peripherals.
338 */
339 orion5x_ehci0_init();
9dd0b194 340 orion5x_eth_init(&db88f5281_eth_data);
044f6c7c
LB		 341 orion5x_i2c_init();
342 orion5x_uart0_init();
343 orion5x_uart1_init();
344
345 orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
346 DB88F5281_NOR_BOOT_SIZE);
347 platform_device_register(&db88f5281_boot_flash);
348
349 orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
350
351 orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
352 platform_device_register(&db88f5281_nor_flash);
353
354 orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
355 platform_device_register(&db88f5281_nand_flash);
356
357 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
e448b12c
TP		 358}
359
360MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
361 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
e448b12c
TP		 362 .boot_params = 0x00000100,
363 .init_machine = db88f5281_init,
9dd0b194 364 .map_io = orion5x_map_io,
4ee1f6b5 365 .init_early = orion5x_init_early,
9dd0b194
LB		 366 .init_irq = orion5x_init_irq,
367 .timer = &orion5x_timer,
e448b12c 368MACHINE_END
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