[deliverable/linux.git] / arch / arm / mach-orion5x / include / mach / orion5x.h

/*
 * arch/arm/mach-orion5x/include/mach/orion5x.h
 *
 * Generic definitions of Orion SoC flavors:
 *  Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __ASM_ARCH_ORION5X_H
#define __ASM_ARCH_ORION5X_H

#include <mach/irqs.h>

/*****************************************************************************
 * Orion Address Maps
 *
 * phys
 * e0000000	PCIe MEM space
 * e8000000	PCI MEM space
 * f0000000	PCIe WA space (Orion-1/Orion-NAS only)
 * f1000000	on-chip peripheral registers
 * f2000000	PCIe I/O space
 * f2100000	PCI I/O space
 * f2200000	SRAM dedicated for the crypto unit
 * f4000000	device bus mappings (boot)
 * fa000000	device bus mappings (cs0)
 * fa800000	device bus mappings (cs2)
 * fc000000	device bus mappings (cs0/cs1)
 *
 * virt		phys		size
 * fe000000	f1000000	1M	on-chip peripheral registers
 * fee00000	f2000000	64K	PCIe I/O space
 * fee10000	f2100000	64K	PCI I/O space
 * fd000000	f0000000	16M	PCIe WA space (Orion-1/Orion-NAS only)
 ****************************************************************************/
#define ORION5X_REGS_PHYS_BASE		0xf1000000
#define ORION5X_REGS_VIRT_BASE		IOMEM(0xfe000000)
#define ORION5X_REGS_SIZE		SZ_1M

#define ORION5X_PCIE_IO_PHYS_BASE	0xf2000000
#define ORION5X_PCIE_IO_BUS_BASE	0x00000000
#define ORION5X_PCIE_IO_SIZE		SZ_64K

#define ORION5X_PCI_IO_PHYS_BASE	0xf2100000
#define ORION5X_PCI_IO_BUS_BASE		0x00010000
#define ORION5X_PCI_IO_SIZE		SZ_64K

#define ORION5X_SRAM_PHYS_BASE		(0xf2200000)
#define ORION5X_SRAM_SIZE		SZ_8K

/* Relevant only for Orion-1/Orion-NAS */
#define ORION5X_PCIE_WA_PHYS_BASE	0xf0000000
#define ORION5X_PCIE_WA_VIRT_BASE	IOMEM(0xfd000000)
#define ORION5X_PCIE_WA_SIZE		SZ_16M

#define ORION5X_PCIE_MEM_PHYS_BASE	0xe0000000
#define ORION5X_PCIE_MEM_SIZE		SZ_128M

#define ORION5X_PCI_MEM_PHYS_BASE	0xe8000000
#define ORION5X_PCI_MEM_SIZE		SZ_128M

/*******************************************************************************
 * Orion Registers Map
 ******************************************************************************/

#define ORION5X_DDR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x00000)
#define  ORION5X_DDR_WINS_BASE          (ORION5X_DDR_PHYS_BASE + 0x1500)
#define  ORION5X_DDR_WINS_SZ            (0x10)
#define ORION5X_DDR_VIRT_BASE		(ORION5X_REGS_VIRT_BASE + 0x00000)
#define ORION5X_DEV_BUS_PHYS_BASE	(ORION5X_REGS_PHYS_BASE + 0x10000)
#define ORION5X_DEV_BUS_VIRT_BASE	(ORION5X_REGS_VIRT_BASE + 0x10000)
#define ORION5X_DEV_BUS_REG(x)		(ORION5X_DEV_BUS_VIRT_BASE + (x))
#define  GPIO_VIRT_BASE			ORION5X_DEV_BUS_REG(0x0100)
#define  SPI_PHYS_BASE			(ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
#define  I2C_PHYS_BASE			(ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
#define  UART0_PHYS_BASE		(ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
#define  UART0_VIRT_BASE		(ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
#define  UART1_PHYS_BASE		(ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
#define  UART1_VIRT_BASE		(ORION5X_DEV_BUS_VIRT_BASE + 0x2100)

#define ORION5X_BRIDGE_VIRT_BASE	(ORION5X_REGS_VIRT_BASE + 0x20000)
#define ORION5X_BRIDGE_PHYS_BASE	(ORION5X_REGS_PHYS_BASE + 0x20000)
#define  ORION5X_BRIDGE_WINS_BASE       (ORION5X_BRIDGE_PHYS_BASE)
#define  ORION5X_BRIDGE_WINS_SZ         (0x80)

#define ORION5X_PCI_VIRT_BASE		(ORION5X_REGS_VIRT_BASE + 0x30000)

#define ORION5X_PCIE_VIRT_BASE		(ORION5X_REGS_VIRT_BASE + 0x40000)

#define ORION5X_USB0_PHYS_BASE		(ORION5X_REGS_PHYS_BASE + 0x50000)
#define ORION5X_USB0_VIRT_BASE		(ORION5X_REGS_VIRT_BASE + 0x50000)

#define ORION5X_XOR_PHYS_BASE		(ORION5X_REGS_PHYS_BASE + 0x60900)
#define ORION5X_XOR_VIRT_BASE		(ORION5X_REGS_VIRT_BASE + 0x60900)

#define ORION5X_ETH_PHYS_BASE		(ORION5X_REGS_PHYS_BASE + 0x70000)
#define ORION5X_ETH_VIRT_BASE		(ORION5X_REGS_VIRT_BASE + 0x70000)

#define ORION5X_SATA_PHYS_BASE		(ORION5X_REGS_PHYS_BASE + 0x80000)
#define ORION5X_SATA_VIRT_BASE		(ORION5X_REGS_VIRT_BASE + 0x80000)

#define ORION5X_CRYPTO_PHYS_BASE	(ORION5X_REGS_PHYS_BASE + 0x90000)

#define ORION5X_USB1_PHYS_BASE		(ORION5X_REGS_PHYS_BASE + 0xa0000)
#define ORION5X_USB1_VIRT_BASE		(ORION5X_REGS_VIRT_BASE + 0xa0000)

/*******************************************************************************
 * Device Bus Registers
 ******************************************************************************/
#define MPP_0_7_CTRL		ORION5X_DEV_BUS_REG(0x000)
#define MPP_8_15_CTRL		ORION5X_DEV_BUS_REG(0x004)
#define MPP_16_19_CTRL		ORION5X_DEV_BUS_REG(0x050)
#define MPP_DEV_CTRL		ORION5X_DEV_BUS_REG(0x008)
#define MPP_RESET_SAMPLE	ORION5X_DEV_BUS_REG(0x010)
#define DEV_BANK_0_PARAM	ORION5X_DEV_BUS_REG(0x45c)
#define DEV_BANK_1_PARAM	ORION5X_DEV_BUS_REG(0x460)
#define DEV_BANK_2_PARAM	ORION5X_DEV_BUS_REG(0x464)
#define DEV_BANK_BOOT_PARAM	ORION5X_DEV_BUS_REG(0x46c)
#define DEV_BUS_CTRL		ORION5X_DEV_BUS_REG(0x4c0)
#define DEV_BUS_INT_CAUSE	ORION5X_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK	ORION5X_DEV_BUS_REG(0x4d4)

/*******************************************************************************
 * Supported Devices & Revisions
 ******************************************************************************/
/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
#define MV88F5181_DEV_ID	0x5181
#define MV88F5181_REV_B1	3
#define MV88F5181L_REV_A0	8
#define MV88F5181L_REV_A1	9
/* Orion-NAS (88F5182) */
#define MV88F5182_DEV_ID	0x5182
#define MV88F5182_REV_A2	2
/* Orion-2 (88F5281) */
#define MV88F5281_DEV_ID	0x5281
#define MV88F5281_REV_D0	4
#define MV88F5281_REV_D1	5
#define MV88F5281_REV_D2	6
/* Orion-1-90 (88F6183) */
#define MV88F6183_DEV_ID	0x6183
#define MV88F6183_REV_B0	3

#endif
Commit	Line	Data
9dd0b194	1	/*
a09e64fb	2	* arch/arm/mach-orion5x/include/mach/orion5x.h
9dd0b194 LB	3	*
9dd0b194 LB	4	* Generic definitions of Orion SoC flavors:
d323ade1	5	* Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
9dd0b194 LB	6	*
	7	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#ifndef __ASM_ARCH_ORION5X_H
	15	#define __ASM_ARCH_ORION5X_H
	16
5cdbe5d2 AB	17	#include <mach/irqs.h>
5cdbe5d2 AB	18
9dd0b194 LB	19	/*****************************************************************************
	20	* Orion Address Maps
	21	*
	22	* phys
	23	* e0000000 PCIe MEM space
	24	* e8000000 PCI MEM space
	25	* f0000000 PCIe WA space (Orion-1/Orion-NAS only)
	26	* f1000000 on-chip peripheral registers
	27	* f2000000 PCIe I/O space
	28	* f2100000 PCI I/O space
3a8f7441	29	* f2200000 SRAM dedicated for the crypto unit
9dd0b194 LB	30	* f4000000 device bus mappings (boot)
	31	* fa000000 device bus mappings (cs0)
	32	* fa800000 device bus mappings (cs2)
	33	* fc000000 device bus mappings (cs0/cs1)
	34	*
	35	* virt phys size
0a4b8c65 RH	36	* fe000000 f1000000 1M on-chip peripheral registers
	37	* fee00000 f2000000 64K PCIe I/O space
	38	* fee10000 f2100000 64K PCI I/O space
	39	* fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
9dd0b194 LB	40	****************************************************************************/
9dd0b194 LB	41	#define ORION5X_REGS_PHYS_BASE 0xf1000000
0d601f61	42	#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000)
9dd0b194 LB	43	#define ORION5X_REGS_SIZE SZ_1M
	44
	45	#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
9dd0b194	46	#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
0a4b8c65	47	#define ORION5X_PCIE_IO_SIZE SZ_64K
9dd0b194 LB	48
9dd0b194 LB	49	#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
0a4b8c65 RH	50	#define ORION5X_PCI_IO_BUS_BASE 0x00010000
0a4b8c65 RH	51	#define ORION5X_PCI_IO_SIZE SZ_64K
9dd0b194	52
3a8f7441 SAS	53	#define ORION5X_SRAM_PHYS_BASE (0xf2200000)
	54	#define ORION5X_SRAM_SIZE SZ_8K
	55
9dd0b194 LB	56	/* Relevant only for Orion-1/Orion-NAS */
9dd0b194 LB	57	#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
0d601f61	58	#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
9dd0b194 LB	59	#define ORION5X_PCIE_WA_SIZE SZ_16M
	60
	61	#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
	62	#define ORION5X_PCIE_MEM_SIZE SZ_128M
	63
	64	#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
	65	#define ORION5X_PCI_MEM_SIZE SZ_128M
	66
9dd0b194 LB	67	/*******************************************************************************
	68	* Orion Registers Map
	69	******************************************************************************/
fdd8b079	70
5d1190ea TP	71	#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000)
	72	#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500)
	73	#define ORION5X_DDR_WINS_SZ (0x10)
2332656a	74	#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000)
2332656a TP	75	#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000)
	76	#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000)
	77	#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x))
9eac6d0a	78	#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
2332656a TP	79	#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
	80	#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
	81	#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
	82	#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
	83	#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
	84	#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
9dd0b194	85
2332656a TP	86	#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000)
2332656a TP	87	#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000)
5d1190ea TP	88	#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE)
5d1190ea TP	89	#define ORION5X_BRIDGE_WINS_SZ (0x80)
9dd0b194	90
2332656a	91	#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000)
9dd0b194	92
2332656a	93	#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000)
9dd0b194	94
2332656a TP	95	#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000)
2332656a TP	96	#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000)
9dd0b194	97
2332656a TP	98	#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900)
2332656a TP	99	#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900)
1d5a1a6e	100
2332656a TP	101	#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000)
2332656a TP	102	#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000)
9dd0b194	103
2332656a TP	104	#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000)
2332656a TP	105	#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000)
9dd0b194	106
2332656a	107	#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000)
3a8f7441	108
2332656a TP	109	#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000)
2332656a TP	110	#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000)
9dd0b194 LB	111
	112	/*******************************************************************************
	113	* Device Bus Registers
	114	******************************************************************************/
	115	#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
	116	#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
	117	#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
	118	#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
	119	#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
9dd0b194 LB	120	#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
	121	#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
	122	#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
	123	#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
	124	#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
	125	#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
	126	#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
9dd0b194	127
fdd8b079 NP	128	/*******************************************************************************
	129	* Supported Devices & Revisions
	130	******************************************************************************/
	131	/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
	132	#define MV88F5181_DEV_ID 0x5181
	133	#define MV88F5181_REV_B1 3
	134	#define MV88F5181L_REV_A0 8
	135	#define MV88F5181L_REV_A1 9
	136	/* Orion-NAS (88F5182) */
	137	#define MV88F5182_DEV_ID 0x5182
	138	#define MV88F5182_REV_A2 2
	139	/* Orion-2 (88F5281) */
	140	#define MV88F5281_DEV_ID 0x5281
	141	#define MV88F5281_REV_D0 4
	142	#define MV88F5281_REV_D1 5
	143	#define MV88F5281_REV_D2 6
	144	/* Orion-1-90 (88F6183) */
	145	#define MV88F6183_DEV_ID 0x6183
	146	#define MV88F6183_REV_B0 3
9dd0b194 LB	147
9dd0b194 LB	148	#endif