[deliverable/linux.git] / arch / arm / mach-orion5x / pci.c

/*
 * arch/arm/mach-orion5x/pci.c
 *
 * PCI and PCIe functions for Marvell Orion System On Chip
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <plat/addr-map.h>
#include <mach/orion5x.h>
#include "common.h"

/*****************************************************************************
 * Orion has one PCIe controller and one PCI controller.
 *
 * Note1: The local PCIe bus number is '0'. The local PCI bus number
 * follows the scanned PCIe bridged busses, if any.
 *
 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
 * device bus, Orion registers, etc. However this code only enable the
 * access to DDR banks.
 ****************************************************************************/


/*****************************************************************************
 * PCIe controller
 ****************************************************************************/
#define PCIE_BASE	(ORION5X_PCIE_VIRT_BASE)

void __init orion5x_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_pcie_dev_id(PCIE_BASE);
	*rev = orion_pcie_rev(PCIE_BASE);
}

static int pcie_valid_config(int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == 0 && dev == 0)
		return 1;

	if (!orion_pcie_link_up(PCIE_BASE))
		return 0;

	if (bus == 0 && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion5x_pcie_lock);

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&orion5x_pcie_lock, flags);
	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);

	return ret;
}

static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
			   int where, int size, u32 *val)
{
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	/*
	 * We only support access to the non-extended configuration
	 * space when using the WA access method (or we would have to
	 * sacrifice 256M of CPU virtual address space.)
	 */
	if (where >= 0x100) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
				    bus, devfn, where, size, val);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&orion5x_pcie_lock, flags);
	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};


static int __init pcie_setup(struct pci_sys_data *sys)
{
	struct resource *res;
	int dev;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_setup(PCIE_BASE);

	/*
	 * Check whether to apply Orion-1/Orion-NAS PCIe config
	 * read transaction workaround.
	 */
	dev = orion_pcie_dev_id(PCIE_BASE);
	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
		printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
				   "read transaction workaround\n");
		orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
					  ORION5X_PCIE_WA_SIZE);
		pcie_ops.read = pcie_rd_conf_wa;
	}

	pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);

	/*
	 * Request resources.
	 */
	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
	if (!res)
		panic("pcie_setup unable to alloc resources");

	/*
	 * IORESOURCE_MEM
	 */
	res->name = "PCIe Memory Space";
	res->flags = IORESOURCE_MEM;
	res->start = ORION5X_PCIE_MEM_PHYS_BASE;
	res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, res))
		panic("Request PCIe Memory resource failed\n");
	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);

	return 1;
}

/*****************************************************************************
 * PCI controller
 ****************************************************************************/
#define ORION5X_PCI_REG(x)	(ORION5X_PCI_VIRT_BASE + (x))
#define PCI_MODE		ORION5X_PCI_REG(0xd00)
#define PCI_CMD			ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF		ORION5X_PCI_REG(0x1d14)
#define PCI_CONF_ADDR		ORION5X_PCI_REG(0xc78)
#define PCI_CONF_DATA		ORION5X_PCI_REG(0xc7c)

/*
 * PCI_MODE bits
 */
#define PCI_MODE_64BIT			(1 << 2)
#define PCI_MODE_PCIX			((1 << 4) | (1 << 5))

/*
 * PCI_CMD bits
 */
#define PCI_CMD_HOST_REORDER		(1 << 29)

/*
 * PCI_P2P_CONF bits
 */
#define PCI_P2P_BUS_OFFS		16
#define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS		24
#define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)

/*
 * PCI_CONF_ADDR bits
 */
#define PCI_CONF_REG(reg)		((reg) & 0xfc)
#define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN		(1 << 31)

/*
 * Internal configuration space
 */
#define PCI_CONF_FUNC_STAT_CMD		0
#define PCI_CONF_REG_STAT_CMD		4
#define PCIX_STAT			0x64
#define PCIX_STAT_BUS_OFFS		8
#define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)

/*
 * PCI Address Decode Windows registers
 */
#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
#define PCI_BAR_ENABLE		ORION5X_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL	ORION5X_PCI_REG(0xd3c)

/*
 * PCI configuration helpers for BAR settings
 */
#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)

/*
 * PCI config cycles are done by programming the PCI_CONF_ADDR register
 * and then reading the PCI_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion5x_pci_lock);

static int orion5x_pci_cardbus_mode;

static int orion5x_pci_local_bus_nr(void)
{
	u32 conf = readl(PCI_P2P_CONF);
	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}

static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 *val)
{
	unsigned long flags;
	spin_lock_irqsave(&orion5x_pci_lock, flags);

	writel(PCI_CONF_BUS(bus) |
		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);

	*val = readl(PCI_CONF_DATA);

	if (size == 1)
		*val = (*val >> (8*(where & 0x3))) & 0xff;
	else if (size == 2)
		*val = (*val >> (8*(where & 0x3))) & 0xffff;

	spin_unlock_irqrestore(&orion5x_pci_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 val)
{
	unsigned long flags;
	int ret = PCIBIOS_SUCCESSFUL;

	spin_lock_irqsave(&orion5x_pci_lock, flags);

	writel(PCI_CONF_BUS(bus) |
		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);

	if (size == 4) {
		__raw_writel(val, PCI_CONF_DATA);
	} else if (size == 2) {
		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	} else if (size == 1) {
		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	} else {
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

	spin_unlock_irqrestore(&orion5x_pci_lock, flags);

	return ret;
}

static int orion5x_pci_valid_config(int bus, u32 devfn)
{
	if (bus == orion5x_pci_local_bus_nr()) {
		/*
		 * Don't go out for local device
		 */
		if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
			return 0;

		/*
		 * When the PCI signals are directly connected to a
		 * Cardbus slot, ignore all but device IDs 0 and 1.
		 */
		if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
			return 0;
	}

	return 1;
}

static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 *val)
{
	if (!orion5x_pci_valid_config(bus->number, devfn)) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 val)
{
	if (!orion5x_pci_valid_config(bus->number, devfn))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static struct pci_ops pci_ops = {
	.read = orion5x_pci_rd_conf,
	.write = orion5x_pci_wr_conf,
};

static void __init orion5x_pci_set_bus_nr(int nr)
{
	u32 p2p = readl(PCI_P2P_CONF);

	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
		/*
		 * PCI-X mode
		 */
		u32 pcix_status, bus, dev;
		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
		orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
		pcix_status &= ~PCIX_STAT_BUS_MASK;
		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
		orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
	} else {
		/*
		 * PCI Conventional mode
		 */
		p2p &= ~PCI_P2P_BUS_MASK;
		p2p |= (nr << PCI_P2P_BUS_OFFS);
		writel(p2p, PCI_P2P_CONF);
	}
}

static void __init orion5x_pci_master_slave_enable(void)
{
	int bus_nr, func, reg;
	u32 val;

	bus_nr = orion5x_pci_local_bus_nr();
	func = PCI_CONF_FUNC_STAT_CMD;
	reg = PCI_CONF_REG_STAT_CMD;
	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
}

static void __init orion5x_setup_pci_wins(void)
{
	const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
	u32 win_enable;
	int bus;
	int i;

	/*
	 * First, disable windows.
	 */
	win_enable = 0xffffffff;
	writel(win_enable, PCI_BAR_ENABLE);

	/*
	 * Setup windows for DDR banks.
	 */
	bus = orion5x_pci_local_bus_nr();

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;
		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
		u32 reg;
		u32 val;

		/*
		 * Write DRAM bank base address register.
		 */
		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
		orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
		val = (cs->base & 0xfffff000) | (val & 0xfff);
		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);

		/*
		 * Write DRAM bank size register.
		 */
		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
		writel((cs->size - 1) & 0xfffff000,
			PCI_BAR_SIZE_DDR_CS(cs->cs_index));
		writel(cs->base & 0xfffff000,
			PCI_BAR_REMAP_DDR_CS(cs->cs_index));

		/*
		 * Enable decode window for this chip select.
		 */
		win_enable &= ~(1 << cs->cs_index);
	}

	/*
	 * Re-enable decode windows.
	 */
	writel(win_enable, PCI_BAR_ENABLE);

	/*
	 * Disable automatic update of address remapping when writing to BARs.
	 */
	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
}

static int __init pci_setup(struct pci_sys_data *sys)
{
	struct resource *res;

	/*
	 * Point PCI unit MBUS decode windows to DRAM space.
	 */
	orion5x_setup_pci_wins();

	/*
	 * Master + Slave enable
	 */
	orion5x_pci_master_slave_enable();

	/*
	 * Force ordering
	 */
	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);

	pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);

	/*
	 * Request resources
	 */
	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
	if (!res)
		panic("pci_setup unable to alloc resources");

	/*
	 * IORESOURCE_MEM
	 */
	res->name = "PCI Memory Space";
	res->flags = IORESOURCE_MEM;
	res->start = ORION5X_PCI_MEM_PHYS_BASE;
	res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, res))
		panic("Request PCI Memory resource failed\n");
	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);

	return 1;
}


/*****************************************************************************
 * General PCIe + PCI
 ****************************************************************************/
static void rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static int orion5x_pci_disabled __initdata;

void __init orion5x_pci_disable(void)
{
	orion5x_pci_disabled = 1;
}

void __init orion5x_pci_set_cardbus_mode(void)
{
	orion5x_pci_cardbus_mode = 1;
}

int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;

	vga_base = ORION5X_PCIE_MEM_PHYS_BASE;

	if (nr == 0) {
		orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
		ret = pcie_setup(sys);
	} else if (nr == 1 && !orion5x_pci_disabled) {
		orion5x_pci_set_bus_nr(sys->busnr);
		ret = pci_setup(sys);
	}

	return ret;
}

struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr == 0) {
		bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
					&sys->resources);
	} else if (nr == 1 && !orion5x_pci_disabled) {
		bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
					&sys->resources);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int bus = dev->bus->number;

	/*
	 * PCIe endpoint?
	 */
	if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
		return IRQ_ORION5X_PCIE0_INT;

	return -1;
}
Commit	Line	Data
038ee083	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/pci.c
038ee083	3	*
159ffb3a	4	* PCI and PCIe functions for Marvell Orion System On Chip
038ee083 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
038ee083 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
5a0e3ad6	15	#include <linux/slab.h>
1f2223b1	16	#include <linux/mbus.h>
158c0c62	17	#include <video/vga.h>
ff89c462	18	#include <asm/irq.h>
038ee083	19	#include <asm/mach/pci.h>
6f088f1d	20	#include <plat/pcie.h>
45173d5e	21	#include <plat/addr-map.h>
8a52dd4f	22	#include <mach/orion5x.h>
038ee083 TP	23	#include "common.h"
	24
	25	/*****************************************************************************
159ffb3a	26	* Orion has one PCIe controller and one PCI controller.
038ee083	27	*
159ffb3a LB	28	* Note1: The local PCIe bus number is '0'. The local PCI bus number
159ffb3a LB	29	* follows the scanned PCIe bridged busses, if any.
038ee083	30	*
159ffb3a	31	* Note2: It is possible for PCI/PCIe agents to access many subsystem's
038ee083 TP	32	* space, by configuring BARs and Address Decode Windows, e.g. flashes on
	33	* device bus, Orion registers, etc. However this code only enable the
	34	* access to DDR banks.
	35	****************************************************************************/
	36
	37
	38	/*****************************************************************************
159ffb3a	39	* PCIe controller
038ee083	40	****************************************************************************/
3904a393	41	#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
038ee083	42
9dd0b194	43	void __init orion5x_pcie_id(u32 dev, u32 rev)
038ee083	44	{
abc0197d LB	45	*dev = orion_pcie_dev_id(PCIE_BASE);
abc0197d LB	46	*rev = orion_pcie_rev(PCIE_BASE);
038ee083 TP	47	}
038ee083 TP	48
abc0197d	49	static int pcie_valid_config(int bus, int dev)
038ee083 TP	50	{
	51	/*
	52	* Don't go out when trying to access --
d50c60a8	53	* 1. nonexisting device on local bus
038ee083	54	* 2. where there's no device connected (no link)
038ee083	55	*/
d50c60a8 LB	56	if (bus == 0 && dev == 0)
d50c60a8 LB	57	return 1;
038ee083	58
abc0197d	59	if (!orion_pcie_link_up(PCIE_BASE))
038ee083 TP	60	return 0;
038ee083 TP	61
d50c60a8 LB	62	if (bus == 0 && dev != 1)
	63	return 0;
	64
038ee083 TP	65	return 1;
	66	}
	67
abc0197d LB	68
abc0197d LB	69	/*
159ffb3a	70	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
abc0197d LB	71	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	72	* transactions are atomic.
	73	*/
9dd0b194	74	static DEFINE_SPINLOCK(orion5x_pcie_lock);
abc0197d LB	75
	76	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	77	int size, u32 *val)
038ee083 TP	78	{
038ee083 TP	79	unsigned long flags;
abc0197d	80	int ret;
038ee083	81
abc0197d	82	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
038ee083 TP	83	*val = 0xffffffff;
	84	return PCIBIOS_DEVICE_NOT_FOUND;
	85	}
	86
9dd0b194	87	spin_lock_irqsave(&orion5x_pcie_lock, flags);
abc0197d	88	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
9dd0b194	89	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
038ee083	90
abc0197d LB	91	return ret;
abc0197d LB	92	}
038ee083	93
abc0197d LB	94	static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
	95	int where, int size, u32 *val)
	96	{
	97	int ret;
038ee083	98
abc0197d LB	99	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
	100	*val = 0xffffffff;
	101	return PCIBIOS_DEVICE_NOT_FOUND;
	102	}
038ee083	103
abc0197d LB	104	/*
	105	* We only support access to the non-extended configuration
	106	* space when using the WA access method (or we would have to
	107	* sacrifice 256M of CPU virtual address space.)
	108	*/
	109	if (where >= 0x100) {
	110	*val = 0xffffffff;
	111	return PCIBIOS_DEVICE_NOT_FOUND;
	112	}
038ee083	113
3904a393	114	ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
abc0197d	115	bus, devfn, where, size, val);
038ee083	116
abc0197d LB	117	return ret;
abc0197d LB	118	}
038ee083	119
abc0197d LB	120	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
abc0197d LB	121	int where, int size, u32 val)
038ee083 TP	122	{
	123	unsigned long flags;
	124	int ret;
	125
abc0197d	126	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
038ee083 TP	127	return PCIBIOS_DEVICE_NOT_FOUND;
038ee083 TP	128
9dd0b194	129	spin_lock_irqsave(&orion5x_pcie_lock, flags);
abc0197d	130	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
9dd0b194	131	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
038ee083 TP	132
	133	return ret;
	134	}
	135
159ffb3a	136	static struct pci_ops pcie_ops = {
abc0197d LB	137	.read = pcie_rd_conf,
abc0197d LB	138	.write = pcie_wr_conf,
038ee083 TP	139	};
	140
	141
a9984270	142	static int __init pcie_setup(struct pci_sys_data *sys)
038ee083 TP	143	{
038ee083 TP	144	struct resource *res;
abc0197d	145	int dev;
038ee083	146
1f2223b1	147	/*
abc0197d	148	* Generic PCIe unit setup.
038ee083	149	*/
63a9332b	150	orion_pcie_setup(PCIE_BASE);
038ee083 TP	151
038ee083 TP	152	/*
abc0197d LB	153	* Check whether to apply Orion-1/Orion-NAS PCIe config
abc0197d LB	154	* read transaction workaround.
038ee083	155	*/
abc0197d LB	156	dev = orion_pcie_dev_id(PCIE_BASE);
	157	if (dev == MV88F5181_DEV_ID \|\| dev == MV88F5182_DEV_ID) {
	158	printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
	159	"read transaction workaround\n");
386a048a LB	160	orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
386a048a LB	161	ORION5X_PCIE_WA_SIZE);
abc0197d LB	162	pcie_ops.read = pcie_rd_conf_wa;
abc0197d LB	163	}
038ee083	164
0a4b8c65 RH	165	pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
0a4b8c65 RH	166
038ee083	167	/*
abc0197d	168	* Request resources.
038ee083	169	*/
0a4b8c65	170	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
038ee083	171	if (!res)
abc0197d	172	panic("pcie_setup unable to alloc resources");
038ee083	173
038ee083 TP	174	/*
	175	* IORESOURCE_MEM
	176	*/
0a4b8c65 RH	177	res->name = "PCIe Memory Space";
	178	res->flags = IORESOURCE_MEM;
	179	res->start = ORION5X_PCIE_MEM_PHYS_BASE;
	180	res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
	181	if (request_resource(&iomem_resource, res))
159ffb3a	182	panic("Request PCIe Memory resource failed\n");
0a4b8c65	183	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
038ee083 TP	184
	185	return 1;
	186	}
	187
	188	/*****************************************************************************
	189	* PCI controller
	190	****************************************************************************/
2332656a	191	#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
9dd0b194 LB	192	#define PCI_MODE ORION5X_PCI_REG(0xd00)
	193	#define PCI_CMD ORION5X_PCI_REG(0xc00)
	194	#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
	195	#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
	196	#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
038ee083 TP	197
	198	/*
	199	* PCI_MODE bits
	200	*/
	201	#define PCI_MODE_64BIT (1 << 2)
	202	#define PCI_MODE_PCIX ((1 << 4) \| (1 << 5))
	203
	204	/*
	205	* PCI_CMD bits
	206	*/
	207	#define PCI_CMD_HOST_REORDER (1 << 29)
	208
	209	/*
	210	* PCI_P2P_CONF bits
	211	*/
	212	#define PCI_P2P_BUS_OFFS 16
	213	#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
	214	#define PCI_P2P_DEV_OFFS 24
	215	#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
	216
	217	/*
	218	* PCI_CONF_ADDR bits
	219	*/
	220	#define PCI_CONF_REG(reg) ((reg) & 0xfc)
	221	#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
	222	#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
	223	#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
	224	#define PCI_CONF_ADDR_EN (1 << 31)
	225
	226	/*
	227	* Internal configuration space
	228	*/
	229	#define PCI_CONF_FUNC_STAT_CMD 0
	230	#define PCI_CONF_REG_STAT_CMD 4
	231	#define PCIX_STAT 0x64
	232	#define PCIX_STAT_BUS_OFFS 8
	233	#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
	234
1f2223b1 LB	235	/*
	236	* PCI Address Decode Windows registers
	237	*/
9dd0b194	238	#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
e7068ad3 LB	239	((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
	240	((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
	241	((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
	242	#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
	243	((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
	244	((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
	245	((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
9dd0b194 LB	246	#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
9dd0b194 LB	247	#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
1f2223b1 LB	248
	249	/*
	250	* PCI configuration helpers for BAR settings
	251	*/
	252	#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
	253	#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
	254	#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
	255
038ee083 TP	256	/*
	257	* PCI config cycles are done by programming the PCI_CONF_ADDR register
	258	* and then reading the PCI_CONF_DATA register. Need to make sure these
	259	* transactions are atomic.
	260	*/
9dd0b194	261	static DEFINE_SPINLOCK(orion5x_pci_lock);
038ee083	262
da01bba3 LB	263	static int orion5x_pci_cardbus_mode;
da01bba3 LB	264
92b913b0	265	static int orion5x_pci_local_bus_nr(void)
038ee083	266	{
79e90dd5	267	u32 conf = readl(PCI_P2P_CONF);
038ee083 TP	268	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
	269	}
	270
9dd0b194	271	static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
038ee083 TP	272	u32 where, u32 size, u32 *val)
	273	{
	274	unsigned long flags;
9dd0b194	275	spin_lock_irqsave(&orion5x_pci_lock, flags);
038ee083	276
79e90dd5 LB	277	writel(PCI_CONF_BUS(bus) \|
	278	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	279	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
038ee083	280
79e90dd5	281	*val = readl(PCI_CONF_DATA);
038ee083 TP	282
	283	if (size == 1)
	284	val = (val >> (8*(where & 0x3))) & 0xff;
	285	else if (size == 2)
	286	val = (val >> (8*(where & 0x3))) & 0xffff;
	287
9dd0b194	288	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
038ee083 TP	289
	290	return PCIBIOS_SUCCESSFUL;
	291	}
	292
9dd0b194	293	static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
038ee083 TP	294	u32 where, u32 size, u32 val)
	295	{
	296	unsigned long flags;
	297	int ret = PCIBIOS_SUCCESSFUL;
	298
9dd0b194	299	spin_lock_irqsave(&orion5x_pci_lock, flags);
038ee083	300
79e90dd5 LB	301	writel(PCI_CONF_BUS(bus) \|
	302	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	303	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
038ee083 TP	304
	305	if (size == 4) {
	306	__raw_writel(val, PCI_CONF_DATA);
	307	} else if (size == 2) {
	308	__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	309	} else if (size == 1) {
	310	__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	311	} else {
	312	ret = PCIBIOS_BAD_REGISTER_NUMBER;
	313	}
	314
9dd0b194	315	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
038ee083 TP	316
	317	return ret;
	318	}
	319
da01bba3 LB	320	static int orion5x_pci_valid_config(int bus, u32 devfn)
	321	{
	322	if (bus == orion5x_pci_local_bus_nr()) {
	323	/*
	324	* Don't go out for local device
	325	*/
	326	if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
	327	return 0;
	328
	329	/*
	330	* When the PCI signals are directly connected to a
	331	* Cardbus slot, ignore all but device IDs 0 and 1.
	332	*/
	333	if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
	334	return 0;
	335	}
	336
	337	return 1;
	338	}
	339
9dd0b194	340	static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
038ee083 TP	341	int where, int size, u32 *val)
038ee083 TP	342	{
da01bba3	343	if (!orion5x_pci_valid_config(bus->number, devfn)) {
038ee083 TP	344	*val = 0xffffffff;
	345	return PCIBIOS_DEVICE_NOT_FOUND;
	346	}
	347
9dd0b194	348	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
038ee083 TP	349	PCI_FUNC(devfn), where, size, val);
	350	}
	351
9dd0b194	352	static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
038ee083 TP	353	int where, int size, u32 val)
038ee083 TP	354	{
da01bba3	355	if (!orion5x_pci_valid_config(bus->number, devfn))
038ee083 TP	356	return PCIBIOS_DEVICE_NOT_FOUND;
038ee083 TP	357
9dd0b194	358	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
038ee083 TP	359	PCI_FUNC(devfn), where, size, val);
	360	}
	361
159ffb3a	362	static struct pci_ops pci_ops = {
9dd0b194 LB	363	.read = orion5x_pci_rd_conf,
9dd0b194 LB	364	.write = orion5x_pci_wr_conf,
038ee083 TP	365	};
038ee083 TP	366
9dd0b194	367	static void __init orion5x_pci_set_bus_nr(int nr)
038ee083	368	{
79e90dd5	369	u32 p2p = readl(PCI_P2P_CONF);
038ee083	370
79e90dd5	371	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
038ee083 TP	372	/*
	373	* PCI-X mode
	374	*/
	375	u32 pcix_status, bus, dev;
	376	bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
	377	dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
9dd0b194	378	orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
038ee083 TP	379	pcix_status &= ~PCIX_STAT_BUS_MASK;
038ee083 TP	380	pcix_status \|= (nr << PCIX_STAT_BUS_OFFS);
9dd0b194	381	orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
038ee083 TP	382	} else {
	383	/*
	384	* PCI Conventional mode
	385	*/
	386	p2p &= ~PCI_P2P_BUS_MASK;
	387	p2p \|= (nr << PCI_P2P_BUS_OFFS);
79e90dd5	388	writel(p2p, PCI_P2P_CONF);
038ee083 TP	389	}
	390	}
	391
9dd0b194	392	static void __init orion5x_pci_master_slave_enable(void)
038ee083	393	{
d50c60a8	394	int bus_nr, func, reg;
abc0197d	395	u32 val;
038ee083	396
9dd0b194	397	bus_nr = orion5x_pci_local_bus_nr();
038ee083 TP	398	func = PCI_CONF_FUNC_STAT_CMD;
038ee083 TP	399	reg = PCI_CONF_REG_STAT_CMD;
9dd0b194	400	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
038ee083	401	val \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
9dd0b194	402	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val \| 0x7);
038ee083 TP	403	}
038ee083 TP	404
3e762c86	405	static void __init orion5x_setup_pci_wins(void)
1f2223b1	406	{
3e762c86	407	const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
1f2223b1	408	u32 win_enable;
abc0197d	409	int bus;
1f2223b1 LB	410	int i;
	411
	412	/*
	413	* First, disable windows.
	414	*/
	415	win_enable = 0xffffffff;
79e90dd5	416	writel(win_enable, PCI_BAR_ENABLE);
1f2223b1 LB	417
	418	/*
	419	* Setup windows for DDR banks.
	420	*/
9dd0b194	421	bus = orion5x_pci_local_bus_nr();
1f2223b1 LB	422
1f2223b1 LB	423	for (i = 0; i < dram->num_cs; i++) {
3e762c86	424	const struct mbus_dram_window *cs = dram->cs + i;
1f2223b1 LB	425	u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
	426	u32 reg;
	427	u32 val;
	428
	429	/*
	430	* Write DRAM bank base address register.
	431	*/
	432	reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
9dd0b194	433	orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
1f2223b1	434	val = (cs->base & 0xfffff000) \| (val & 0xfff);
9dd0b194	435	orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
1f2223b1 LB	436
	437	/*
	438	* Write DRAM bank size register.
	439	*/
	440	reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
9dd0b194	441	orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
79e90dd5 LB	442	writel((cs->size - 1) & 0xfffff000,
	443	PCI_BAR_SIZE_DDR_CS(cs->cs_index));
	444	writel(cs->base & 0xfffff000,
	445	PCI_BAR_REMAP_DDR_CS(cs->cs_index));
1f2223b1 LB	446
	447	/*
	448	* Enable decode window for this chip select.
	449	*/
	450	win_enable &= ~(1 << cs->cs_index);
	451	}
	452
	453	/*
	454	* Re-enable decode windows.
	455	*/
79e90dd5	456	writel(win_enable, PCI_BAR_ENABLE);
1f2223b1 LB	457
1f2223b1 LB	458	/*
af901ca1	459	* Disable automatic update of address remapping when writing to BARs.
1f2223b1	460	*/
9dd0b194	461	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
1f2223b1 LB	462	}
1f2223b1 LB	463
a9984270	464	static int __init pci_setup(struct pci_sys_data *sys)
038ee083 TP	465	{
	466	struct resource *res;
	467
1f2223b1 LB	468	/*
	469	* Point PCI unit MBUS decode windows to DRAM space.
	470	*/
3e762c86	471	orion5x_setup_pci_wins();
1f2223b1	472
038ee083 TP	473	/*
	474	* Master + Slave enable
	475	*/
9dd0b194	476	orion5x_pci_master_slave_enable();
038ee083 TP	477
	478	/*
	479	* Force ordering
	480	*/
9dd0b194	481	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
038ee083	482
0a4b8c65 RH	483	pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
0a4b8c65 RH	484
038ee083 TP	485	/*
	486	* Request resources
	487	*/
0a4b8c65	488	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
038ee083	489	if (!res)
abc0197d	490	panic("pci_setup unable to alloc resources");
038ee083	491
038ee083 TP	492	/*
	493	* IORESOURCE_MEM
	494	*/
0a4b8c65 RH	495	res->name = "PCI Memory Space";
	496	res->flags = IORESOURCE_MEM;
	497	res->start = ORION5X_PCI_MEM_PHYS_BASE;
	498	res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
	499	if (request_resource(&iomem_resource, res))
038ee083	500	panic("Request PCI Memory resource failed\n");
0a4b8c65	501	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
038ee083 TP	502
	503	return 1;
	504	}
	505
	506
	507	/*****************************************************************************
159ffb3a	508	* General PCIe + PCI
038ee083	509	****************************************************************************/
351a102d	510	static void rc_pci_fixup(struct pci_dev *dev)
d50c60a8 LB	511	{
	512	/*
	513	* Prevent enumeration of root complex.
	514	*/
	515	if (dev->bus->parent == NULL && dev->devfn == 0) {
	516	int i;
	517
	518	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	519	dev->resource[i].start = 0;
	520	dev->resource[i].end = 0;
	521	dev->resource[i].flags = 0;
	522	}
	523	}
	524	}
	525	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	526
7a6bb262 PA	527	static int orion5x_pci_disabled __initdata;
	528
	529	void __init orion5x_pci_disable(void)
	530	{
	531	orion5x_pci_disabled = 1;
	532	}
	533
da01bba3 LB	534	void __init orion5x_pci_set_cardbus_mode(void)
	535	{
	536	orion5x_pci_cardbus_mode = 1;
	537	}
	538
9dd0b194	539	int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
038ee083 TP	540	{
	541	int ret = 0;
	542
cc22b4c1 RH	543	vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
cc22b4c1 RH	544
038ee083	545	if (nr == 0) {
abc0197d LB	546	orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
abc0197d LB	547	ret = pcie_setup(sys);
7a6bb262	548	} else if (nr == 1 && !orion5x_pci_disabled) {
9dd0b194	549	orion5x_pci_set_bus_nr(sys->busnr);
abc0197d	550	ret = pci_setup(sys);
038ee083 TP	551	}
	552
	553	return ret;
	554	}
	555
9dd0b194	556	struct pci_bus __init orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data sys)
038ee083	557	{
038ee083 TP	558	struct pci_bus *bus;
038ee083 TP	559
038ee083	560	if (nr == 0) {
37d15909 BH	561	bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
37d15909 BH	562	&sys->resources);
7a6bb262	563	} else if (nr == 1 && !orion5x_pci_disabled) {
37d15909 BH	564	bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
37d15909 BH	565	&sys->resources);
038ee083	566	} else {
038ee083	567	bus = NULL;
abc0197d	568	BUG();
038ee083 TP	569	}
	570
	571	return bus;
	572	}
92b913b0	573
d5341942	574	int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
92b913b0 LB	575	{
	576	int bus = dev->bus->number;
	577
	578	/*
	579	* PCIe endpoint?
	580	*/
7a6bb262	581	if (orion5x_pci_disabled \|\| bus < orion5x_pci_local_bus_nr())
92b913b0 LB	582	return IRQ_ORION5X_PCIE0_INT;
	583
	584	return -1;
	585	}