[deliverable/linux.git] / arch / arm / mach-orion5x / pci.c

/*
 * arch/arm/mach-orion5x/pci.c
 *
 * PCI and PCIe functions for Marvell Orion System On Chip
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include "common.h"

/*****************************************************************************
 * Orion has one PCIe controller and one PCI controller.
 *
 * Note1: The local PCIe bus number is '0'. The local PCI bus number
 * follows the scanned PCIe bridged busses, if any.
 *
 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
 * device bus, Orion registers, etc. However this code only enable the
 * access to DDR banks.
 ****************************************************************************/


/*****************************************************************************
 * PCIe controller
 ****************************************************************************/
#define PCIE_BASE	((void __iomem *)ORION5X_PCIE_VIRT_BASE)

void __init orion5x_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_pcie_dev_id(PCIE_BASE);
	*rev = orion_pcie_rev(PCIE_BASE);
}

static int pcie_valid_config(int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == 0 && dev == 0)
		return 1;

	if (!orion_pcie_link_up(PCIE_BASE))
		return 0;

	if (bus == 0 && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion5x_pcie_lock);

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&orion5x_pcie_lock, flags);
	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);

	return ret;
}

static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
			   int where, int size, u32 *val)
{
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	/*
	 * We only support access to the non-extended configuration
	 * space when using the WA access method (or we would have to
	 * sacrifice 256M of CPU virtual address space.)
	 */
	if (where >= 0x100) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
				    bus, devfn, where, size, val);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&orion5x_pcie_lock, flags);
	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};


static int __init pcie_setup(struct pci_sys_data *sys)
{
	struct resource *res;
	int dev;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);

	/*
	 * Check whether to apply Orion-1/Orion-NAS PCIe config
	 * read transaction workaround.
	 */
	dev = orion_pcie_dev_id(PCIE_BASE);
	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
		printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
				   "read transaction workaround\n");
		orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
					  ORION5X_PCIE_WA_SIZE);
		pcie_ops.read = pcie_rd_conf_wa;
	}

	/*
	 * Request resources.
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pcie_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCIe I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION5X_PCIE_IO_BUS_BASE;
	res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCIe IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCIe Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCIe Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}

/*****************************************************************************
 * PCI controller
 ****************************************************************************/
#define ORION5X_PCI_REG(x)	(ORION5X_PCI_VIRT_BASE | (x))
#define PCI_MODE		ORION5X_PCI_REG(0xd00)
#define PCI_CMD			ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF		ORION5X_PCI_REG(0x1d14)
#define PCI_CONF_ADDR		ORION5X_PCI_REG(0xc78)
#define PCI_CONF_DATA		ORION5X_PCI_REG(0xc7c)

/*
 * PCI_MODE bits
 */
#define PCI_MODE_64BIT			(1 << 2)
#define PCI_MODE_PCIX			((1 << 4) | (1 << 5))

/*
 * PCI_CMD bits
 */
#define PCI_CMD_HOST_REORDER		(1 << 29)

/*
 * PCI_P2P_CONF bits
 */
#define PCI_P2P_BUS_OFFS		16
#define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS		24
#define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)

/*
 * PCI_CONF_ADDR bits
 */
#define PCI_CONF_REG(reg)		((reg) & 0xfc)
#define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN		(1 << 31)

/*
 * Internal configuration space
 */
#define PCI_CONF_FUNC_STAT_CMD		0
#define PCI_CONF_REG_STAT_CMD		4
#define PCIX_STAT			0x64
#define PCIX_STAT_BUS_OFFS		8
#define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)

/*
 * PCI Address Decode Windows registers
 */
#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
#define PCI_BAR_ENABLE		ORION5X_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL	ORION5X_PCI_REG(0xd3c)

/*
 * PCI configuration helpers for BAR settings
 */
#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)

/*
 * PCI config cycles are done by programming the PCI_CONF_ADDR register
 * and then reading the PCI_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion5x_pci_lock);

static int orion5x_pci_cardbus_mode;

static int orion5x_pci_local_bus_nr(void)
{
	u32 conf = readl(PCI_P2P_CONF);
	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}

static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 *val)
{
	unsigned long flags;
	spin_lock_irqsave(&orion5x_pci_lock, flags);

	writel(PCI_CONF_BUS(bus) |
		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);

	*val = readl(PCI_CONF_DATA);

	if (size == 1)
		*val = (*val >> (8*(where & 0x3))) & 0xff;
	else if (size == 2)
		*val = (*val >> (8*(where & 0x3))) & 0xffff;

	spin_unlock_irqrestore(&orion5x_pci_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 val)
{
	unsigned long flags;
	int ret = PCIBIOS_SUCCESSFUL;

	spin_lock_irqsave(&orion5x_pci_lock, flags);

	writel(PCI_CONF_BUS(bus) |
		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);

	if (size == 4) {
		__raw_writel(val, PCI_CONF_DATA);
	} else if (size == 2) {
		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	} else if (size == 1) {
		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	} else {
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

	spin_unlock_irqrestore(&orion5x_pci_lock, flags);

	return ret;
}

static int orion5x_pci_valid_config(int bus, u32 devfn)
{
	if (bus == orion5x_pci_local_bus_nr()) {
		/*
		 * Don't go out for local device
		 */
		if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
			return 0;

		/*
		 * When the PCI signals are directly connected to a
		 * Cardbus slot, ignore all but device IDs 0 and 1.
		 */
		if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
			return 0;
	}

	return 1;
}

static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 *val)
{
	if (!orion5x_pci_valid_config(bus->number, devfn)) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 val)
{
	if (!orion5x_pci_valid_config(bus->number, devfn))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static struct pci_ops pci_ops = {
	.read = orion5x_pci_rd_conf,
	.write = orion5x_pci_wr_conf,
};

static void __init orion5x_pci_set_bus_nr(int nr)
{
	u32 p2p = readl(PCI_P2P_CONF);

	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
		/*
		 * PCI-X mode
		 */
		u32 pcix_status, bus, dev;
		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
		orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
		pcix_status &= ~PCIX_STAT_BUS_MASK;
		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
		orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
	} else {
		/*
		 * PCI Conventional mode
		 */
		p2p &= ~PCI_P2P_BUS_MASK;
		p2p |= (nr << PCI_P2P_BUS_OFFS);
		writel(p2p, PCI_P2P_CONF);
	}
}

static void __init orion5x_pci_master_slave_enable(void)
{
	int bus_nr, func, reg;
	u32 val;

	bus_nr = orion5x_pci_local_bus_nr();
	func = PCI_CONF_FUNC_STAT_CMD;
	reg = PCI_CONF_REG_STAT_CMD;
	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
}

static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
{
	u32 win_enable;
	int bus;
	int i;

	/*
	 * First, disable windows.
	 */
	win_enable = 0xffffffff;
	writel(win_enable, PCI_BAR_ENABLE);

	/*
	 * Setup windows for DDR banks.
	 */
	bus = orion5x_pci_local_bus_nr();

	for (i = 0; i < dram->num_cs; i++) {
		struct mbus_dram_window *cs = dram->cs + i;
		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
		u32 reg;
		u32 val;

		/*
		 * Write DRAM bank base address register.
		 */
		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
		orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
		val = (cs->base & 0xfffff000) | (val & 0xfff);
		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);

		/*
		 * Write DRAM bank size register.
		 */
		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
		writel((cs->size - 1) & 0xfffff000,
			PCI_BAR_SIZE_DDR_CS(cs->cs_index));
		writel(cs->base & 0xfffff000,
			PCI_BAR_REMAP_DDR_CS(cs->cs_index));

		/*
		 * Enable decode window for this chip select.
		 */
		win_enable &= ~(1 << cs->cs_index);
	}

	/*
	 * Re-enable decode windows.
	 */
	writel(win_enable, PCI_BAR_ENABLE);

	/*
	 * Disable automatic update of address remapping when writing to BARs.
	 */
	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
}

static int __init pci_setup(struct pci_sys_data *sys)
{
	struct resource *res;

	/*
	 * Point PCI unit MBUS decode windows to DRAM space.
	 */
	orion5x_setup_pci_wins(&orion5x_mbus_dram_info);

	/*
	 * Master + Slave enable
	 */
	orion5x_pci_master_slave_enable();

	/*
	 * Force ordering
	 */
	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);

	/*
	 * Request resources
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pci_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCI I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION5X_PCI_IO_BUS_BASE;
	res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCI IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCI Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCI Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}


/*****************************************************************************
 * General PCIe + PCI
 ****************************************************************************/
static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static int orion5x_pci_disabled __initdata;

void __init orion5x_pci_disable(void)
{
	orion5x_pci_disabled = 1;
}

void __init orion5x_pci_set_cardbus_mode(void)
{
	orion5x_pci_cardbus_mode = 1;
}

int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;

	vga_base = ORION5X_PCIE_MEM_PHYS_BASE;

	if (nr == 0) {
		orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
		ret = pcie_setup(sys);
	} else if (nr == 1 && !orion5x_pci_disabled) {
		orion5x_pci_set_bus_nr(sys->busnr);
		ret = pci_setup(sys);
	}

	return ret;
}

struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr == 0) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else if (nr == 1 && !orion5x_pci_disabled) {
		bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int bus = dev->bus->number;

	/*
	 * PCIe endpoint?
	 */
	if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
		return IRQ_ORION5X_PCIE0_INT;

	return -1;
}
Commit	Line	Data
038ee083	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/pci.c
038ee083	3	*
159ffb3a	4	* PCI and PCIe functions for Marvell Orion System On Chip
038ee083 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
038ee083 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
5a0e3ad6	15	#include <linux/slab.h>
1f2223b1	16	#include <linux/mbus.h>
158c0c62	17	#include <video/vga.h>
ff89c462	18	#include <asm/irq.h>
038ee083	19	#include <asm/mach/pci.h>
6f088f1d	20	#include <plat/pcie.h>
038ee083 TP	21	#include "common.h"
	22
	23	/*****************************************************************************
159ffb3a	24	* Orion has one PCIe controller and one PCI controller.
038ee083	25	*
159ffb3a LB	26	* Note1: The local PCIe bus number is '0'. The local PCI bus number
159ffb3a LB	27	* follows the scanned PCIe bridged busses, if any.
038ee083	28	*
159ffb3a	29	* Note2: It is possible for PCI/PCIe agents to access many subsystem's
038ee083 TP	30	* space, by configuring BARs and Address Decode Windows, e.g. flashes on
	31	* device bus, Orion registers, etc. However this code only enable the
	32	* access to DDR banks.
	33	****************************************************************************/
	34
	35
	36	/*****************************************************************************
159ffb3a	37	* PCIe controller
038ee083	38	****************************************************************************/
9dd0b194	39	#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
038ee083	40
9dd0b194	41	void __init orion5x_pcie_id(u32 dev, u32 rev)
038ee083	42	{
abc0197d LB	43	*dev = orion_pcie_dev_id(PCIE_BASE);
abc0197d LB	44	*rev = orion_pcie_rev(PCIE_BASE);
038ee083 TP	45	}
038ee083 TP	46
abc0197d	47	static int pcie_valid_config(int bus, int dev)
038ee083 TP	48	{
	49	/*
	50	* Don't go out when trying to access --
d50c60a8	51	* 1. nonexisting device on local bus
038ee083	52	* 2. where there's no device connected (no link)
038ee083	53	*/
d50c60a8 LB	54	if (bus == 0 && dev == 0)
d50c60a8 LB	55	return 1;
038ee083	56
abc0197d	57	if (!orion_pcie_link_up(PCIE_BASE))
038ee083 TP	58	return 0;
038ee083 TP	59
d50c60a8 LB	60	if (bus == 0 && dev != 1)
	61	return 0;
	62
038ee083 TP	63	return 1;
	64	}
	65
abc0197d LB	66
abc0197d LB	67	/*
159ffb3a	68	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
abc0197d LB	69	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	70	* transactions are atomic.
	71	*/
9dd0b194	72	static DEFINE_SPINLOCK(orion5x_pcie_lock);
abc0197d LB	73
	74	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	75	int size, u32 *val)
038ee083 TP	76	{
038ee083 TP	77	unsigned long flags;
abc0197d	78	int ret;
038ee083	79
abc0197d	80	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
038ee083 TP	81	*val = 0xffffffff;
	82	return PCIBIOS_DEVICE_NOT_FOUND;
	83	}
	84
9dd0b194	85	spin_lock_irqsave(&orion5x_pcie_lock, flags);
abc0197d	86	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
9dd0b194	87	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
038ee083	88
abc0197d LB	89	return ret;
abc0197d LB	90	}
038ee083	91
abc0197d LB	92	static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
	93	int where, int size, u32 *val)
	94	{
	95	int ret;
038ee083	96
abc0197d LB	97	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
	98	*val = 0xffffffff;
	99	return PCIBIOS_DEVICE_NOT_FOUND;
	100	}
038ee083	101
abc0197d LB	102	/*
	103	* We only support access to the non-extended configuration
	104	* space when using the WA access method (or we would have to
	105	* sacrifice 256M of CPU virtual address space.)
	106	*/
	107	if (where >= 0x100) {
	108	*val = 0xffffffff;
	109	return PCIBIOS_DEVICE_NOT_FOUND;
	110	}
038ee083	111
9dd0b194	112	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
abc0197d	113	bus, devfn, where, size, val);
038ee083	114
abc0197d LB	115	return ret;
abc0197d LB	116	}
038ee083	117
abc0197d LB	118	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
abc0197d LB	119	int where, int size, u32 val)
038ee083 TP	120	{
	121	unsigned long flags;
	122	int ret;
	123
abc0197d	124	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
038ee083 TP	125	return PCIBIOS_DEVICE_NOT_FOUND;
038ee083 TP	126
9dd0b194	127	spin_lock_irqsave(&orion5x_pcie_lock, flags);
abc0197d	128	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
9dd0b194	129	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
038ee083 TP	130
	131	return ret;
	132	}
	133
159ffb3a	134	static struct pci_ops pcie_ops = {
abc0197d LB	135	.read = pcie_rd_conf,
abc0197d LB	136	.write = pcie_wr_conf,
038ee083 TP	137	};
	138
	139
a9984270	140	static int __init pcie_setup(struct pci_sys_data *sys)
038ee083 TP	141	{
038ee083 TP	142	struct resource *res;
abc0197d	143	int dev;
038ee083	144
1f2223b1	145	/*
abc0197d	146	* Generic PCIe unit setup.
038ee083	147	*/
9dd0b194	148	orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
038ee083 TP	149
038ee083 TP	150	/*
abc0197d LB	151	* Check whether to apply Orion-1/Orion-NAS PCIe config
abc0197d LB	152	* read transaction workaround.
038ee083	153	*/
abc0197d LB	154	dev = orion_pcie_dev_id(PCIE_BASE);
	155	if (dev == MV88F5181_DEV_ID \|\| dev == MV88F5182_DEV_ID) {
	156	printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
	157	"read transaction workaround\n");
386a048a LB	158	orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
386a048a LB	159	ORION5X_PCIE_WA_SIZE);
abc0197d LB	160	pcie_ops.read = pcie_rd_conf_wa;
abc0197d LB	161	}
038ee083 TP	162
038ee083 TP	163	/*
abc0197d	164	* Request resources.
038ee083 TP	165	*/
	166	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	167	if (!res)
abc0197d	168	panic("pcie_setup unable to alloc resources");
038ee083 TP	169
	170	/*
	171	* IORESOURCE_IO
	172	*/
159ffb3a	173	res[0].name = "PCIe I/O Space";
038ee083	174	res[0].flags = IORESOURCE_IO;
9dd0b194 LB	175	res[0].start = ORION5X_PCIE_IO_BUS_BASE;
9dd0b194 LB	176	res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
038ee083	177	if (request_resource(&ioport_resource, &res[0]))
159ffb3a	178	panic("Request PCIe IO resource failed\n");
038ee083 TP	179	sys->resource[0] = &res[0];
	180
	181	/*
	182	* IORESOURCE_MEM
	183	*/
159ffb3a	184	res[1].name = "PCIe Memory Space";
038ee083	185	res[1].flags = IORESOURCE_MEM;
9dd0b194 LB	186	res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
9dd0b194 LB	187	res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
038ee083	188	if (request_resource(&iomem_resource, &res[1]))
159ffb3a	189	panic("Request PCIe Memory resource failed\n");
038ee083 TP	190	sys->resource[1] = &res[1];
	191
	192	sys->resource[2] = NULL;
	193	sys->io_offset = 0;
	194
	195	return 1;
	196	}
	197
	198	/*****************************************************************************
	199	* PCI controller
	200	****************************************************************************/
fdd8b079	201	#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE \| (x))
9dd0b194 LB	202	#define PCI_MODE ORION5X_PCI_REG(0xd00)
	203	#define PCI_CMD ORION5X_PCI_REG(0xc00)
	204	#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
	205	#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
	206	#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
038ee083 TP	207
	208	/*
	209	* PCI_MODE bits
	210	*/
	211	#define PCI_MODE_64BIT (1 << 2)
	212	#define PCI_MODE_PCIX ((1 << 4) \| (1 << 5))
	213
	214	/*
	215	* PCI_CMD bits
	216	*/
	217	#define PCI_CMD_HOST_REORDER (1 << 29)
	218
	219	/*
	220	* PCI_P2P_CONF bits
	221	*/
	222	#define PCI_P2P_BUS_OFFS 16
	223	#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
	224	#define PCI_P2P_DEV_OFFS 24
	225	#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
	226
	227	/*
	228	* PCI_CONF_ADDR bits
	229	*/
	230	#define PCI_CONF_REG(reg) ((reg) & 0xfc)
	231	#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
	232	#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
	233	#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
	234	#define PCI_CONF_ADDR_EN (1 << 31)
	235
	236	/*
	237	* Internal configuration space
	238	*/
	239	#define PCI_CONF_FUNC_STAT_CMD 0
	240	#define PCI_CONF_REG_STAT_CMD 4
	241	#define PCIX_STAT 0x64
	242	#define PCIX_STAT_BUS_OFFS 8
	243	#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
	244
1f2223b1 LB	245	/*
	246	* PCI Address Decode Windows registers
	247	*/
9dd0b194	248	#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
e7068ad3 LB	249	((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
	250	((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
	251	((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
	252	#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
	253	((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
	254	((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
	255	((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
9dd0b194 LB	256	#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
9dd0b194 LB	257	#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
1f2223b1 LB	258
	259	/*
	260	* PCI configuration helpers for BAR settings
	261	*/
	262	#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
	263	#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
	264	#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
	265
038ee083 TP	266	/*
	267	* PCI config cycles are done by programming the PCI_CONF_ADDR register
	268	* and then reading the PCI_CONF_DATA register. Need to make sure these
	269	* transactions are atomic.
	270	*/
9dd0b194	271	static DEFINE_SPINLOCK(orion5x_pci_lock);
038ee083	272
da01bba3 LB	273	static int orion5x_pci_cardbus_mode;
da01bba3 LB	274
92b913b0	275	static int orion5x_pci_local_bus_nr(void)
038ee083	276	{
79e90dd5	277	u32 conf = readl(PCI_P2P_CONF);
038ee083 TP	278	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
	279	}
	280
9dd0b194	281	static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
038ee083 TP	282	u32 where, u32 size, u32 *val)
	283	{
	284	unsigned long flags;
9dd0b194	285	spin_lock_irqsave(&orion5x_pci_lock, flags);
038ee083	286
79e90dd5 LB	287	writel(PCI_CONF_BUS(bus) \|
	288	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	289	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
038ee083	290
79e90dd5	291	*val = readl(PCI_CONF_DATA);
038ee083 TP	292
	293	if (size == 1)
	294	val = (val >> (8*(where & 0x3))) & 0xff;
	295	else if (size == 2)
	296	val = (val >> (8*(where & 0x3))) & 0xffff;
	297
9dd0b194	298	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
038ee083 TP	299
	300	return PCIBIOS_SUCCESSFUL;
	301	}
	302
9dd0b194	303	static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
038ee083 TP	304	u32 where, u32 size, u32 val)
	305	{
	306	unsigned long flags;
	307	int ret = PCIBIOS_SUCCESSFUL;
	308
9dd0b194	309	spin_lock_irqsave(&orion5x_pci_lock, flags);
038ee083	310
79e90dd5 LB	311	writel(PCI_CONF_BUS(bus) \|
	312	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	313	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
038ee083 TP	314
	315	if (size == 4) {
	316	__raw_writel(val, PCI_CONF_DATA);
	317	} else if (size == 2) {
	318	__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	319	} else if (size == 1) {
	320	__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	321	} else {
	322	ret = PCIBIOS_BAD_REGISTER_NUMBER;
	323	}
	324
9dd0b194	325	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
038ee083 TP	326
	327	return ret;
	328	}
	329
da01bba3 LB	330	static int orion5x_pci_valid_config(int bus, u32 devfn)
	331	{
	332	if (bus == orion5x_pci_local_bus_nr()) {
	333	/*
	334	* Don't go out for local device
	335	*/
	336	if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
	337	return 0;
	338
	339	/*
	340	* When the PCI signals are directly connected to a
	341	* Cardbus slot, ignore all but device IDs 0 and 1.
	342	*/
	343	if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
	344	return 0;
	345	}
	346
	347	return 1;
	348	}
	349
9dd0b194	350	static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
038ee083 TP	351	int where, int size, u32 *val)
038ee083 TP	352	{
da01bba3	353	if (!orion5x_pci_valid_config(bus->number, devfn)) {
038ee083 TP	354	*val = 0xffffffff;
	355	return PCIBIOS_DEVICE_NOT_FOUND;
	356	}
	357
9dd0b194	358	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
038ee083 TP	359	PCI_FUNC(devfn), where, size, val);
	360	}
	361
9dd0b194	362	static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
038ee083 TP	363	int where, int size, u32 val)
038ee083 TP	364	{
da01bba3	365	if (!orion5x_pci_valid_config(bus->number, devfn))
038ee083 TP	366	return PCIBIOS_DEVICE_NOT_FOUND;
038ee083 TP	367
9dd0b194	368	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
038ee083 TP	369	PCI_FUNC(devfn), where, size, val);
	370	}
	371
159ffb3a	372	static struct pci_ops pci_ops = {
9dd0b194 LB	373	.read = orion5x_pci_rd_conf,
9dd0b194 LB	374	.write = orion5x_pci_wr_conf,
038ee083 TP	375	};
038ee083 TP	376
9dd0b194	377	static void __init orion5x_pci_set_bus_nr(int nr)
038ee083	378	{
79e90dd5	379	u32 p2p = readl(PCI_P2P_CONF);
038ee083	380
79e90dd5	381	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
038ee083 TP	382	/*
	383	* PCI-X mode
	384	*/
	385	u32 pcix_status, bus, dev;
	386	bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
	387	dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
9dd0b194	388	orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
038ee083 TP	389	pcix_status &= ~PCIX_STAT_BUS_MASK;
038ee083 TP	390	pcix_status \|= (nr << PCIX_STAT_BUS_OFFS);
9dd0b194	391	orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
038ee083 TP	392	} else {
	393	/*
	394	* PCI Conventional mode
	395	*/
	396	p2p &= ~PCI_P2P_BUS_MASK;
	397	p2p \|= (nr << PCI_P2P_BUS_OFFS);
79e90dd5	398	writel(p2p, PCI_P2P_CONF);
038ee083 TP	399	}
	400	}
	401
9dd0b194	402	static void __init orion5x_pci_master_slave_enable(void)
038ee083	403	{
d50c60a8	404	int bus_nr, func, reg;
abc0197d	405	u32 val;
038ee083	406
9dd0b194	407	bus_nr = orion5x_pci_local_bus_nr();
038ee083 TP	408	func = PCI_CONF_FUNC_STAT_CMD;
038ee083 TP	409	reg = PCI_CONF_REG_STAT_CMD;
9dd0b194	410	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
038ee083	411	val \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
9dd0b194	412	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val \| 0x7);
038ee083 TP	413	}
038ee083 TP	414
9dd0b194	415	static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
1f2223b1 LB	416	{
1f2223b1 LB	417	u32 win_enable;
abc0197d	418	int bus;
1f2223b1 LB	419	int i;
	420
	421	/*
	422	* First, disable windows.
	423	*/
	424	win_enable = 0xffffffff;
79e90dd5	425	writel(win_enable, PCI_BAR_ENABLE);
1f2223b1 LB	426
	427	/*
	428	* Setup windows for DDR banks.
	429	*/
9dd0b194	430	bus = orion5x_pci_local_bus_nr();
1f2223b1 LB	431
	432	for (i = 0; i < dram->num_cs; i++) {
	433	struct mbus_dram_window *cs = dram->cs + i;
	434	u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
	435	u32 reg;
	436	u32 val;
	437
	438	/*
	439	* Write DRAM bank base address register.
	440	*/
	441	reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
9dd0b194	442	orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
1f2223b1	443	val = (cs->base & 0xfffff000) \| (val & 0xfff);
9dd0b194	444	orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
1f2223b1 LB	445
	446	/*
	447	* Write DRAM bank size register.
	448	*/
	449	reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
9dd0b194	450	orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
79e90dd5 LB	451	writel((cs->size - 1) & 0xfffff000,
	452	PCI_BAR_SIZE_DDR_CS(cs->cs_index));
	453	writel(cs->base & 0xfffff000,
	454	PCI_BAR_REMAP_DDR_CS(cs->cs_index));
1f2223b1 LB	455
	456	/*
	457	* Enable decode window for this chip select.
	458	*/
	459	win_enable &= ~(1 << cs->cs_index);
	460	}
	461
	462	/*
	463	* Re-enable decode windows.
	464	*/
79e90dd5	465	writel(win_enable, PCI_BAR_ENABLE);
1f2223b1 LB	466
1f2223b1 LB	467	/*
af901ca1	468	* Disable automatic update of address remapping when writing to BARs.
1f2223b1	469	*/
9dd0b194	470	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
1f2223b1 LB	471	}
1f2223b1 LB	472
a9984270	473	static int __init pci_setup(struct pci_sys_data *sys)
038ee083 TP	474	{
	475	struct resource *res;
	476
1f2223b1 LB	477	/*
	478	* Point PCI unit MBUS decode windows to DRAM space.
	479	*/
9dd0b194	480	orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
1f2223b1	481
038ee083 TP	482	/*
	483	* Master + Slave enable
	484	*/
9dd0b194	485	orion5x_pci_master_slave_enable();
038ee083 TP	486
	487	/*
	488	* Force ordering
	489	*/
9dd0b194	490	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
038ee083 TP	491
	492	/*
	493	* Request resources
	494	*/
	495	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	496	if (!res)
abc0197d	497	panic("pci_setup unable to alloc resources");
038ee083 TP	498
	499	/*
	500	* IORESOURCE_IO
	501	*/
	502	res[0].name = "PCI I/O Space";
	503	res[0].flags = IORESOURCE_IO;
9dd0b194 LB	504	res[0].start = ORION5X_PCI_IO_BUS_BASE;
9dd0b194 LB	505	res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
038ee083 TP	506	if (request_resource(&ioport_resource, &res[0]))
	507	panic("Request PCI IO resource failed\n");
	508	sys->resource[0] = &res[0];
	509
	510	/*
	511	* IORESOURCE_MEM
	512	*/
	513	res[1].name = "PCI Memory Space";
	514	res[1].flags = IORESOURCE_MEM;
9dd0b194 LB	515	res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
9dd0b194 LB	516	res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
038ee083 TP	517	if (request_resource(&iomem_resource, &res[1]))
	518	panic("Request PCI Memory resource failed\n");
	519	sys->resource[1] = &res[1];
	520
	521	sys->resource[2] = NULL;
	522	sys->io_offset = 0;
	523
	524	return 1;
	525	}
	526
	527
	528	/*****************************************************************************
159ffb3a	529	* General PCIe + PCI
038ee083	530	****************************************************************************/
d50c60a8 LB	531	static void __devinit rc_pci_fixup(struct pci_dev *dev)
	532	{
	533	/*
	534	* Prevent enumeration of root complex.
	535	*/
	536	if (dev->bus->parent == NULL && dev->devfn == 0) {
	537	int i;
	538
	539	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	540	dev->resource[i].start = 0;
	541	dev->resource[i].end = 0;
	542	dev->resource[i].flags = 0;
	543	}
	544	}
	545	}
	546	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	547
7a6bb262 PA	548	static int orion5x_pci_disabled __initdata;
	549
	550	void __init orion5x_pci_disable(void)
	551	{
	552	orion5x_pci_disabled = 1;
	553	}
	554
da01bba3 LB	555	void __init orion5x_pci_set_cardbus_mode(void)
	556	{
	557	orion5x_pci_cardbus_mode = 1;
	558	}
	559
9dd0b194	560	int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
038ee083 TP	561	{
	562	int ret = 0;
	563
cc22b4c1 RH	564	vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
cc22b4c1 RH	565
038ee083	566	if (nr == 0) {
abc0197d LB	567	orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
abc0197d LB	568	ret = pcie_setup(sys);
7a6bb262	569	} else if (nr == 1 && !orion5x_pci_disabled) {
9dd0b194	570	orion5x_pci_set_bus_nr(sys->busnr);
abc0197d	571	ret = pci_setup(sys);
038ee083 TP	572	}
	573
	574	return ret;
	575	}
	576
9dd0b194	577	struct pci_bus __init orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data sys)
038ee083	578	{
038ee083 TP	579	struct pci_bus *bus;
038ee083 TP	580
038ee083	581	if (nr == 0) {
abc0197d	582	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
7a6bb262	583	} else if (nr == 1 && !orion5x_pci_disabled) {
abc0197d	584	bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
038ee083	585	} else {
038ee083	586	bus = NULL;
abc0197d	587	BUG();
038ee083 TP	588	}
	589
	590	return bus;
	591	}
92b913b0	592
d5341942	593	int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
92b913b0 LB	594	{
	595	int bus = dev->bus->number;
	596
	597	/*
	598	* PCIe endpoint?
	599	*/
7a6bb262	600	if (orion5x_pci_disabled \|\| bus < orion5x_pci_local_bus_nr())
92b913b0 LB	601	return IRQ_ORION5X_PCIE0_INT;
	602
	603	return -1;
	604	}