Commit | Line | Data |
---|---|---|
038ee083 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/pci.c |
038ee083 | 3 | * |
159ffb3a | 4 | * PCI and PCIe functions for Marvell Orion System On Chip |
038ee083 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
038ee083 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1f2223b1 | 16 | #include <linux/mbus.h> |
158c0c62 | 17 | #include <video/vga.h> |
ff89c462 | 18 | #include <asm/irq.h> |
038ee083 | 19 | #include <asm/mach/pci.h> |
6f088f1d | 20 | #include <plat/pcie.h> |
45173d5e | 21 | #include <plat/addr-map.h> |
038ee083 | 22 | #include "common.h" |
c22c2c60 | 23 | #include "orion5x.h" |
038ee083 TP |
24 | |
25 | /***************************************************************************** | |
159ffb3a | 26 | * Orion has one PCIe controller and one PCI controller. |
038ee083 | 27 | * |
159ffb3a LB |
28 | * Note1: The local PCIe bus number is '0'. The local PCI bus number |
29 | * follows the scanned PCIe bridged busses, if any. | |
038ee083 | 30 | * |
159ffb3a | 31 | * Note2: It is possible for PCI/PCIe agents to access many subsystem's |
038ee083 TP |
32 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on |
33 | * device bus, Orion registers, etc. However this code only enable the | |
34 | * access to DDR banks. | |
35 | ****************************************************************************/ | |
36 | ||
37 | ||
38 | /***************************************************************************** | |
159ffb3a | 39 | * PCIe controller |
038ee083 | 40 | ****************************************************************************/ |
3904a393 | 41 | #define PCIE_BASE (ORION5X_PCIE_VIRT_BASE) |
038ee083 | 42 | |
9dd0b194 | 43 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) |
038ee083 | 44 | { |
abc0197d LB |
45 | *dev = orion_pcie_dev_id(PCIE_BASE); |
46 | *rev = orion_pcie_rev(PCIE_BASE); | |
038ee083 TP |
47 | } |
48 | ||
abc0197d | 49 | static int pcie_valid_config(int bus, int dev) |
038ee083 TP |
50 | { |
51 | /* | |
52 | * Don't go out when trying to access -- | |
d50c60a8 | 53 | * 1. nonexisting device on local bus |
038ee083 | 54 | * 2. where there's no device connected (no link) |
038ee083 | 55 | */ |
d50c60a8 LB |
56 | if (bus == 0 && dev == 0) |
57 | return 1; | |
038ee083 | 58 | |
abc0197d | 59 | if (!orion_pcie_link_up(PCIE_BASE)) |
038ee083 TP |
60 | return 0; |
61 | ||
d50c60a8 LB |
62 | if (bus == 0 && dev != 1) |
63 | return 0; | |
64 | ||
038ee083 TP |
65 | return 1; |
66 | } | |
67 | ||
abc0197d LB |
68 | |
69 | /* | |
159ffb3a | 70 | * PCIe config cycles are done by programming the PCIE_CONF_ADDR register |
abc0197d LB |
71 | * and then reading the PCIE_CONF_DATA register. Need to make sure these |
72 | * transactions are atomic. | |
73 | */ | |
9dd0b194 | 74 | static DEFINE_SPINLOCK(orion5x_pcie_lock); |
abc0197d LB |
75 | |
76 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
77 | int size, u32 *val) | |
038ee083 TP |
78 | { |
79 | unsigned long flags; | |
abc0197d | 80 | int ret; |
038ee083 | 81 | |
abc0197d | 82 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
038ee083 TP |
83 | *val = 0xffffffff; |
84 | return PCIBIOS_DEVICE_NOT_FOUND; | |
85 | } | |
86 | ||
9dd0b194 | 87 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
abc0197d | 88 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); |
9dd0b194 | 89 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
038ee083 | 90 | |
abc0197d LB |
91 | return ret; |
92 | } | |
038ee083 | 93 | |
abc0197d LB |
94 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, |
95 | int where, int size, u32 *val) | |
96 | { | |
97 | int ret; | |
038ee083 | 98 | |
abc0197d LB |
99 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
100 | *val = 0xffffffff; | |
101 | return PCIBIOS_DEVICE_NOT_FOUND; | |
102 | } | |
038ee083 | 103 | |
abc0197d LB |
104 | /* |
105 | * We only support access to the non-extended configuration | |
106 | * space when using the WA access method (or we would have to | |
107 | * sacrifice 256M of CPU virtual address space.) | |
108 | */ | |
109 | if (where >= 0x100) { | |
110 | *val = 0xffffffff; | |
111 | return PCIBIOS_DEVICE_NOT_FOUND; | |
112 | } | |
038ee083 | 113 | |
3904a393 | 114 | ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, |
abc0197d | 115 | bus, devfn, where, size, val); |
038ee083 | 116 | |
abc0197d LB |
117 | return ret; |
118 | } | |
038ee083 | 119 | |
abc0197d LB |
120 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
121 | int where, int size, u32 val) | |
038ee083 TP |
122 | { |
123 | unsigned long flags; | |
124 | int ret; | |
125 | ||
abc0197d | 126 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) |
038ee083 TP |
127 | return PCIBIOS_DEVICE_NOT_FOUND; |
128 | ||
9dd0b194 | 129 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
abc0197d | 130 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); |
9dd0b194 | 131 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
038ee083 TP |
132 | |
133 | return ret; | |
134 | } | |
135 | ||
159ffb3a | 136 | static struct pci_ops pcie_ops = { |
abc0197d LB |
137 | .read = pcie_rd_conf, |
138 | .write = pcie_wr_conf, | |
038ee083 TP |
139 | }; |
140 | ||
141 | ||
a9984270 | 142 | static int __init pcie_setup(struct pci_sys_data *sys) |
038ee083 TP |
143 | { |
144 | struct resource *res; | |
abc0197d | 145 | int dev; |
038ee083 | 146 | |
1f2223b1 | 147 | /* |
abc0197d | 148 | * Generic PCIe unit setup. |
038ee083 | 149 | */ |
63a9332b | 150 | orion_pcie_setup(PCIE_BASE); |
038ee083 TP |
151 | |
152 | /* | |
abc0197d LB |
153 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
154 | * read transaction workaround. | |
038ee083 | 155 | */ |
abc0197d LB |
156 | dev = orion_pcie_dev_id(PCIE_BASE); |
157 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | |
158 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " | |
159 | "read transaction workaround\n"); | |
4ca2c040 TP |
160 | mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET, |
161 | ORION_MBUS_PCIE_WA_ATTR, | |
162 | ORION5X_PCIE_WA_PHYS_BASE, | |
163 | ORION5X_PCIE_WA_SIZE); | |
abc0197d LB |
164 | pcie_ops.read = pcie_rd_conf_wa; |
165 | } | |
038ee083 | 166 | |
0a4b8c65 RH |
167 | pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); |
168 | ||
038ee083 | 169 | /* |
abc0197d | 170 | * Request resources. |
038ee083 | 171 | */ |
0a4b8c65 | 172 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); |
038ee083 | 173 | if (!res) |
abc0197d | 174 | panic("pcie_setup unable to alloc resources"); |
038ee083 | 175 | |
038ee083 TP |
176 | /* |
177 | * IORESOURCE_MEM | |
178 | */ | |
0a4b8c65 RH |
179 | res->name = "PCIe Memory Space"; |
180 | res->flags = IORESOURCE_MEM; | |
181 | res->start = ORION5X_PCIE_MEM_PHYS_BASE; | |
182 | res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1; | |
183 | if (request_resource(&iomem_resource, res)) | |
159ffb3a | 184 | panic("Request PCIe Memory resource failed\n"); |
0a4b8c65 | 185 | pci_add_resource_offset(&sys->resources, res, sys->mem_offset); |
038ee083 TP |
186 | |
187 | return 1; | |
188 | } | |
189 | ||
190 | /***************************************************************************** | |
191 | * PCI controller | |
192 | ****************************************************************************/ | |
2332656a | 193 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x)) |
9dd0b194 LB |
194 | #define PCI_MODE ORION5X_PCI_REG(0xd00) |
195 | #define PCI_CMD ORION5X_PCI_REG(0xc00) | |
196 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) | |
197 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) | |
198 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) | |
038ee083 TP |
199 | |
200 | /* | |
201 | * PCI_MODE bits | |
202 | */ | |
203 | #define PCI_MODE_64BIT (1 << 2) | |
204 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) | |
205 | ||
206 | /* | |
207 | * PCI_CMD bits | |
208 | */ | |
209 | #define PCI_CMD_HOST_REORDER (1 << 29) | |
210 | ||
211 | /* | |
212 | * PCI_P2P_CONF bits | |
213 | */ | |
214 | #define PCI_P2P_BUS_OFFS 16 | |
215 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) | |
216 | #define PCI_P2P_DEV_OFFS 24 | |
217 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) | |
218 | ||
219 | /* | |
220 | * PCI_CONF_ADDR bits | |
221 | */ | |
222 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) | |
223 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) | |
224 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) | |
225 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) | |
226 | #define PCI_CONF_ADDR_EN (1 << 31) | |
227 | ||
228 | /* | |
229 | * Internal configuration space | |
230 | */ | |
231 | #define PCI_CONF_FUNC_STAT_CMD 0 | |
232 | #define PCI_CONF_REG_STAT_CMD 4 | |
233 | #define PCIX_STAT 0x64 | |
234 | #define PCIX_STAT_BUS_OFFS 8 | |
235 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) | |
236 | ||
1f2223b1 LB |
237 | /* |
238 | * PCI Address Decode Windows registers | |
239 | */ | |
9dd0b194 | 240 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ |
e7068ad3 LB |
241 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ |
242 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ | |
42366666 | 243 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL) |
e7068ad3 LB |
244 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ |
245 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ | |
246 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ | |
42366666 | 247 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL) |
9dd0b194 LB |
248 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) |
249 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) | |
1f2223b1 LB |
250 | |
251 | /* | |
252 | * PCI configuration helpers for BAR settings | |
253 | */ | |
254 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | |
255 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | |
256 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | |
257 | ||
038ee083 TP |
258 | /* |
259 | * PCI config cycles are done by programming the PCI_CONF_ADDR register | |
260 | * and then reading the PCI_CONF_DATA register. Need to make sure these | |
261 | * transactions are atomic. | |
262 | */ | |
9dd0b194 | 263 | static DEFINE_SPINLOCK(orion5x_pci_lock); |
038ee083 | 264 | |
da01bba3 LB |
265 | static int orion5x_pci_cardbus_mode; |
266 | ||
92b913b0 | 267 | static int orion5x_pci_local_bus_nr(void) |
038ee083 | 268 | { |
79e90dd5 | 269 | u32 conf = readl(PCI_P2P_CONF); |
038ee083 TP |
270 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); |
271 | } | |
272 | ||
9dd0b194 | 273 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, |
038ee083 TP |
274 | u32 where, u32 size, u32 *val) |
275 | { | |
276 | unsigned long flags; | |
9dd0b194 | 277 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
038ee083 | 278 | |
79e90dd5 LB |
279 | writel(PCI_CONF_BUS(bus) | |
280 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | |
281 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); | |
038ee083 | 282 | |
79e90dd5 | 283 | *val = readl(PCI_CONF_DATA); |
038ee083 TP |
284 | |
285 | if (size == 1) | |
286 | *val = (*val >> (8*(where & 0x3))) & 0xff; | |
287 | else if (size == 2) | |
288 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | |
289 | ||
9dd0b194 | 290 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
038ee083 TP |
291 | |
292 | return PCIBIOS_SUCCESSFUL; | |
293 | } | |
294 | ||
9dd0b194 | 295 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, |
038ee083 TP |
296 | u32 where, u32 size, u32 val) |
297 | { | |
298 | unsigned long flags; | |
299 | int ret = PCIBIOS_SUCCESSFUL; | |
300 | ||
9dd0b194 | 301 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
038ee083 | 302 | |
79e90dd5 LB |
303 | writel(PCI_CONF_BUS(bus) | |
304 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | |
305 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); | |
038ee083 TP |
306 | |
307 | if (size == 4) { | |
308 | __raw_writel(val, PCI_CONF_DATA); | |
309 | } else if (size == 2) { | |
310 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); | |
311 | } else if (size == 1) { | |
312 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); | |
313 | } else { | |
314 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | |
315 | } | |
316 | ||
9dd0b194 | 317 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
038ee083 TP |
318 | |
319 | return ret; | |
320 | } | |
321 | ||
da01bba3 LB |
322 | static int orion5x_pci_valid_config(int bus, u32 devfn) |
323 | { | |
324 | if (bus == orion5x_pci_local_bus_nr()) { | |
325 | /* | |
326 | * Don't go out for local device | |
327 | */ | |
328 | if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) | |
329 | return 0; | |
330 | ||
331 | /* | |
332 | * When the PCI signals are directly connected to a | |
333 | * Cardbus slot, ignore all but device IDs 0 and 1. | |
334 | */ | |
335 | if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) | |
336 | return 0; | |
337 | } | |
338 | ||
339 | return 1; | |
340 | } | |
341 | ||
9dd0b194 | 342 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, |
038ee083 TP |
343 | int where, int size, u32 *val) |
344 | { | |
da01bba3 | 345 | if (!orion5x_pci_valid_config(bus->number, devfn)) { |
038ee083 TP |
346 | *val = 0xffffffff; |
347 | return PCIBIOS_DEVICE_NOT_FOUND; | |
348 | } | |
349 | ||
9dd0b194 | 350 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), |
038ee083 TP |
351 | PCI_FUNC(devfn), where, size, val); |
352 | } | |
353 | ||
9dd0b194 | 354 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, |
038ee083 TP |
355 | int where, int size, u32 val) |
356 | { | |
da01bba3 | 357 | if (!orion5x_pci_valid_config(bus->number, devfn)) |
038ee083 TP |
358 | return PCIBIOS_DEVICE_NOT_FOUND; |
359 | ||
9dd0b194 | 360 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), |
038ee083 TP |
361 | PCI_FUNC(devfn), where, size, val); |
362 | } | |
363 | ||
159ffb3a | 364 | static struct pci_ops pci_ops = { |
9dd0b194 LB |
365 | .read = orion5x_pci_rd_conf, |
366 | .write = orion5x_pci_wr_conf, | |
038ee083 TP |
367 | }; |
368 | ||
9dd0b194 | 369 | static void __init orion5x_pci_set_bus_nr(int nr) |
038ee083 | 370 | { |
79e90dd5 | 371 | u32 p2p = readl(PCI_P2P_CONF); |
038ee083 | 372 | |
79e90dd5 | 373 | if (readl(PCI_MODE) & PCI_MODE_PCIX) { |
038ee083 TP |
374 | /* |
375 | * PCI-X mode | |
376 | */ | |
377 | u32 pcix_status, bus, dev; | |
378 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | |
379 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | |
9dd0b194 | 380 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); |
038ee083 TP |
381 | pcix_status &= ~PCIX_STAT_BUS_MASK; |
382 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | |
9dd0b194 | 383 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); |
038ee083 TP |
384 | } else { |
385 | /* | |
386 | * PCI Conventional mode | |
387 | */ | |
388 | p2p &= ~PCI_P2P_BUS_MASK; | |
389 | p2p |= (nr << PCI_P2P_BUS_OFFS); | |
79e90dd5 | 390 | writel(p2p, PCI_P2P_CONF); |
038ee083 TP |
391 | } |
392 | } | |
393 | ||
9dd0b194 | 394 | static void __init orion5x_pci_master_slave_enable(void) |
038ee083 | 395 | { |
d50c60a8 | 396 | int bus_nr, func, reg; |
abc0197d | 397 | u32 val; |
038ee083 | 398 | |
9dd0b194 | 399 | bus_nr = orion5x_pci_local_bus_nr(); |
038ee083 TP |
400 | func = PCI_CONF_FUNC_STAT_CMD; |
401 | reg = PCI_CONF_REG_STAT_CMD; | |
9dd0b194 | 402 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); |
038ee083 | 403 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
9dd0b194 | 404 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
038ee083 TP |
405 | } |
406 | ||
3e762c86 | 407 | static void __init orion5x_setup_pci_wins(void) |
1f2223b1 | 408 | { |
3e762c86 | 409 | const struct mbus_dram_target_info *dram = mv_mbus_dram_info(); |
1f2223b1 | 410 | u32 win_enable; |
abc0197d | 411 | int bus; |
1f2223b1 LB |
412 | int i; |
413 | ||
414 | /* | |
415 | * First, disable windows. | |
416 | */ | |
417 | win_enable = 0xffffffff; | |
79e90dd5 | 418 | writel(win_enable, PCI_BAR_ENABLE); |
1f2223b1 LB |
419 | |
420 | /* | |
421 | * Setup windows for DDR banks. | |
422 | */ | |
9dd0b194 | 423 | bus = orion5x_pci_local_bus_nr(); |
1f2223b1 LB |
424 | |
425 | for (i = 0; i < dram->num_cs; i++) { | |
3e762c86 | 426 | const struct mbus_dram_window *cs = dram->cs + i; |
1f2223b1 LB |
427 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); |
428 | u32 reg; | |
429 | u32 val; | |
430 | ||
431 | /* | |
432 | * Write DRAM bank base address register. | |
433 | */ | |
434 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); | |
9dd0b194 | 435 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); |
1f2223b1 | 436 | val = (cs->base & 0xfffff000) | (val & 0xfff); |
9dd0b194 | 437 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); |
1f2223b1 LB |
438 | |
439 | /* | |
440 | * Write DRAM bank size register. | |
441 | */ | |
442 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); | |
9dd0b194 | 443 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); |
79e90dd5 LB |
444 | writel((cs->size - 1) & 0xfffff000, |
445 | PCI_BAR_SIZE_DDR_CS(cs->cs_index)); | |
446 | writel(cs->base & 0xfffff000, | |
447 | PCI_BAR_REMAP_DDR_CS(cs->cs_index)); | |
1f2223b1 LB |
448 | |
449 | /* | |
450 | * Enable decode window for this chip select. | |
451 | */ | |
452 | win_enable &= ~(1 << cs->cs_index); | |
453 | } | |
454 | ||
455 | /* | |
456 | * Re-enable decode windows. | |
457 | */ | |
79e90dd5 | 458 | writel(win_enable, PCI_BAR_ENABLE); |
1f2223b1 LB |
459 | |
460 | /* | |
af901ca1 | 461 | * Disable automatic update of address remapping when writing to BARs. |
1f2223b1 | 462 | */ |
9dd0b194 | 463 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); |
1f2223b1 LB |
464 | } |
465 | ||
a9984270 | 466 | static int __init pci_setup(struct pci_sys_data *sys) |
038ee083 TP |
467 | { |
468 | struct resource *res; | |
469 | ||
1f2223b1 LB |
470 | /* |
471 | * Point PCI unit MBUS decode windows to DRAM space. | |
472 | */ | |
3e762c86 | 473 | orion5x_setup_pci_wins(); |
1f2223b1 | 474 | |
038ee083 TP |
475 | /* |
476 | * Master + Slave enable | |
477 | */ | |
9dd0b194 | 478 | orion5x_pci_master_slave_enable(); |
038ee083 TP |
479 | |
480 | /* | |
481 | * Force ordering | |
482 | */ | |
9dd0b194 | 483 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); |
038ee083 | 484 | |
0a4b8c65 RH |
485 | pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); |
486 | ||
038ee083 TP |
487 | /* |
488 | * Request resources | |
489 | */ | |
0a4b8c65 | 490 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); |
038ee083 | 491 | if (!res) |
abc0197d | 492 | panic("pci_setup unable to alloc resources"); |
038ee083 | 493 | |
038ee083 TP |
494 | /* |
495 | * IORESOURCE_MEM | |
496 | */ | |
0a4b8c65 RH |
497 | res->name = "PCI Memory Space"; |
498 | res->flags = IORESOURCE_MEM; | |
499 | res->start = ORION5X_PCI_MEM_PHYS_BASE; | |
500 | res->end = res->start + ORION5X_PCI_MEM_SIZE - 1; | |
501 | if (request_resource(&iomem_resource, res)) | |
038ee083 | 502 | panic("Request PCI Memory resource failed\n"); |
0a4b8c65 | 503 | pci_add_resource_offset(&sys->resources, res, sys->mem_offset); |
038ee083 TP |
504 | |
505 | return 1; | |
506 | } | |
507 | ||
508 | ||
509 | /***************************************************************************** | |
159ffb3a | 510 | * General PCIe + PCI |
038ee083 | 511 | ****************************************************************************/ |
351a102d | 512 | static void rc_pci_fixup(struct pci_dev *dev) |
d50c60a8 LB |
513 | { |
514 | /* | |
515 | * Prevent enumeration of root complex. | |
516 | */ | |
517 | if (dev->bus->parent == NULL && dev->devfn == 0) { | |
518 | int i; | |
519 | ||
520 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
521 | dev->resource[i].start = 0; | |
522 | dev->resource[i].end = 0; | |
523 | dev->resource[i].flags = 0; | |
524 | } | |
525 | } | |
526 | } | |
527 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); | |
528 | ||
7a6bb262 PA |
529 | static int orion5x_pci_disabled __initdata; |
530 | ||
531 | void __init orion5x_pci_disable(void) | |
532 | { | |
533 | orion5x_pci_disabled = 1; | |
534 | } | |
535 | ||
da01bba3 LB |
536 | void __init orion5x_pci_set_cardbus_mode(void) |
537 | { | |
538 | orion5x_pci_cardbus_mode = 1; | |
539 | } | |
540 | ||
9dd0b194 | 541 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) |
038ee083 | 542 | { |
cc22b4c1 RH |
543 | vga_base = ORION5X_PCIE_MEM_PHYS_BASE; |
544 | ||
038ee083 | 545 | if (nr == 0) { |
abc0197d | 546 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); |
9e808eb6 BH |
547 | return pcie_setup(sys); |
548 | } | |
549 | ||
550 | if (nr == 1 && !orion5x_pci_disabled) { | |
9dd0b194 | 551 | orion5x_pci_set_bus_nr(sys->busnr); |
9e808eb6 | 552 | return pci_setup(sys); |
038ee083 TP |
553 | } |
554 | ||
9e808eb6 | 555 | return 0; |
038ee083 TP |
556 | } |
557 | ||
9dd0b194 | 558 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) |
038ee083 | 559 | { |
9e808eb6 BH |
560 | if (nr == 0) |
561 | return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, | |
562 | &sys->resources); | |
038ee083 | 563 | |
9e808eb6 BH |
564 | if (nr == 1 && !orion5x_pci_disabled) |
565 | return pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, | |
566 | &sys->resources); | |
038ee083 | 567 | |
9e808eb6 BH |
568 | BUG(); |
569 | return NULL; | |
038ee083 | 570 | } |
92b913b0 | 571 | |
d5341942 | 572 | int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
92b913b0 LB |
573 | { |
574 | int bus = dev->bus->number; | |
575 | ||
576 | /* | |
577 | * PCIe endpoint? | |
578 | */ | |
7a6bb262 | 579 | if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) |
92b913b0 LB |
580 | return IRQ_ORION5X_PCIE0_INT; |
581 | ||
582 | return -1; | |
583 | } |