[deliverable/linux.git] / arch / arm / mach-orion5x / rd88f5182-setup.c

/*
 * arch/arm/mach-orion5x/rd88f5182-setup.c
 *
 * Marvell Orion-NAS Reference Design Setup
 *
 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/arch/orion5x.h>
#include "common.h"

/*****************************************************************************
 * RD-88F5182 Info
 ****************************************************************************/

/*
 * 512K NOR flash Device bus boot chip select
 */

#define RD88F5182_NOR_BOOT_BASE		0xf4000000
#define RD88F5182_NOR_BOOT_SIZE		SZ_512K

/*
 * 16M NOR flash on Device bus chip select 1
 */

#define RD88F5182_NOR_BASE		0xfc000000
#define RD88F5182_NOR_SIZE		SZ_16M

/*
 * PCI
 */

#define RD88F5182_PCI_SLOT0_OFFS	7
#define RD88F5182_PCI_SLOT0_IRQ_A_PIN	7
#define RD88F5182_PCI_SLOT0_IRQ_B_PIN	6

/*
 * GPIO Debug LED
 */

#define RD88F5182_GPIO_DBG_LED		0

/*****************************************************************************
 * 16M NOR Flash on Device bus CS1
 ****************************************************************************/

static struct physmap_flash_data rd88f5182_nor_flash_data = {
	.width		= 1,
};

static struct resource rd88f5182_nor_flash_resource = {
	.flags			= IORESOURCE_MEM,
	.start			= RD88F5182_NOR_BASE,
	.end			= RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
};

static struct platform_device rd88f5182_nor_flash = {
	.name			= "physmap-flash",
	.id			= 0,
	.dev		= {
		.platform_data	= &rd88f5182_nor_flash_data,
	},
	.num_resources		= 1,
	.resource		= &rd88f5182_nor_flash_resource,
};

#ifdef CONFIG_LEDS

/*****************************************************************************
 * Use GPIO debug led as CPU active indication
 ****************************************************************************/

static void rd88f5182_dbgled_event(led_event_t evt)
{
	int val;

	if (evt == led_idle_end)
		val = 1;
	else if (evt == led_idle_start)
		val = 0;
	else
		return;

	gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
}

static int __init rd88f5182_dbgled_init(void)
{
	int pin;

	if (machine_is_rd88f5182()) {
		pin = RD88F5182_GPIO_DBG_LED;

		if (gpio_request(pin, "DBGLED") == 0) {
			if (gpio_direction_output(pin, 0) != 0) {
				printk(KERN_ERR "rd88f5182_dbgled_init failed "
						"to set output pin %d\n", pin);
				gpio_free(pin);
				return 0;
			}
		} else {
			printk(KERN_ERR "rd88f5182_dbgled_init failed "
					"to request gpio %d\n", pin);
			return 0;
		}

		leds_event = rd88f5182_dbgled_event;
	}

	return 0;
}

__initcall(rd88f5182_dbgled_init);

#endif

/*****************************************************************************
 * PCI
 ****************************************************************************/

void __init rd88f5182_pci_preinit(void)
{
	int pin;

	/*
	 * Configure PCI GPIO IRQ pins
	 */
	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
	if (gpio_request(pin, "PCI IntA") == 0) {
		if (gpio_direction_input(pin) == 0) {
			set_irq_type(gpio_to_irq(pin), IRQT_LOW);
		} else {
			printk(KERN_ERR "rd88f5182_pci_preinit faield to "
					"set_irq_type pin %d\n", pin);
			gpio_free(pin);
		}
	} else {
		printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
	}

	pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
	if (gpio_request(pin, "PCI IntB") == 0) {
		if (gpio_direction_input(pin) == 0) {
			set_irq_type(gpio_to_irq(pin), IRQT_LOW);
		} else {
			printk(KERN_ERR "rd88f5182_pci_preinit faield to "
					"set_irq_type pin %d\n", pin);
			gpio_free(pin);
		}
	} else {
		printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
	}
}

static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	/*
	 * Check for devices with hard-wired IRQs.
	 */
	irq = orion5x_pci_map_irq(dev, slot, pin);
	if (irq != -1)
		return irq;

	/*
	 * PCI IRQs are connected via GPIOs
	 */
	switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
	case 0:
		if (pin == 1)
			return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
		else
			return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
	default:
		return -1;
	}
}

static struct hw_pci rd88f5182_pci __initdata = {
	.nr_controllers	= 2,
	.preinit	= rd88f5182_pci_preinit,
	.swizzle	= pci_std_swizzle,
	.setup		= orion5x_pci_sys_setup,
	.scan		= orion5x_pci_sys_scan_bus,
	.map_irq	= rd88f5182_pci_map_irq,
};

static int __init rd88f5182_pci_init(void)
{
	if (machine_is_rd88f5182())
		pci_common_init(&rd88f5182_pci);

	return 0;
}

subsys_initcall(rd88f5182_pci_init);

/*****************************************************************************
 * Ethernet
 ****************************************************************************/

static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
	.phy_addr	= 8,
	.force_phy_addr = 1,
};

/*****************************************************************************
 * RTC DS1338 on I2C bus
 ****************************************************************************/
static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
	I2C_BOARD_INFO("ds1338", 0x68),
};

/*****************************************************************************
 * Sata
 ****************************************************************************/
static struct mv_sata_platform_data rd88f5182_sata_data = {
	.n_ports	= 2,
};

/*****************************************************************************
 * General Setup
 ****************************************************************************/

static struct platform_device *rd88f5182_devices[] __initdata = {
	&rd88f5182_nor_flash,
};

static void __init rd88f5182_init(void)
{
	/*
	 * Setup basic Orion functions. Need to be called early.
	 */
	orion5x_init();

	/*
	 * Setup the CPU address decode windows for our devices
	 */
	orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
				RD88F5182_NOR_BOOT_SIZE);
	orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);

	/*
	 * Open a special address decode windows for the PCIe WA.
	 */
	orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
				ORION5X_PCIE_WA_SIZE);

	/*
	 * Setup Multiplexing Pins --
	 * MPP[0] Debug Led (GPIO - Out)
	 * MPP[1] Debug Led (GPIO - Out)
	 * MPP[2] N/A
	 * MPP[3] RTC_Int (GPIO - In)
	 * MPP[4] GPIO
	 * MPP[5] GPIO
	 * MPP[6] PCI_intA (GPIO - In)
	 * MPP[7] PCI_intB (GPIO - In)
	 * MPP[8-11] N/A
	 * MPP[12] SATA 0 presence Indication
	 * MPP[13] SATA 1 presence Indication
	 * MPP[14] SATA 0 active Indication
	 * MPP[15] SATA 1 active indication
	 * MPP[16-19] Not used
	 * MPP[20] PCI Clock to MV88F5182
	 * MPP[21] PCI Clock to mini PCI CON11
	 * MPP[22] USB 0 over current indication
	 * MPP[23] USB 1 over current indication
	 * MPP[24] USB 1 over current enable
	 * MPP[25] USB 0 over current enable
	 */

	orion5x_write(MPP_0_7_CTRL, 0x00000003);
	orion5x_write(MPP_8_15_CTRL, 0x55550000);
	orion5x_write(MPP_16_19_CTRL, 0x5555);

	orion5x_gpio_set_valid_pins(0x000000fb);

	platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
	i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
	orion5x_eth_init(&rd88f5182_eth_data);
	orion5x_sata_init(&rd88f5182_sata_data);
}

MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
	/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
	.phys_io	= ORION5X_REGS_PHYS_BASE,
	.io_pg_offst	= ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
	.boot_params	= 0x00000100,
	.init_machine	= rd88f5182_init,
	.map_io		= orion5x_map_io,
	.init_irq	= orion5x_init_irq,
	.timer		= &orion5x_timer,
MACHINE_END
Commit	Line	Data
817eb210	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/rd88f5182-setup.c
817eb210 RS	3	*
	4	* Marvell Orion-NAS Reference Design Setup
	5	*
	6	* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
817eb210 RS	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/pci.h>
	17	#include <linux/irq.h>
	18	#include <linux/mtd/physmap.h>
	19	#include <linux/mv643xx_eth.h>
f244baa3	20	#include <linux/ata_platform.h>
817eb210 RS	21	#include <linux/i2c.h>
	22	#include <asm/mach-types.h>
	23	#include <asm/gpio.h>
	24	#include <asm/leds.h>
	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/pci.h>
9dd0b194	27	#include <asm/arch/orion5x.h>
817eb210 RS	28	#include "common.h"
	29
	30	/*****************************************************************************
	31	* RD-88F5182 Info
	32	****************************************************************************/
	33
	34	/*
	35	* 512K NOR flash Device bus boot chip select
	36	*/
	37
	38	#define RD88F5182_NOR_BOOT_BASE 0xf4000000
	39	#define RD88F5182_NOR_BOOT_SIZE SZ_512K
	40
	41	/*
	42	* 16M NOR flash on Device bus chip select 1
	43	*/
	44
	45	#define RD88F5182_NOR_BASE 0xfc000000
	46	#define RD88F5182_NOR_SIZE SZ_16M
	47
	48	/*
	49	* PCI
	50	*/
	51
	52	#define RD88F5182_PCI_SLOT0_OFFS 7
	53	#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
	54	#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
	55
	56	/*
	57	* GPIO Debug LED
	58	*/
	59
	60	#define RD88F5182_GPIO_DBG_LED 0
	61
	62	/*****************************************************************************
	63	* 16M NOR Flash on Device bus CS1
	64	****************************************************************************/
	65
	66	static struct physmap_flash_data rd88f5182_nor_flash_data = {
	67	.width = 1,
	68	};
	69
	70	static struct resource rd88f5182_nor_flash_resource = {
	71	.flags = IORESOURCE_MEM,
	72	.start = RD88F5182_NOR_BASE,
	73	.end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
	74	};
	75
	76	static struct platform_device rd88f5182_nor_flash = {
	77	.name = "physmap-flash",
	78	.id = 0,
	79	.dev = {
	80	.platform_data = &rd88f5182_nor_flash_data,
	81	},
	82	.num_resources = 1,
	83	.resource = &rd88f5182_nor_flash_resource,
	84	};
	85
	86	#ifdef CONFIG_LEDS
	87
	88	/*****************************************************************************
	89	* Use GPIO debug led as CPU active indication
	90	****************************************************************************/
	91
92	static void rd88f5182_dbgled_event(led_event_t evt)
93	{
94	int val;
95
96	if (evt == led_idle_end)
97	val = 1;
98	else if (evt == led_idle_start)
99	val = 0;
100	else
101	return;
102
103	gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
104	}
105
106	static int __init rd88f5182_dbgled_init(void)
107	{
108	int pin;
109
110	if (machine_is_rd88f5182()) {
111	pin = RD88F5182_GPIO_DBG_LED;
112
113	if (gpio_request(pin, "DBGLED") == 0) {
114	if (gpio_direction_output(pin, 0) != 0) {
115	printk(KERN_ERR "rd88f5182_dbgled_init failed "
116	"to set output pin %d\n", pin);
117	gpio_free(pin);
118	return 0;
119	}
120	} else {
121	printk(KERN_ERR "rd88f5182_dbgled_init failed "
122	"to request gpio %d\n", pin);
123	return 0;
124	}
125
126	leds_event = rd88f5182_dbgled_event;
127	}
e7068ad3	128
817eb210 RS	129	return 0;
	130	}
	131
	132	__initcall(rd88f5182_dbgled_init);
	133
	134	#endif
	135
	136	/*****************************************************************************
	137	* PCI
	138	****************************************************************************/
	139
	140	void __init rd88f5182_pci_preinit(void)
	141	{
	142	int pin;
	143
	144	/*
	145	* Configure PCI GPIO IRQ pins
	146	*/
	147	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
	148	if (gpio_request(pin, "PCI IntA") == 0) {
	149	if (gpio_direction_input(pin) == 0) {
	150	set_irq_type(gpio_to_irq(pin), IRQT_LOW);
	151	} else {
	152	printk(KERN_ERR "rd88f5182_pci_preinit faield to "
	153	"set_irq_type pin %d\n", pin);
	154	gpio_free(pin);
	155	}
	156	} else {
	157	printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
	158	}
	159
	160	pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
	161	if (gpio_request(pin, "PCI IntB") == 0) {
	162	if (gpio_direction_input(pin) == 0) {
	163	set_irq_type(gpio_to_irq(pin), IRQT_LOW);
	164	} else {
	165	printk(KERN_ERR "rd88f5182_pci_preinit faield to "
	166	"set_irq_type pin %d\n", pin);
	167	gpio_free(pin);
	168	}
	169	} else {
	170	printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
	171	}
	172	}
	173
	174	static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	175	{
92b913b0 LB	176	int irq;
92b913b0 LB	177
817eb210	178	/*
92b913b0	179	* Check for devices with hard-wired IRQs.
817eb210	180	*/
92b913b0 LB	181	irq = orion5x_pci_map_irq(dev, slot, pin);
	182	if (irq != -1)
	183	return irq;
817eb210 RS	184
	185	/*
	186	* PCI IRQs are connected via GPIOs
	187	*/
	188	switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
	189	case 0:
	190	if (pin == 1)
	191	return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
	192	else
	193	return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
	194	default:
	195	return -1;
	196	}
	197	}
	198
	199	static struct hw_pci rd88f5182_pci __initdata = {
	200	.nr_controllers = 2,
	201	.preinit = rd88f5182_pci_preinit,
	202	.swizzle = pci_std_swizzle,
9dd0b194 LB	203	.setup = orion5x_pci_sys_setup,
9dd0b194 LB	204	.scan = orion5x_pci_sys_scan_bus,
817eb210 RS	205	.map_irq = rd88f5182_pci_map_irq,
	206	};
	207
	208	static int __init rd88f5182_pci_init(void)
	209	{
	210	if (machine_is_rd88f5182())
	211	pci_common_init(&rd88f5182_pci);
	212
	213	return 0;
	214	}
	215
	216	subsys_initcall(rd88f5182_pci_init);
	217
	218	/*****************************************************************************
	219	* Ethernet
	220	****************************************************************************/
	221
	222	static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
	223	.phy_addr = 8,
	224	.force_phy_addr = 1,
	225	};
	226
	227	/*****************************************************************************
	228	* RTC DS1338 on I2C bus
	229	****************************************************************************/
	230	static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
3760f736	231	I2C_BOARD_INFO("ds1338", 0x68),
817eb210 RS	232	};
817eb210 RS	233
f244baa3 SB	234	/*****************************************************************************
	235	* Sata
	236	****************************************************************************/
	237	static struct mv_sata_platform_data rd88f5182_sata_data = {
e7068ad3	238	.n_ports = 2,
f244baa3 SB	239	};
f244baa3 SB	240
817eb210 RS	241	/*****************************************************************************
	242	* General Setup
	243	****************************************************************************/
	244
	245	static struct platform_device *rd88f5182_devices[] __initdata = {
	246	&rd88f5182_nor_flash,
	247	};
	248
	249	static void __init rd88f5182_init(void)
	250	{
	251	/*
	252	* Setup basic Orion functions. Need to be called early.
	253	*/
9dd0b194	254	orion5x_init();
817eb210 RS	255
	256	/*
	257	* Setup the CPU address decode windows for our devices
	258	*/
9dd0b194	259	orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
98f79d1e	260	RD88F5182_NOR_BOOT_SIZE);
9dd0b194	261	orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
817eb210 RS	262
817eb210 RS	263	/*
b46926bb	264	* Open a special address decode windows for the PCIe WA.
817eb210	265	*/
9dd0b194 LB	266	orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
9dd0b194 LB	267	ORION5X_PCIE_WA_SIZE);
817eb210 RS	268
	269	/*
	270	* Setup Multiplexing Pins --
	271	* MPP[0] Debug Led (GPIO - Out)
	272	* MPP[1] Debug Led (GPIO - Out)
	273	* MPP[2] N/A
	274	* MPP[3] RTC_Int (GPIO - In)
	275	* MPP[4] GPIO
	276	* MPP[5] GPIO
	277	* MPP[6] PCI_intA (GPIO - In)
	278	* MPP[7] PCI_intB (GPIO - In)
	279	* MPP[8-11] N/A
	280	* MPP[12] SATA 0 presence Indication
	281	* MPP[13] SATA 1 presence Indication
	282	* MPP[14] SATA 0 active Indication
	283	* MPP[15] SATA 1 active indication
	284	* MPP[16-19] Not used
	285	* MPP[20] PCI Clock to MV88F5182
	286	* MPP[21] PCI Clock to mini PCI CON11
	287	* MPP[22] USB 0 over current indication
	288	* MPP[23] USB 1 over current indication
	289	* MPP[24] USB 1 over current enable
	290	* MPP[25] USB 0 over current enable
	291	*/
	292
9dd0b194 LB	293	orion5x_write(MPP_0_7_CTRL, 0x00000003);
	294	orion5x_write(MPP_8_15_CTRL, 0x55550000);
	295	orion5x_write(MPP_16_19_CTRL, 0x5555);
817eb210	296
9dd0b194	297	orion5x_gpio_set_valid_pins(0x000000fb);
817eb210 RS	298
	299	platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
	300	i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
9dd0b194 LB	301	orion5x_eth_init(&rd88f5182_eth_data);
9dd0b194 LB	302	orion5x_sata_init(&rd88f5182_sata_data);
817eb210 RS	303	}
	304
	305	MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
	306	/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
9dd0b194 LB	307	.phys_io = ORION5X_REGS_PHYS_BASE,
9dd0b194 LB	308	.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
817eb210 RS	309	.boot_params = 0x00000100,
817eb210 RS	310	.init_machine = rd88f5182_init,
9dd0b194 LB	311	.map_io = orion5x_map_io,
	312	.init_irq = orion5x_init_irq,
	313	.timer = &orion5x_timer,
817eb210	314	MACHINE_END