[deliverable/linux.git] / arch / arm / mach-orion5x / rd88f5182-setup.c

/*
 * arch/arm/mach-orion5x/rd88f5182-setup.c
 *
 * Marvell Orion-NAS Reference Design Setup
 *
 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <mach/orion5x.h>
#include "common.h"
#include "mpp.h"

/*****************************************************************************
 * RD-88F5182 Info
 ****************************************************************************/

/*
 * 512K NOR flash Device bus boot chip select
 */

#define RD88F5182_NOR_BOOT_BASE		0xf4000000
#define RD88F5182_NOR_BOOT_SIZE		SZ_512K

/*
 * 16M NOR flash on Device bus chip select 1
 */

#define RD88F5182_NOR_BASE		0xfc000000
#define RD88F5182_NOR_SIZE		SZ_16M

/*
 * PCI
 */

#define RD88F5182_PCI_SLOT0_OFFS	7
#define RD88F5182_PCI_SLOT0_IRQ_A_PIN	7
#define RD88F5182_PCI_SLOT0_IRQ_B_PIN	6

/*
 * GPIO Debug LED
 */

#define RD88F5182_GPIO_DBG_LED		0

/*****************************************************************************
 * 16M NOR Flash on Device bus CS1
 ****************************************************************************/

static struct physmap_flash_data rd88f5182_nor_flash_data = {
	.width		= 1,
};

static struct resource rd88f5182_nor_flash_resource = {
	.flags			= IORESOURCE_MEM,
	.start			= RD88F5182_NOR_BASE,
	.end			= RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
};

static struct platform_device rd88f5182_nor_flash = {
	.name			= "physmap-flash",
	.id			= 0,
	.dev		= {
		.platform_data	= &rd88f5182_nor_flash_data,
	},
	.num_resources		= 1,
	.resource		= &rd88f5182_nor_flash_resource,
};

#ifdef CONFIG_LEDS

/*****************************************************************************
 * Use GPIO debug led as CPU active indication
 ****************************************************************************/

static void rd88f5182_dbgled_event(led_event_t evt)
{
	int val;

	if (evt == led_idle_end)
		val = 1;
	else if (evt == led_idle_start)
		val = 0;
	else
		return;

	gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
}

static int __init rd88f5182_dbgled_init(void)
{
	int pin;

	if (machine_is_rd88f5182()) {
		pin = RD88F5182_GPIO_DBG_LED;

		if (gpio_request(pin, "DBGLED") == 0) {
			if (gpio_direction_output(pin, 0) != 0) {
				printk(KERN_ERR "rd88f5182_dbgled_init failed "
						"to set output pin %d\n", pin);
				gpio_free(pin);
				return 0;
			}
		} else {
			printk(KERN_ERR "rd88f5182_dbgled_init failed "
					"to request gpio %d\n", pin);
			return 0;
		}

		leds_event = rd88f5182_dbgled_event;
	}

	return 0;
}

__initcall(rd88f5182_dbgled_init);

#endif

/*****************************************************************************
 * PCI
 ****************************************************************************/

void __init rd88f5182_pci_preinit(void)
{
	int pin;

	/*
	 * Configure PCI GPIO IRQ pins
	 */
	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
	if (gpio_request(pin, "PCI IntA") == 0) {
		if (gpio_direction_input(pin) == 0) {
			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
		} else {
			printk(KERN_ERR "rd88f5182_pci_preinit faield to "
					"set_irq_type pin %d\n", pin);
			gpio_free(pin);
		}
	} else {
		printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
	}

	pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
	if (gpio_request(pin, "PCI IntB") == 0) {
		if (gpio_direction_input(pin) == 0) {
			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
		} else {
			printk(KERN_ERR "rd88f5182_pci_preinit faield to "
					"set_irq_type pin %d\n", pin);
			gpio_free(pin);
		}
	} else {
		printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
	}
}

static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
	u8 pin)
{
	int irq;

	/*
	 * Check for devices with hard-wired IRQs.
	 */
	irq = orion5x_pci_map_irq(dev, slot, pin);
	if (irq != -1)
		return irq;

	/*
	 * PCI IRQs are connected via GPIOs
	 */
	switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
	case 0:
		if (pin == 1)
			return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
		else
			return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
	default:
		return -1;
	}
}

static struct hw_pci rd88f5182_pci __initdata = {
	.nr_controllers	= 2,
	.preinit	= rd88f5182_pci_preinit,
	.swizzle	= pci_std_swizzle,
	.setup		= orion5x_pci_sys_setup,
	.scan		= orion5x_pci_sys_scan_bus,
	.map_irq	= rd88f5182_pci_map_irq,
};

static int __init rd88f5182_pci_init(void)
{
	if (machine_is_rd88f5182())
		pci_common_init(&rd88f5182_pci);

	return 0;
}

subsys_initcall(rd88f5182_pci_init);

/*****************************************************************************
 * Ethernet
 ****************************************************************************/

static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
};

/*****************************************************************************
 * RTC DS1338 on I2C bus
 ****************************************************************************/
static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
	I2C_BOARD_INFO("ds1338", 0x68),
};

/*****************************************************************************
 * Sata
 ****************************************************************************/
static struct mv_sata_platform_data rd88f5182_sata_data = {
	.n_ports	= 2,
};

/*****************************************************************************
 * General Setup
 ****************************************************************************/
static unsigned int rd88f5182_mpp_modes[] __initdata = {
	MPP0_GPIO,		/* Debug Led */
	MPP1_GPIO,		/* Reset Switch */
	MPP2_UNUSED,
	MPP3_GPIO,		/* RTC Int */
	MPP4_GPIO,
	MPP5_GPIO,
	MPP6_GPIO,		/* PCI_intA */
	MPP7_GPIO,		/* PCI_intB */
	MPP8_UNUSED,
	MPP9_UNUSED,
	MPP10_UNUSED,
	MPP11_UNUSED,
	MPP12_SATA_LED,		/* SATA 0 presence */
	MPP13_SATA_LED,		/* SATA 1 presence */
	MPP14_SATA_LED,		/* SATA 0 active */
	MPP15_SATA_LED,		/* SATA 1 active */
	MPP16_UNUSED,
	MPP17_UNUSED,
	MPP18_UNUSED,
	MPP19_UNUSED,
	0,
};

static void __init rd88f5182_init(void)
{
	/*
	 * Setup basic Orion functions. Need to be called early.
	 */
	orion5x_init();

	orion5x_mpp_conf(rd88f5182_mpp_modes);

	/*
	 * MPP[20] PCI Clock to MV88F5182
	 * MPP[21] PCI Clock to mini PCI CON11
	 * MPP[22] USB 0 over current indication
	 * MPP[23] USB 1 over current indication
	 * MPP[24] USB 1 over current enable
	 * MPP[25] USB 0 over current enable
	 */

	/*
	 * Configure peripherals.
	 */
	orion5x_ehci0_init();
	orion5x_ehci1_init();
	orion5x_eth_init(&rd88f5182_eth_data);
	orion5x_i2c_init();
	orion5x_sata_init(&rd88f5182_sata_data);
	orion5x_uart0_init();
	orion5x_xor_init();

	orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
				   RD88F5182_NOR_BOOT_SIZE);

	orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
	platform_device_register(&rd88f5182_nor_flash);

	i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
}

MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
	/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
	.boot_params	= 0x00000100,
	.init_machine	= rd88f5182_init,
	.map_io		= orion5x_map_io,
	.init_early	= orion5x_init_early,
	.init_irq	= orion5x_init_irq,
	.timer		= &orion5x_timer,
MACHINE_END
Commit	Line	Data
817eb210	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/rd88f5182-setup.c
817eb210 RS	3	*
	4	* Marvell Orion-NAS Reference Design Setup
	5	*
	6	* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
817eb210 RS	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/pci.h>
	17	#include <linux/irq.h>
	18	#include <linux/mtd/physmap.h>
	19	#include <linux/mv643xx_eth.h>
f244baa3	20	#include <linux/ata_platform.h>
817eb210 RS	21	#include <linux/i2c.h>
	22	#include <asm/mach-types.h>
	23	#include <asm/gpio.h>
	24	#include <asm/leds.h>
	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/pci.h>
a09e64fb	27	#include <mach/orion5x.h>
817eb210	28	#include "common.h"
19cfd5c0	29	#include "mpp.h"
817eb210 RS	30
	31	/*****************************************************************************
	32	* RD-88F5182 Info
	33	****************************************************************************/
	34
	35	/*
	36	* 512K NOR flash Device bus boot chip select
	37	*/
	38
	39	#define RD88F5182_NOR_BOOT_BASE 0xf4000000
	40	#define RD88F5182_NOR_BOOT_SIZE SZ_512K
	41
	42	/*
	43	* 16M NOR flash on Device bus chip select 1
	44	*/
	45
	46	#define RD88F5182_NOR_BASE 0xfc000000
	47	#define RD88F5182_NOR_SIZE SZ_16M
	48
	49	/*
	50	* PCI
	51	*/
	52
	53	#define RD88F5182_PCI_SLOT0_OFFS 7
	54	#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
	55	#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
	56
	57	/*
	58	* GPIO Debug LED
	59	*/
	60
	61	#define RD88F5182_GPIO_DBG_LED 0
	62
	63	/*****************************************************************************
	64	* 16M NOR Flash on Device bus CS1
	65	****************************************************************************/
	66
	67	static struct physmap_flash_data rd88f5182_nor_flash_data = {
	68	.width = 1,
	69	};
	70
	71	static struct resource rd88f5182_nor_flash_resource = {
	72	.flags = IORESOURCE_MEM,
	73	.start = RD88F5182_NOR_BASE,
	74	.end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
	75	};
	76
	77	static struct platform_device rd88f5182_nor_flash = {
	78	.name = "physmap-flash",
	79	.id = 0,
	80	.dev = {
	81	.platform_data = &rd88f5182_nor_flash_data,
	82	},
	83	.num_resources = 1,
	84	.resource = &rd88f5182_nor_flash_resource,
	85	};
	86
	87	#ifdef CONFIG_LEDS
	88
	89	/*****************************************************************************
	90	* Use GPIO debug led as CPU active indication
	91	****************************************************************************/
	92
	93	static void rd88f5182_dbgled_event(led_event_t evt)
94	{
95	int val;
96
97	if (evt == led_idle_end)
98	val = 1;
99	else if (evt == led_idle_start)
100	val = 0;
101	else
102	return;
103
104	gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
105	}
106
107	static int __init rd88f5182_dbgled_init(void)
108	{
109	int pin;
110
111	if (machine_is_rd88f5182()) {
112	pin = RD88F5182_GPIO_DBG_LED;
113
114	if (gpio_request(pin, "DBGLED") == 0) {
115	if (gpio_direction_output(pin, 0) != 0) {
116	printk(KERN_ERR "rd88f5182_dbgled_init failed "
117	"to set output pin %d\n", pin);
118	gpio_free(pin);
119	return 0;
120	}
121	} else {
122	printk(KERN_ERR "rd88f5182_dbgled_init failed "
123	"to request gpio %d\n", pin);
124	return 0;
125	}
126
127	leds_event = rd88f5182_dbgled_event;
128	}
e7068ad3	129
817eb210 RS	130	return 0;
	131	}
	132
	133	__initcall(rd88f5182_dbgled_init);
	134
	135	#endif
	136
	137	/*****************************************************************************
	138	* PCI
	139	****************************************************************************/
	140
	141	void __init rd88f5182_pci_preinit(void)
	142	{
	143	int pin;
	144
	145	/*
	146	* Configure PCI GPIO IRQ pins
	147	*/
	148	pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
	149	if (gpio_request(pin, "PCI IntA") == 0) {
	150	if (gpio_direction_input(pin) == 0) {
6845664a	151	irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
817eb210 RS	152	} else {
	153	printk(KERN_ERR "rd88f5182_pci_preinit faield to "
	154	"set_irq_type pin %d\n", pin);
	155	gpio_free(pin);
	156	}
	157	} else {
	158	printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
	159	}
	160
	161	pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
	162	if (gpio_request(pin, "PCI IntB") == 0) {
	163	if (gpio_direction_input(pin) == 0) {
6845664a	164	irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
817eb210 RS	165	} else {
	166	printk(KERN_ERR "rd88f5182_pci_preinit faield to "
	167	"set_irq_type pin %d\n", pin);
	168	gpio_free(pin);
	169	}
	170	} else {
	171	printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
	172	}
	173	}
	174
d5341942 RB	175	static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
d5341942 RB	176	u8 pin)
817eb210	177	{
92b913b0 LB	178	int irq;
92b913b0 LB	179
817eb210	180	/*
92b913b0	181	* Check for devices with hard-wired IRQs.
817eb210	182	*/
92b913b0 LB	183	irq = orion5x_pci_map_irq(dev, slot, pin);
	184	if (irq != -1)
	185	return irq;
817eb210 RS	186
	187	/*
	188	* PCI IRQs are connected via GPIOs
	189	*/
	190	switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
	191	case 0:
	192	if (pin == 1)
	193	return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
	194	else
	195	return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
	196	default:
	197	return -1;
	198	}
	199	}
	200
	201	static struct hw_pci rd88f5182_pci __initdata = {
	202	.nr_controllers = 2,
	203	.preinit = rd88f5182_pci_preinit,
	204	.swizzle = pci_std_swizzle,
9dd0b194 LB	205	.setup = orion5x_pci_sys_setup,
9dd0b194 LB	206	.scan = orion5x_pci_sys_scan_bus,
817eb210 RS	207	.map_irq = rd88f5182_pci_map_irq,
	208	};
	209
	210	static int __init rd88f5182_pci_init(void)
	211	{
	212	if (machine_is_rd88f5182())
	213	pci_common_init(&rd88f5182_pci);
	214
	215	return 0;
	216	}
	217
	218	subsys_initcall(rd88f5182_pci_init);
	219
	220	/*****************************************************************************
	221	* Ethernet
	222	****************************************************************************/
	223
	224	static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
ac840605	225	.phy_addr = MV643XX_ETH_PHY_ADDR(8),
817eb210 RS	226	};
	227
	228	/*****************************************************************************
	229	* RTC DS1338 on I2C bus
	230	****************************************************************************/
	231	static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
3760f736	232	I2C_BOARD_INFO("ds1338", 0x68),
817eb210 RS	233	};
817eb210 RS	234
f244baa3 SB	235	/*****************************************************************************
	236	* Sata
	237	****************************************************************************/
	238	static struct mv_sata_platform_data rd88f5182_sata_data = {
e7068ad3	239	.n_ports = 2,
f244baa3 SB	240	};
f244baa3 SB	241
817eb210 RS	242	/*****************************************************************************
	243	* General Setup
	244	****************************************************************************/
554cdaef AL	245	static unsigned int rd88f5182_mpp_modes[] __initdata = {
	246	MPP0_GPIO, /* Debug Led */
	247	MPP1_GPIO, /* Reset Switch */
	248	MPP2_UNUSED,
	249	MPP3_GPIO, /* RTC Int */
	250	MPP4_GPIO,
	251	MPP5_GPIO,
	252	MPP6_GPIO, /* PCI_intA */
	253	MPP7_GPIO, /* PCI_intB */
	254	MPP8_UNUSED,
	255	MPP9_UNUSED,
	256	MPP10_UNUSED,
	257	MPP11_UNUSED,
	258	MPP12_SATA_LED, /* SATA 0 presence */
	259	MPP13_SATA_LED, /* SATA 1 presence */
	260	MPP14_SATA_LED, /* SATA 0 active */
	261	MPP15_SATA_LED, /* SATA 1 active */
	262	MPP16_UNUSED,
	263	MPP17_UNUSED,
	264	MPP18_UNUSED,
	265	MPP19_UNUSED,
	266	0,
19cfd5c0 LB	267	};
19cfd5c0 LB	268
817eb210 RS	269	static void __init rd88f5182_init(void)
	270	{
	271	/*
	272	* Setup basic Orion functions. Need to be called early.
	273	*/
9dd0b194	274	orion5x_init();
817eb210	275
19cfd5c0 LB	276	orion5x_mpp_conf(rd88f5182_mpp_modes);
19cfd5c0 LB	277
817eb210	278	/*
817eb210 RS	279	* MPP[20] PCI Clock to MV88F5182
	280	* MPP[21] PCI Clock to mini PCI CON11
	281	* MPP[22] USB 0 over current indication
	282	* MPP[23] USB 1 over current indication
	283	* MPP[24] USB 1 over current enable
	284	* MPP[25] USB 0 over current enable
	285	*/
	286
044f6c7c LB	287	/*
	288	* Configure peripherals.
	289	*/
	290	orion5x_ehci0_init();
	291	orion5x_ehci1_init();
9dd0b194	292	orion5x_eth_init(&rd88f5182_eth_data);
044f6c7c	293	orion5x_i2c_init();
9dd0b194	294	orion5x_sata_init(&rd88f5182_sata_data);
044f6c7c	295	orion5x_uart0_init();
1d5a1a6e	296	orion5x_xor_init();
044f6c7c LB	297
	298	orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
	299	RD88F5182_NOR_BOOT_SIZE);
	300
	301	orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
	302	platform_device_register(&rd88f5182_nor_flash);
	303
	304	i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
817eb210 RS	305	}
	306
	307	MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
	308	/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
817eb210 RS	309	.boot_params = 0x00000100,
817eb210 RS	310	.init_machine = rd88f5182_init,
9dd0b194	311	.map_io = orion5x_map_io,
4ee1f6b5	312	.init_early = orion5x_init_early,
9dd0b194 LB	313	.init_irq = orion5x_init_irq,
9dd0b194 LB	314	.timer = &orion5x_timer,
817eb210	315	MACHINE_END