projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 21278aea | 1 | menuconfig ARCH_SIRF |
| e3246542 MY |
2 | bool "CSR SiRF" |
| 3 | depends on ARCH_MULTI_V7 | |
| e7eda91f | 4 | select ARCH_HAS_RESET_CONTROLLER |
| ef2b1d77 | 5 | select RESET_CONTROLLER |
| cf82e0e4 | 6 | select ARCH_REQUIRE_GPIOLIB |
| cf82e0e4 | 7 | select GENERIC_IRQ_CHIP |
| ce816fa8 | 8 | select NO_IOPORT_MAP |
| b1999477 | 9 | select REGMAP |
| cf82e0e4 AB |
10 | select PINCTRL |
| 11 | select PINCTRL_SIRF | |
| 12 | help | |
| 13 | Support for CSR SiRFprimaII/Marco/Polo platforms | |
| 14 | ||
| 156a0997 BS |
15 | if ARCH_SIRF |
| 16 | ||
| 4cba0585 | 17 | comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features" |
| d4fe49e5 BS |
18 | |
| 19 | config ARCH_ATLAS6 | |
| 20 | bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" | |
| 21 | default y | |
| d4fe49e5 BS |
22 | select SIRF_IRQ |
| 23 | help | |
| 24 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
| 156a0997 | 25 | |
| 4cba0585 ZS |
26 | config ARCH_ATLAS7 |
| 27 | bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform" | |
| 28 | default y | |
| 29 | select ARM_GIC | |
| 30 | select CPU_V7 | |
| b56d5d21 | 31 | select ATLAS7_TIMER |
| 4cba0585 ZS |
32 | select HAVE_ARM_SCU if SMP |
| 33 | select HAVE_SMP | |
| 4cba0585 ZS |
34 | help |
| 35 | Support for CSR SiRFSoC ARM Cortex A7 Platform | |
| 36 | ||
| 156a0997 BS |
37 | config ARCH_PRIMA2 |
| 38 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" | |
| 39 | default y | |
| c1e3c119 | 40 | select SIRF_IRQ |
| b1b3f49c | 41 | select ZONE_DMA |
| f3550d49 | 42 | select PRIMA2_TIMER |
| 156a0997 BS |
43 | help |
| 44 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
| 45 | ||
| c1e3c119 BS |
46 | config SIRF_IRQ |
| 47 | bool | |
| 48 | ||
| 156a0997 | 49 | endif |