[deliverable/linux.git] / arch / arm / mach-prima2 / rstc.c

/*
 * reset controller for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/reset-controller.h>

#include <asm/system_misc.h>

#define SIRFSOC_RSTBIT_NUM	64

static void __iomem *sirfsoc_rstc_base;
static DEFINE_MUTEX(rstc_lock);

static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
					unsigned long sw_reset_idx)
{
	u32 reset_bit = sw_reset_idx;

	if (reset_bit >= SIRFSOC_RSTBIT_NUM)
		return -EINVAL;

	mutex_lock(&rstc_lock);

	if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
		/*
		 * Writing 1 to this bit resets corresponding block. Writing 0 to this
		 * bit de-asserts reset signal of the corresponding block.
		 * datasheet doesn't require explicit delay between the set and clear
		 * of reset bit. it could be shorter if tests pass.
		 */
		writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit),
			sirfsoc_rstc_base + (reset_bit / 32) * 4);
		msleep(10);
		writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
			sirfsoc_rstc_base + (reset_bit / 32) * 4);
	} else {
		/*
		 * For MARCO and POLO
		 * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
		 * register de-asserts reset signal of the corresponding block.
		 * datasheet doesn't require explicit delay between the set and clear
		 * of reset bit. it could be shorter if tests pass.
		 */
		writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
		msleep(10);
		writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
	}

	mutex_unlock(&rstc_lock);

	return 0;
}

static struct reset_control_ops sirfsoc_rstc_ops = {
	.reset = sirfsoc_reset_module,
};

static struct reset_controller_dev sirfsoc_reset_controller = {
	.ops = &sirfsoc_rstc_ops,
	.nr_resets = SIRFSOC_RSTBIT_NUM,
};

#define SIRFSOC_SYS_RST_BIT  BIT(31)

static void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
{
	writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
}

static int sirfsoc_rstc_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	sirfsoc_rstc_base = of_iomap(np, 0);
	if (!sirfsoc_rstc_base) {
		dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
		return -ENOMEM;
	}

	sirfsoc_reset_controller.of_node = np;
	arm_pm_restart = sirfsoc_restart;

	if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
		reset_controller_register(&sirfsoc_reset_controller);

	return 0;
}

static const struct of_device_id rstc_ids[]  = {
	{ .compatible = "sirf,prima2-rstc" },
	{ .compatible = "sirf,marco-rstc" },
	{},
};

static struct platform_driver sirfsoc_rstc_driver = {
	.probe		= sirfsoc_rstc_probe,
	.driver		= {
		.name	= "sirfsoc_rstc",
		.owner	= THIS_MODULE,
		.of_match_table = rstc_ids,
	},
};

static int __init sirfsoc_rstc_init(void)
{
	return platform_driver_register(&sirfsoc_rstc_driver);
}
subsys_initcall(sirfsoc_rstc_init);
Commit	Line	Data
02c981c0 BD	1	/*
	2	* reset controller for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/mutex.h>
	11	#include <linux/io.h>
	12	#include <linux/delay.h>
	13	#include <linux/device.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
e7eda91f	16	#include <linux/platform_device.h>
7b6d864b	17	#include <linux/reboot.h>
e7eda91f BS	18	#include <linux/reset-controller.h>
e7eda91f BS	19
48352e52 AB	20	#include <asm/system_misc.h>
48352e52 AB	21
e7eda91f	22	#define SIRFSOC_RSTBIT_NUM 64
02c981c0	23
48352e52	24	static void __iomem *sirfsoc_rstc_base;
02c981c0 BD	25	static DEFINE_MUTEX(rstc_lock);
02c981c0 BD	26
e7eda91f BS	27	static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
e7eda91f BS	28	unsigned long sw_reset_idx)
02c981c0	29	{
e7eda91f	30	u32 reset_bit = sw_reset_idx;
02c981c0	31
e7eda91f	32	if (reset_bit >= SIRFSOC_RSTBIT_NUM)
0ecb40ca	33	return -EINVAL;
02c981c0 BD	34
	35	mutex_lock(&rstc_lock);
	36
e7eda91f	37	if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
0ecb40ca BS	38	/*
	39	* Writing 1 to this bit resets corresponding block. Writing 0 to this
	40	* bit de-asserts reset signal of the corresponding block.
	41	* datasheet doesn't require explicit delay between the set and clear
	42	* of reset bit. it could be shorter if tests pass.
	43	*/
e7eda91f	44	writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) \| (1 << reset_bit),
0ecb40ca BS	45	sirfsoc_rstc_base + (reset_bit / 32) * 4);
0ecb40ca BS	46	msleep(10);
e7eda91f	47	writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
0ecb40ca BS	48	sirfsoc_rstc_base + (reset_bit / 32) * 4);
	49	} else {
	50	/*
	51	* For MARCO and POLO
	52	* Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
	53	* register de-asserts reset signal of the corresponding block.
	54	* datasheet doesn't require explicit delay between the set and clear
	55	* of reset bit. it could be shorter if tests pass.
	56	*/
e7eda91f	57	writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
0ecb40ca	58	msleep(10);
e7eda91f	59	writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
0ecb40ca	60	}
02c981c0 BD	61
	62	mutex_unlock(&rstc_lock);
	63
	64	return 0;
	65	}
125c4033	66
e7eda91f BS	67	static struct reset_control_ops sirfsoc_rstc_ops = {
	68	.reset = sirfsoc_reset_module,
	69	};
	70
	71	static struct reset_controller_dev sirfsoc_reset_controller = {
	72	.ops = &sirfsoc_rstc_ops,
	73	.nr_resets = SIRFSOC_RSTBIT_NUM,
	74	};
	75
48352e52 AB	76	#define SIRFSOC_SYS_RST_BIT BIT(31)
	77
	78	static void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
	79	{
	80	writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
	81	}
	82
e7eda91f BS	83	static int sirfsoc_rstc_probe(struct platform_device *pdev)
	84	{
	85	struct device_node *np = pdev->dev.of_node;
	86	sirfsoc_rstc_base = of_iomap(np, 0);
	87	if (!sirfsoc_rstc_base) {
	88	dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
	89	return -ENOMEM;
	90	}
	91
	92	sirfsoc_reset_controller.of_node = np;
48352e52	93	arm_pm_restart = sirfsoc_restart;
e7eda91f	94
48352e52 AB	95	if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
48352e52 AB	96	reset_controller_register(&sirfsoc_reset_controller);
e7eda91f BS	97
	98	return 0;
	99	}
	100
	101	static const struct of_device_id rstc_ids[] = {
	102	{ .compatible = "sirf,prima2-rstc" },
	103	{ .compatible = "sirf,marco-rstc" },
	104	{},
	105	};
	106
	107	static struct platform_driver sirfsoc_rstc_driver = {
	108	.probe = sirfsoc_rstc_probe,
	109	.driver = {
	110	.name = "sirfsoc_rstc",
	111	.owner = THIS_MODULE,
	112	.of_match_table = rstc_ids,
	113	},
	114	};
	115
	116	static int __init sirfsoc_rstc_init(void)
	117	{
	118	return platform_driver_register(&sirfsoc_rstc_driver);
	119	}
	120	subsys_initcall(sirfsoc_rstc_init);