Commit | Line | Data |
---|---|---|
02c981c0 BD |
1 | /* |
2 | * reset controller for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/mutex.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
e7eda91f | 16 | #include <linux/platform_device.h> |
7b6d864b | 17 | #include <linux/reboot.h> |
e7eda91f BS |
18 | #include <linux/reset-controller.h> |
19 | ||
48352e52 AB |
20 | #include <asm/system_misc.h> |
21 | ||
e7eda91f | 22 | #define SIRFSOC_RSTBIT_NUM 64 |
02c981c0 | 23 | |
48352e52 | 24 | static void __iomem *sirfsoc_rstc_base; |
02c981c0 BD |
25 | static DEFINE_MUTEX(rstc_lock); |
26 | ||
e7eda91f BS |
27 | static int sirfsoc_reset_module(struct reset_controller_dev *rcdev, |
28 | unsigned long sw_reset_idx) | |
02c981c0 | 29 | { |
e7eda91f | 30 | u32 reset_bit = sw_reset_idx; |
02c981c0 | 31 | |
e7eda91f | 32 | if (reset_bit >= SIRFSOC_RSTBIT_NUM) |
0ecb40ca | 33 | return -EINVAL; |
02c981c0 BD |
34 | |
35 | mutex_lock(&rstc_lock); | |
36 | ||
e664c3ff BS |
37 | /* |
38 | * Writing 1 to this bit resets corresponding block. | |
39 | * Writing 0 to this bit de-asserts reset signal of the | |
40 | * corresponding block. datasheet doesn't require explicit | |
41 | * delay between the set and clear of reset bit. it could | |
42 | * be shorter if tests pass. | |
43 | */ | |
44 | writel(readl(sirfsoc_rstc_base + | |
a2a25683 | 45 | (reset_bit / 32) * 4) | (1 << reset_bit), |
e664c3ff BS |
46 | sirfsoc_rstc_base + (reset_bit / 32) * 4); |
47 | msleep(20); | |
48 | writel(readl(sirfsoc_rstc_base + | |
a2a25683 | 49 | (reset_bit / 32) * 4) & ~(1 << reset_bit), |
e664c3ff | 50 | sirfsoc_rstc_base + (reset_bit / 32) * 4); |
02c981c0 BD |
51 | |
52 | mutex_unlock(&rstc_lock); | |
53 | ||
54 | return 0; | |
55 | } | |
125c4033 | 56 | |
e7eda91f BS |
57 | static struct reset_control_ops sirfsoc_rstc_ops = { |
58 | .reset = sirfsoc_reset_module, | |
59 | }; | |
60 | ||
61 | static struct reset_controller_dev sirfsoc_reset_controller = { | |
62 | .ops = &sirfsoc_rstc_ops, | |
63 | .nr_resets = SIRFSOC_RSTBIT_NUM, | |
64 | }; | |
65 | ||
48352e52 AB |
66 | #define SIRFSOC_SYS_RST_BIT BIT(31) |
67 | ||
68 | static void sirfsoc_restart(enum reboot_mode mode, const char *cmd) | |
69 | { | |
70 | writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base); | |
71 | } | |
72 | ||
e7eda91f BS |
73 | static int sirfsoc_rstc_probe(struct platform_device *pdev) |
74 | { | |
75 | struct device_node *np = pdev->dev.of_node; | |
76 | sirfsoc_rstc_base = of_iomap(np, 0); | |
77 | if (!sirfsoc_rstc_base) { | |
78 | dev_err(&pdev->dev, "unable to map rstc cpu registers\n"); | |
79 | return -ENOMEM; | |
80 | } | |
81 | ||
82 | sirfsoc_reset_controller.of_node = np; | |
48352e52 | 83 | arm_pm_restart = sirfsoc_restart; |
e7eda91f | 84 | |
48352e52 AB |
85 | if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) |
86 | reset_controller_register(&sirfsoc_reset_controller); | |
e7eda91f BS |
87 | |
88 | return 0; | |
89 | } | |
90 | ||
91 | static const struct of_device_id rstc_ids[] = { | |
92 | { .compatible = "sirf,prima2-rstc" }, | |
e7eda91f BS |
93 | {}, |
94 | }; | |
95 | ||
96 | static struct platform_driver sirfsoc_rstc_driver = { | |
97 | .probe = sirfsoc_rstc_probe, | |
98 | .driver = { | |
99 | .name = "sirfsoc_rstc", | |
e7eda91f BS |
100 | .of_match_table = rstc_ids, |
101 | }, | |
102 | }; | |
103 | ||
104 | static int __init sirfsoc_rstc_init(void) | |
105 | { | |
106 | return platform_driver_register(&sirfsoc_rstc_driver); | |
107 | } | |
108 | subsys_initcall(sirfsoc_rstc_init); |