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02c981c0 BD |
1 | /* |
2 | * System timer for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/clockchips.h> | |
12 | #include <linux/clocksource.h> | |
13 | #include <linux/bitops.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <mach/map.h> | |
21 | #include <asm/mach/time.h> | |
22 | ||
23 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 | |
24 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 | |
25 | #define SIRFSOC_TIMER_MATCH_0 0x0008 | |
26 | #define SIRFSOC_TIMER_MATCH_1 0x000C | |
27 | #define SIRFSOC_TIMER_MATCH_2 0x0010 | |
28 | #define SIRFSOC_TIMER_MATCH_3 0x0014 | |
29 | #define SIRFSOC_TIMER_MATCH_4 0x0018 | |
30 | #define SIRFSOC_TIMER_MATCH_5 0x001C | |
31 | #define SIRFSOC_TIMER_STATUS 0x0020 | |
32 | #define SIRFSOC_TIMER_INT_EN 0x0024 | |
33 | #define SIRFSOC_TIMER_WATCHDOG_EN 0x0028 | |
34 | #define SIRFSOC_TIMER_DIV 0x002C | |
35 | #define SIRFSOC_TIMER_LATCH 0x0030 | |
36 | #define SIRFSOC_TIMER_LATCHED_LO 0x0034 | |
37 | #define SIRFSOC_TIMER_LATCHED_HI 0x0038 | |
38 | ||
39 | #define SIRFSOC_TIMER_WDT_INDEX 5 | |
40 | ||
41 | #define SIRFSOC_TIMER_LATCH_BIT BIT(0) | |
42 | ||
e5598a85 BS |
43 | #define SIRFSOC_TIMER_REG_CNT 11 |
44 | ||
45 | static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { | |
46 | SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2, | |
47 | SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5, | |
48 | SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV, | |
49 | SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI, | |
50 | }; | |
51 | ||
52 | static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; | |
53 | ||
02c981c0 BD |
54 | static void __iomem *sirfsoc_timer_base; |
55 | static void __init sirfsoc_of_timer_map(void); | |
56 | ||
57 | /* timer0 interrupt handler */ | |
58 | static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) | |
59 | { | |
60 | struct clock_event_device *ce = dev_id; | |
61 | ||
62 | WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0))); | |
63 | ||
64 | /* clear timer0 interrupt */ | |
65 | writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); | |
66 | ||
67 | ce->event_handler(ce); | |
68 | ||
69 | return IRQ_HANDLED; | |
70 | } | |
71 | ||
72 | /* read 64-bit timer counter */ | |
73 | static cycle_t sirfsoc_timer_read(struct clocksource *cs) | |
74 | { | |
75 | u64 cycles; | |
76 | ||
77 | /* latch the 64-bit timer counter */ | |
78 | writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); | |
79 | cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); | |
80 | cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); | |
81 | ||
82 | return cycles; | |
83 | } | |
84 | ||
85 | static int sirfsoc_timer_set_next_event(unsigned long delta, | |
86 | struct clock_event_device *ce) | |
87 | { | |
88 | unsigned long now, next; | |
89 | ||
90 | writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); | |
91 | now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); | |
92 | next = now + delta; | |
93 | writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); | |
94 | writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); | |
95 | now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); | |
96 | ||
97 | return next - now > delta ? -ETIME : 0; | |
98 | } | |
99 | ||
100 | static void sirfsoc_timer_set_mode(enum clock_event_mode mode, | |
101 | struct clock_event_device *ce) | |
102 | { | |
103 | u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); | |
104 | switch (mode) { | |
105 | case CLOCK_EVT_MODE_PERIODIC: | |
106 | WARN_ON(1); | |
107 | break; | |
108 | case CLOCK_EVT_MODE_ONESHOT: | |
109 | writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); | |
110 | break; | |
111 | case CLOCK_EVT_MODE_SHUTDOWN: | |
112 | writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); | |
113 | break; | |
114 | case CLOCK_EVT_MODE_UNUSED: | |
115 | case CLOCK_EVT_MODE_RESUME: | |
116 | break; | |
117 | } | |
118 | } | |
119 | ||
e5598a85 BS |
120 | static void sirfsoc_clocksource_suspend(struct clocksource *cs) |
121 | { | |
122 | int i; | |
123 | ||
124 | writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); | |
125 | ||
126 | for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) | |
127 | sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); | |
128 | } | |
129 | ||
130 | static void sirfsoc_clocksource_resume(struct clocksource *cs) | |
131 | { | |
132 | int i; | |
133 | ||
134 | for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) | |
135 | writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); | |
136 | ||
137 | writel_relaxed(sirfsoc_timer_reg_val[i - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); | |
138 | writel_relaxed(sirfsoc_timer_reg_val[i - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); | |
139 | } | |
140 | ||
02c981c0 BD |
141 | static struct clock_event_device sirfsoc_clockevent = { |
142 | .name = "sirfsoc_clockevent", | |
143 | .rating = 200, | |
144 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
145 | .set_mode = sirfsoc_timer_set_mode, | |
146 | .set_next_event = sirfsoc_timer_set_next_event, | |
147 | }; | |
148 | ||
149 | static struct clocksource sirfsoc_clocksource = { | |
150 | .name = "sirfsoc_clocksource", | |
151 | .rating = 200, | |
152 | .mask = CLOCKSOURCE_MASK(64), | |
153 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
154 | .read = sirfsoc_timer_read, | |
e5598a85 BS |
155 | .suspend = sirfsoc_clocksource_suspend, |
156 | .resume = sirfsoc_clocksource_resume, | |
02c981c0 BD |
157 | }; |
158 | ||
159 | static struct irqaction sirfsoc_timer_irq = { | |
160 | .name = "sirfsoc_timer0", | |
161 | .flags = IRQF_TIMER, | |
162 | .irq = 0, | |
163 | .handler = sirfsoc_timer_interrupt, | |
164 | .dev_id = &sirfsoc_clockevent, | |
165 | }; | |
166 | ||
167 | /* Overwrite weak default sched_clock with more precise one */ | |
168 | unsigned long long notrace sched_clock(void) | |
169 | { | |
f70fc57e | 170 | static int is_mapped; |
02c981c0 BD |
171 | |
172 | /* | |
173 | * sched_clock is called earlier than .init of sys_timer | |
174 | * if we map timer memory in .init of sys_timer, system | |
175 | * will panic due to illegal memory access | |
176 | */ | |
c6b96c54 | 177 | if (!is_mapped) { |
02c981c0 BD |
178 | sirfsoc_of_timer_map(); |
179 | is_mapped = 1; | |
180 | } | |
181 | ||
182 | return sirfsoc_timer_read(NULL) * (NSEC_PER_SEC / CLOCK_TICK_RATE); | |
183 | } | |
184 | ||
185 | static void __init sirfsoc_clockevent_init(void) | |
186 | { | |
187 | clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60); | |
188 | ||
189 | sirfsoc_clockevent.max_delta_ns = | |
190 | clockevent_delta2ns(-2, &sirfsoc_clockevent); | |
191 | sirfsoc_clockevent.min_delta_ns = | |
192 | clockevent_delta2ns(2, &sirfsoc_clockevent); | |
193 | ||
194 | sirfsoc_clockevent.cpumask = cpumask_of(0); | |
195 | clockevents_register_device(&sirfsoc_clockevent); | |
196 | } | |
197 | ||
198 | /* initialize the kernel jiffy timer source */ | |
199 | static void __init sirfsoc_timer_init(void) | |
200 | { | |
201 | unsigned long rate; | |
202 | ||
203 | /* timer's input clock is io clock */ | |
204 | struct clk *clk = clk_get_sys("io", NULL); | |
205 | ||
206 | BUG_ON(IS_ERR(clk)); | |
207 | ||
208 | rate = clk_get_rate(clk); | |
209 | ||
210 | BUG_ON(rate < CLOCK_TICK_RATE); | |
211 | BUG_ON(rate % CLOCK_TICK_RATE); | |
212 | ||
213 | writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); | |
214 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); | |
215 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); | |
216 | writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); | |
217 | ||
218 | BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); | |
219 | ||
220 | BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); | |
221 | ||
222 | sirfsoc_clockevent_init(); | |
223 | } | |
224 | ||
225 | static struct of_device_id timer_ids[] = { | |
226 | { .compatible = "sirf,prima2-tick" }, | |
6a53747b | 227 | {}, |
02c981c0 BD |
228 | }; |
229 | ||
230 | static void __init sirfsoc_of_timer_map(void) | |
231 | { | |
232 | struct device_node *np; | |
233 | const unsigned int *intspec; | |
234 | ||
235 | np = of_find_matching_node(NULL, timer_ids); | |
236 | if (!np) | |
237 | panic("unable to find compatible timer node in dtb\n"); | |
238 | sirfsoc_timer_base = of_iomap(np, 0); | |
239 | if (!sirfsoc_timer_base) | |
240 | panic("unable to map timer cpu registers\n"); | |
241 | ||
242 | /* Get the interrupts property */ | |
243 | intspec = of_get_property(np, "interrupts", NULL); | |
244 | BUG_ON(!intspec); | |
245 | sirfsoc_timer_irq.irq = be32_to_cpup(intspec); | |
246 | ||
247 | of_node_put(np); | |
248 | } | |
249 | ||
250 | struct sys_timer sirfsoc_timer = { | |
251 | .init = sirfsoc_timer_init, | |
252 | }; |