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02c981c0 BD |
1 | /* |
2 | * System timer for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/clockchips.h> | |
12 | #include <linux/clocksource.h> | |
13 | #include <linux/bitops.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <mach/map.h> | |
bc8d849d | 21 | #include <asm/sched_clock.h> |
02c981c0 BD |
22 | #include <asm/mach/time.h> |
23 | ||
24 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 | |
25 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 | |
26 | #define SIRFSOC_TIMER_MATCH_0 0x0008 | |
27 | #define SIRFSOC_TIMER_MATCH_1 0x000C | |
28 | #define SIRFSOC_TIMER_MATCH_2 0x0010 | |
29 | #define SIRFSOC_TIMER_MATCH_3 0x0014 | |
30 | #define SIRFSOC_TIMER_MATCH_4 0x0018 | |
31 | #define SIRFSOC_TIMER_MATCH_5 0x001C | |
32 | #define SIRFSOC_TIMER_STATUS 0x0020 | |
33 | #define SIRFSOC_TIMER_INT_EN 0x0024 | |
34 | #define SIRFSOC_TIMER_WATCHDOG_EN 0x0028 | |
35 | #define SIRFSOC_TIMER_DIV 0x002C | |
36 | #define SIRFSOC_TIMER_LATCH 0x0030 | |
37 | #define SIRFSOC_TIMER_LATCHED_LO 0x0034 | |
38 | #define SIRFSOC_TIMER_LATCHED_HI 0x0038 | |
39 | ||
40 | #define SIRFSOC_TIMER_WDT_INDEX 5 | |
41 | ||
42 | #define SIRFSOC_TIMER_LATCH_BIT BIT(0) | |
43 | ||
e5598a85 BS |
44 | #define SIRFSOC_TIMER_REG_CNT 11 |
45 | ||
46 | static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { | |
47 | SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2, | |
48 | SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5, | |
49 | SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV, | |
50 | SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI, | |
51 | }; | |
52 | ||
53 | static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; | |
54 | ||
02c981c0 BD |
55 | static void __iomem *sirfsoc_timer_base; |
56 | static void __init sirfsoc_of_timer_map(void); | |
57 | ||
58 | /* timer0 interrupt handler */ | |
59 | static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) | |
60 | { | |
61 | struct clock_event_device *ce = dev_id; | |
62 | ||
63 | WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0))); | |
64 | ||
65 | /* clear timer0 interrupt */ | |
66 | writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); | |
67 | ||
68 | ce->event_handler(ce); | |
69 | ||
70 | return IRQ_HANDLED; | |
71 | } | |
72 | ||
73 | /* read 64-bit timer counter */ | |
74 | static cycle_t sirfsoc_timer_read(struct clocksource *cs) | |
75 | { | |
76 | u64 cycles; | |
77 | ||
78 | /* latch the 64-bit timer counter */ | |
79 | writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); | |
80 | cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); | |
81 | cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); | |
82 | ||
83 | return cycles; | |
84 | } | |
85 | ||
86 | static int sirfsoc_timer_set_next_event(unsigned long delta, | |
87 | struct clock_event_device *ce) | |
88 | { | |
89 | unsigned long now, next; | |
90 | ||
91 | writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); | |
92 | now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); | |
93 | next = now + delta; | |
94 | writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); | |
95 | writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); | |
96 | now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); | |
97 | ||
98 | return next - now > delta ? -ETIME : 0; | |
99 | } | |
100 | ||
101 | static void sirfsoc_timer_set_mode(enum clock_event_mode mode, | |
102 | struct clock_event_device *ce) | |
103 | { | |
104 | u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); | |
105 | switch (mode) { | |
106 | case CLOCK_EVT_MODE_PERIODIC: | |
107 | WARN_ON(1); | |
108 | break; | |
109 | case CLOCK_EVT_MODE_ONESHOT: | |
110 | writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); | |
111 | break; | |
112 | case CLOCK_EVT_MODE_SHUTDOWN: | |
113 | writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); | |
114 | break; | |
115 | case CLOCK_EVT_MODE_UNUSED: | |
116 | case CLOCK_EVT_MODE_RESUME: | |
117 | break; | |
118 | } | |
119 | } | |
120 | ||
e5598a85 BS |
121 | static void sirfsoc_clocksource_suspend(struct clocksource *cs) |
122 | { | |
123 | int i; | |
124 | ||
125 | writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); | |
126 | ||
127 | for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) | |
128 | sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); | |
129 | } | |
130 | ||
131 | static void sirfsoc_clocksource_resume(struct clocksource *cs) | |
132 | { | |
133 | int i; | |
134 | ||
135 | for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) | |
136 | writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); | |
137 | ||
138 | writel_relaxed(sirfsoc_timer_reg_val[i - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); | |
139 | writel_relaxed(sirfsoc_timer_reg_val[i - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); | |
140 | } | |
141 | ||
02c981c0 BD |
142 | static struct clock_event_device sirfsoc_clockevent = { |
143 | .name = "sirfsoc_clockevent", | |
144 | .rating = 200, | |
145 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
146 | .set_mode = sirfsoc_timer_set_mode, | |
147 | .set_next_event = sirfsoc_timer_set_next_event, | |
148 | }; | |
149 | ||
150 | static struct clocksource sirfsoc_clocksource = { | |
151 | .name = "sirfsoc_clocksource", | |
152 | .rating = 200, | |
153 | .mask = CLOCKSOURCE_MASK(64), | |
154 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
155 | .read = sirfsoc_timer_read, | |
e5598a85 BS |
156 | .suspend = sirfsoc_clocksource_suspend, |
157 | .resume = sirfsoc_clocksource_resume, | |
02c981c0 BD |
158 | }; |
159 | ||
160 | static struct irqaction sirfsoc_timer_irq = { | |
161 | .name = "sirfsoc_timer0", | |
162 | .flags = IRQF_TIMER, | |
163 | .irq = 0, | |
164 | .handler = sirfsoc_timer_interrupt, | |
165 | .dev_id = &sirfsoc_clockevent, | |
166 | }; | |
167 | ||
168 | /* Overwrite weak default sched_clock with more precise one */ | |
bc8d849d | 169 | static u32 notrace sirfsoc_read_sched_clock(void) |
02c981c0 | 170 | { |
bc8d849d | 171 | return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff); |
02c981c0 BD |
172 | } |
173 | ||
174 | static void __init sirfsoc_clockevent_init(void) | |
175 | { | |
176 | clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60); | |
177 | ||
178 | sirfsoc_clockevent.max_delta_ns = | |
179 | clockevent_delta2ns(-2, &sirfsoc_clockevent); | |
180 | sirfsoc_clockevent.min_delta_ns = | |
181 | clockevent_delta2ns(2, &sirfsoc_clockevent); | |
182 | ||
183 | sirfsoc_clockevent.cpumask = cpumask_of(0); | |
184 | clockevents_register_device(&sirfsoc_clockevent); | |
185 | } | |
186 | ||
187 | /* initialize the kernel jiffy timer source */ | |
188 | static void __init sirfsoc_timer_init(void) | |
189 | { | |
190 | unsigned long rate; | |
191 | ||
192 | /* timer's input clock is io clock */ | |
193 | struct clk *clk = clk_get_sys("io", NULL); | |
194 | ||
195 | BUG_ON(IS_ERR(clk)); | |
196 | ||
197 | rate = clk_get_rate(clk); | |
198 | ||
199 | BUG_ON(rate < CLOCK_TICK_RATE); | |
200 | BUG_ON(rate % CLOCK_TICK_RATE); | |
201 | ||
bc8d849d MZ |
202 | sirfsoc_of_timer_map(); |
203 | ||
02c981c0 BD |
204 | writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); |
205 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); | |
206 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); | |
207 | writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); | |
208 | ||
209 | BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); | |
210 | ||
bc8d849d MZ |
211 | setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE); |
212 | ||
02c981c0 BD |
213 | BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); |
214 | ||
215 | sirfsoc_clockevent_init(); | |
216 | } | |
217 | ||
218 | static struct of_device_id timer_ids[] = { | |
219 | { .compatible = "sirf,prima2-tick" }, | |
6a53747b | 220 | {}, |
02c981c0 BD |
221 | }; |
222 | ||
223 | static void __init sirfsoc_of_timer_map(void) | |
224 | { | |
225 | struct device_node *np; | |
226 | const unsigned int *intspec; | |
227 | ||
228 | np = of_find_matching_node(NULL, timer_ids); | |
229 | if (!np) | |
230 | panic("unable to find compatible timer node in dtb\n"); | |
231 | sirfsoc_timer_base = of_iomap(np, 0); | |
232 | if (!sirfsoc_timer_base) | |
233 | panic("unable to map timer cpu registers\n"); | |
234 | ||
235 | /* Get the interrupts property */ | |
236 | intspec = of_get_property(np, "interrupts", NULL); | |
237 | BUG_ON(!intspec); | |
238 | sirfsoc_timer_irq.irq = be32_to_cpup(intspec); | |
239 | ||
240 | of_node_put(np); | |
241 | } | |
242 | ||
243 | struct sys_timer sirfsoc_timer = { | |
244 | .init = sirfsoc_timer_init, | |
245 | }; |