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9e2697ff | 1 | /* |
0d1bde9e | 2 | * linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c |
9e2697ff RK |
3 | * |
4 | * Copyright (C) 2002,2003 Intrinsyc Software | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | * History: | |
21 | * 31-Jul-2002 : Initial version [FB] | |
22 | * 29-Jan-2003 : added PXA255 support [FB] | |
23 | * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) | |
24 | * | |
25 | * Note: | |
26 | * This driver may change the memory bus clock rate, but will not do any | |
27 | * platform specific access timing changes... for example if you have flash | |
28 | * memory connected to CS0, you will need to register a platform specific | |
29 | * notifier which will adjust the memory access strobes to maintain a | |
30 | * minimum strobe width. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/sched.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/cpufreq.h> | |
3dbeef23 RJ |
39 | #include <linux/err.h> |
40 | #include <linux/regulator/consumer.h> | |
9e2697ff | 41 | |
a09e64fb | 42 | #include <mach/pxa2xx-regs.h> |
9e2697ff RK |
43 | |
44 | #ifdef DEBUG | |
45 | static unsigned int freq_debug; | |
c710e39c | 46 | module_param(freq_debug, uint, 0); |
9e2697ff RK |
47 | MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); |
48 | #else | |
49 | #define freq_debug 0 | |
50 | #endif | |
51 | ||
3dbeef23 RJ |
52 | static struct regulator *vcc_core; |
53 | ||
592eb999 RJ |
54 | static unsigned int pxa27x_maxfreq; |
55 | module_param(pxa27x_maxfreq, uint, 0); | |
56 | MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz" | |
57 | "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)"); | |
58 | ||
9e2697ff RK |
59 | typedef struct { |
60 | unsigned int khz; | |
61 | unsigned int membus; | |
62 | unsigned int cccr; | |
63 | unsigned int div2; | |
592eb999 | 64 | unsigned int cclkcfg; |
3dbeef23 RJ |
65 | int vmin; |
66 | int vmax; | |
9e2697ff RK |
67 | } pxa_freqs_t; |
68 | ||
69 | /* Define the refresh period in mSec for the SDRAM and the number of rows */ | |
3679389b | 70 | #define SDRAM_TREF 64 /* standard 64ms SDRAM */ |
a10c287d | 71 | static unsigned int sdram_rows; |
9e2697ff | 72 | |
3679389b RJ |
73 | #define CCLKCFG_TURBO 0x1 |
74 | #define CCLKCFG_FCS 0x2 | |
592eb999 RJ |
75 | #define CCLKCFG_HALFTURBO 0x4 |
76 | #define CCLKCFG_FASTBUS 0x8 | |
3679389b RJ |
77 | #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) |
78 | #define MDREFR_DRI_MASK 0xFFF | |
9e2697ff | 79 | |
a10c287d PZ |
80 | #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) |
81 | #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) | |
82 | ||
592eb999 RJ |
83 | /* |
84 | * PXA255 definitions | |
85 | */ | |
9e2697ff | 86 | /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ |
592eb999 RJ |
87 | #define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS |
88 | ||
9e2697ff RK |
89 | static pxa_freqs_t pxa255_run_freqs[] = |
90 | { | |
3dbeef23 RJ |
91 | /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ |
92 | { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */ | |
93 | {132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */ | |
94 | {199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */ | |
95 | {265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */ | |
96 | {331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */ | |
97 | {398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */ | |
9e2697ff | 98 | }; |
9e2697ff RK |
99 | |
100 | /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ | |
101 | static pxa_freqs_t pxa255_turbo_freqs[] = | |
102 | { | |
592eb999 | 103 | /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ |
3dbeef23 RJ |
104 | { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */ |
105 | {199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */ | |
106 | {298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */ | |
107 | {298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */ | |
108 | {398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */ | |
9e2697ff | 109 | }; |
9e2697ff | 110 | |
592eb999 RJ |
111 | #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs) |
112 | #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs) | |
113 | ||
114 | static struct cpufreq_frequency_table | |
115 | pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1]; | |
3679389b | 116 | static struct cpufreq_frequency_table |
592eb999 RJ |
117 | pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; |
118 | ||
65587f7d MZ |
119 | static unsigned int pxa255_turbo_table; |
120 | module_param(pxa255_turbo_table, uint, 0); | |
121 | MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)"); | |
122 | ||
592eb999 RJ |
123 | /* |
124 | * PXA270 definitions | |
125 | * | |
126 | * For the PXA27x: | |
127 | * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG. | |
128 | * | |
129 | * A = 0 => memory controller clock from table 3-7, | |
130 | * A = 1 => memory controller clock = system bus clock | |
131 | * Run mode frequency = 13 MHz * L | |
132 | * Turbo mode frequency = 13 MHz * L * N | |
133 | * System bus frequency = 13 MHz * L / (B + 1) | |
134 | * | |
135 | * In CCCR: | |
136 | * A = 1 | |
137 | * L = 16 oscillator to run mode ratio | |
138 | * 2N = 6 2 * (turbo mode to run mode ratio) | |
139 | * | |
140 | * In CCLKCFG: | |
141 | * B = 1 Fast bus mode | |
142 | * HT = 0 Half-Turbo mode | |
143 | * T = 1 Turbo mode | |
144 | * | |
145 | * For now, just support some of the combinations in table 3-7 of | |
146 | * PXA27x Processor Family Developer's Manual to simplify frequency | |
147 | * change sequences. | |
148 | */ | |
149 | #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) | |
150 | #define CCLKCFG2(B, HT, T) \ | |
151 | (CCLKCFG_FCS | \ | |
152 | ((B) ? CCLKCFG_FASTBUS : 0) | \ | |
153 | ((HT) ? CCLKCFG_HALFTURBO : 0) | \ | |
154 | ((T) ? CCLKCFG_TURBO : 0)) | |
155 | ||
156 | static pxa_freqs_t pxa27x_freqs[] = { | |
3dbeef23 | 157 | {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 }, |
4367216a | 158 | {156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 }, |
3dbeef23 RJ |
159 | {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 }, |
160 | {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 }, | |
161 | {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 }, | |
162 | {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 }, | |
163 | {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 } | |
592eb999 RJ |
164 | }; |
165 | ||
166 | #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs) | |
167 | static struct cpufreq_frequency_table | |
168 | pxa27x_freq_table[NUM_PXA27x_FREQS+1]; | |
9e2697ff RK |
169 | |
170 | extern unsigned get_clk_frequency_khz(int info); | |
171 | ||
3dbeef23 RJ |
172 | #ifdef CONFIG_REGULATOR |
173 | ||
174 | static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq) | |
175 | { | |
176 | int ret = 0; | |
177 | int vmin, vmax; | |
178 | ||
179 | if (!cpu_is_pxa27x()) | |
180 | return 0; | |
181 | ||
182 | vmin = pxa_freq->vmin; | |
183 | vmax = pxa_freq->vmax; | |
184 | if ((vmin == -1) || (vmax == -1)) | |
185 | return 0; | |
186 | ||
187 | ret = regulator_set_voltage(vcc_core, vmin, vmax); | |
188 | if (ret) | |
189 | pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n", | |
190 | vmin, vmax); | |
191 | return ret; | |
192 | } | |
193 | ||
194 | static __init void pxa_cpufreq_init_voltages(void) | |
195 | { | |
196 | vcc_core = regulator_get(NULL, "vcc_core"); | |
197 | if (IS_ERR(vcc_core)) { | |
198 | pr_info("cpufreq: Didn't find vcc_core regulator\n"); | |
199 | vcc_core = NULL; | |
200 | } else { | |
201 | pr_info("cpufreq: Found vcc_core regulator\n"); | |
202 | } | |
203 | } | |
204 | #else | |
205 | static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq) | |
206 | { | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static __init void pxa_cpufreq_init_voltages(void) { } | |
211 | #endif | |
212 | ||
65587f7d | 213 | static void find_freq_tables(struct cpufreq_frequency_table **freq_table, |
592eb999 RJ |
214 | pxa_freqs_t **pxa_freqs) |
215 | { | |
216 | if (cpu_is_pxa25x()) { | |
65587f7d | 217 | if (!pxa255_turbo_table) { |
592eb999 RJ |
218 | *pxa_freqs = pxa255_run_freqs; |
219 | *freq_table = pxa255_run_freq_table; | |
65587f7d | 220 | } else { |
592eb999 RJ |
221 | *pxa_freqs = pxa255_turbo_freqs; |
222 | *freq_table = pxa255_turbo_freq_table; | |
592eb999 RJ |
223 | } |
224 | } | |
225 | if (cpu_is_pxa27x()) { | |
226 | *pxa_freqs = pxa27x_freqs; | |
227 | *freq_table = pxa27x_freq_table; | |
228 | } | |
229 | } | |
230 | ||
231 | static void pxa27x_guess_max_freq(void) | |
232 | { | |
233 | if (!pxa27x_maxfreq) { | |
234 | pxa27x_maxfreq = 416000; | |
235 | printk(KERN_INFO "PXA CPU 27x max frequency not defined " | |
236 | "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n", | |
237 | pxa27x_maxfreq); | |
238 | } else { | |
239 | pxa27x_maxfreq *= 1000; | |
240 | } | |
241 | } | |
242 | ||
a10c287d PZ |
243 | static void init_sdram_rows(void) |
244 | { | |
245 | uint32_t mdcnfg = MDCNFG; | |
246 | unsigned int drac2 = 0, drac0 = 0; | |
247 | ||
248 | if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) | |
249 | drac2 = MDCNFG_DRAC2(mdcnfg); | |
250 | ||
251 | if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) | |
252 | drac0 = MDCNFG_DRAC0(mdcnfg); | |
253 | ||
254 | sdram_rows = 1 << (11 + max(drac0, drac2)); | |
255 | } | |
256 | ||
592eb999 RJ |
257 | static u32 mdrefr_dri(unsigned int freq) |
258 | { | |
3d3d0fbf | 259 | u32 interval = freq * SDRAM_TREF / sdram_rows; |
592eb999 | 260 | |
3d3d0fbf | 261 | return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32; |
592eb999 RJ |
262 | } |
263 | ||
9e2697ff RK |
264 | /* find a valid frequency point */ |
265 | static int pxa_verify_policy(struct cpufreq_policy *policy) | |
266 | { | |
267 | struct cpufreq_frequency_table *pxa_freqs_table; | |
592eb999 | 268 | pxa_freqs_t *pxa_freqs; |
9e2697ff RK |
269 | int ret; |
270 | ||
65587f7d | 271 | find_freq_tables(&pxa_freqs_table, &pxa_freqs); |
9e2697ff RK |
272 | ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); |
273 | ||
274 | if (freq_debug) | |
275 | pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n", | |
3679389b | 276 | policy->min, policy->max); |
9e2697ff RK |
277 | |
278 | return ret; | |
279 | } | |
280 | ||
592eb999 RJ |
281 | static unsigned int pxa_cpufreq_get(unsigned int cpu) |
282 | { | |
283 | return get_clk_frequency_khz(0); | |
284 | } | |
285 | ||
9e2697ff | 286 | static int pxa_set_target(struct cpufreq_policy *policy, |
3679389b RJ |
287 | unsigned int target_freq, |
288 | unsigned int relation) | |
9e2697ff RK |
289 | { |
290 | struct cpufreq_frequency_table *pxa_freqs_table; | |
291 | pxa_freqs_t *pxa_freq_settings; | |
292 | struct cpufreq_freqs freqs; | |
ea833f0b | 293 | unsigned int idx; |
9e2697ff | 294 | unsigned long flags; |
592eb999 RJ |
295 | unsigned int new_freq_cpu, new_freq_mem; |
296 | unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; | |
3dbeef23 | 297 | int ret = 0; |
9e2697ff RK |
298 | |
299 | /* Get the current policy */ | |
65587f7d | 300 | find_freq_tables(&pxa_freqs_table, &pxa_freq_settings); |
9e2697ff RK |
301 | |
302 | /* Lookup the next frequency */ | |
303 | if (cpufreq_frequency_table_target(policy, pxa_freqs_table, | |
3679389b | 304 | target_freq, relation, &idx)) { |
9e2697ff RK |
305 | return -EINVAL; |
306 | } | |
307 | ||
592eb999 RJ |
308 | new_freq_cpu = pxa_freq_settings[idx].khz; |
309 | new_freq_mem = pxa_freq_settings[idx].membus; | |
9e2697ff | 310 | freqs.old = policy->cur; |
592eb999 | 311 | freqs.new = new_freq_cpu; |
9e2697ff RK |
312 | freqs.cpu = policy->cpu; |
313 | ||
314 | if (freq_debug) | |
3679389b RJ |
315 | pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, " |
316 | "(SDRAM %d Mhz)\n", | |
317 | freqs.new / 1000, (pxa_freq_settings[idx].div2) ? | |
592eb999 | 318 | (new_freq_mem / 2000) : (new_freq_mem / 1000)); |
9e2697ff | 319 | |
3dbeef23 RJ |
320 | if (vcc_core && freqs.new > freqs.old) |
321 | ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]); | |
322 | if (ret) | |
323 | return ret; | |
9e2697ff RK |
324 | /* |
325 | * Tell everyone what we're about to do... | |
326 | * you should add a notify client with any platform specific | |
327 | * Vcc changing capability | |
328 | */ | |
329 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
330 | ||
331 | /* Calculate the next MDREFR. If we're slowing down the SDRAM clock | |
3679389b RJ |
332 | * we need to preset the smaller DRI before the change. If we're |
333 | * speeding up we need to set the larger DRI value after the change. | |
9e2697ff RK |
334 | */ |
335 | preset_mdrefr = postset_mdrefr = MDREFR; | |
592eb999 RJ |
336 | if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { |
337 | preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); | |
338 | preset_mdrefr |= mdrefr_dri(new_freq_mem); | |
9e2697ff | 339 | } |
592eb999 RJ |
340 | postset_mdrefr = |
341 | (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem); | |
9e2697ff RK |
342 | |
343 | /* If we're dividing the memory clock by two for the SDRAM clock, this | |
344 | * must be set prior to the change. Clearing the divide must be done | |
345 | * after the change. | |
346 | */ | |
347 | if (pxa_freq_settings[idx].div2) { | |
348 | preset_mdrefr |= MDREFR_DB2_MASK; | |
349 | postset_mdrefr |= MDREFR_DB2_MASK; | |
350 | } else { | |
351 | postset_mdrefr &= ~MDREFR_DB2_MASK; | |
352 | } | |
353 | ||
354 | local_irq_save(flags); | |
355 | ||
592eb999 | 356 | /* Set new the CCCR and prepare CCLKCFG */ |
9e2697ff | 357 | CCCR = pxa_freq_settings[idx].cccr; |
592eb999 | 358 | cclkcfg = pxa_freq_settings[idx].cclkcfg; |
9e2697ff RK |
359 | |
360 | asm volatile(" \n\ | |
361 | ldr r4, [%1] /* load MDREFR */ \n\ | |
362 | b 2f \n\ | |
3679389b | 363 | .align 5 \n\ |
9e2697ff | 364 | 1: \n\ |
592eb999 | 365 | str %3, [%1] /* preset the MDREFR */ \n\ |
9e2697ff | 366 | mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ |
592eb999 | 367 | str %4, [%1] /* postset the MDREFR */ \n\ |
9e2697ff RK |
368 | \n\ |
369 | b 3f \n\ | |
370 | 2: b 1b \n\ | |
371 | 3: nop \n\ | |
372 | " | |
3679389b | 373 | : "=&r" (unused) |
592eb999 RJ |
374 | : "r" (&MDREFR), "r" (cclkcfg), |
375 | "r" (preset_mdrefr), "r" (postset_mdrefr) | |
3679389b | 376 | : "r4", "r5"); |
9e2697ff RK |
377 | local_irq_restore(flags); |
378 | ||
379 | /* | |
380 | * Tell everyone what we've just done... | |
381 | * you should add a notify client with any platform specific | |
382 | * SDRAM refresh timer adjustments | |
383 | */ | |
384 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
385 | ||
3dbeef23 RJ |
386 | /* |
387 | * Even if voltage setting fails, we don't report it, as the frequency | |
388 | * change succeeded. The voltage reduction is not a critical failure, | |
389 | * only power savings will suffer from this. | |
390 | * | |
391 | * Note: if the voltage change fails, and a return value is returned, a | |
392 | * bug is triggered (seems a deadlock). Should anybody find out where, | |
393 | * the "return 0" should become a "return ret". | |
394 | */ | |
395 | if (vcc_core && freqs.new < freqs.old) | |
396 | ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]); | |
397 | ||
9e2697ff RK |
398 | return 0; |
399 | } | |
400 | ||
592eb999 | 401 | static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) |
9e2697ff RK |
402 | { |
403 | int i; | |
592eb999 | 404 | unsigned int freq; |
65587f7d MZ |
405 | struct cpufreq_frequency_table *pxa255_freq_table; |
406 | pxa_freqs_t *pxa255_freqs; | |
592eb999 RJ |
407 | |
408 | /* try to guess pxa27x cpu */ | |
409 | if (cpu_is_pxa27x()) | |
410 | pxa27x_guess_max_freq(); | |
9e2697ff | 411 | |
3dbeef23 RJ |
412 | pxa_cpufreq_init_voltages(); |
413 | ||
a10c287d PZ |
414 | init_sdram_rows(); |
415 | ||
9e2697ff | 416 | /* set default policy and cpuinfo */ |
9e2697ff | 417 | policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ |
3679389b | 418 | policy->cur = get_clk_frequency_khz(0); /* current freq */ |
9e2697ff RK |
419 | policy->min = policy->max = policy->cur; |
420 | ||
592eb999 RJ |
421 | /* Generate pxa25x the run cpufreq_frequency_table struct */ |
422 | for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) { | |
9e2697ff RK |
423 | pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; |
424 | pxa255_run_freq_table[i].index = i; | |
425 | } | |
9e2697ff | 426 | pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; |
592eb999 RJ |
427 | |
428 | /* Generate pxa25x the turbo cpufreq_frequency_table struct */ | |
429 | for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) { | |
3679389b RJ |
430 | pxa255_turbo_freq_table[i].frequency = |
431 | pxa255_turbo_freqs[i].khz; | |
9e2697ff RK |
432 | pxa255_turbo_freq_table[i].index = i; |
433 | } | |
434 | pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; | |
435 | ||
65587f7d MZ |
436 | pxa255_turbo_table = !!pxa255_turbo_table; |
437 | ||
592eb999 RJ |
438 | /* Generate the pxa27x cpufreq_frequency_table struct */ |
439 | for (i = 0; i < NUM_PXA27x_FREQS; i++) { | |
440 | freq = pxa27x_freqs[i].khz; | |
441 | if (freq > pxa27x_maxfreq) | |
442 | break; | |
443 | pxa27x_freq_table[i].frequency = freq; | |
444 | pxa27x_freq_table[i].index = i; | |
445 | } | |
68a31de3 | 446 | pxa27x_freq_table[i].index = i; |
592eb999 RJ |
447 | pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END; |
448 | ||
449 | /* | |
450 | * Set the policy's minimum and maximum frequencies from the tables | |
451 | * just constructed. This sets cpuinfo.mxx_freq, min and max. | |
452 | */ | |
65587f7d MZ |
453 | if (cpu_is_pxa25x()) { |
454 | find_freq_tables(&pxa255_freq_table, &pxa255_freqs); | |
455 | pr_info("PXA255 cpufreq using %s frequency table\n", | |
456 | pxa255_turbo_table ? "turbo" : "run"); | |
457 | cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table); | |
458 | } | |
592eb999 RJ |
459 | else if (cpu_is_pxa27x()) |
460 | cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table); | |
461 | ||
9e2697ff RK |
462 | printk(KERN_INFO "PXA CPU frequency change support initialized\n"); |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static struct cpufreq_driver pxa_cpufreq_driver = { | |
468 | .verify = pxa_verify_policy, | |
469 | .target = pxa_set_target, | |
470 | .init = pxa_cpufreq_init, | |
ea833f0b | 471 | .get = pxa_cpufreq_get, |
592eb999 | 472 | .name = "PXA2xx", |
9e2697ff RK |
473 | }; |
474 | ||
475 | static int __init pxa_cpu_init(void) | |
476 | { | |
477 | int ret = -ENODEV; | |
592eb999 | 478 | if (cpu_is_pxa25x() || cpu_is_pxa27x()) |
9e2697ff RK |
479 | ret = cpufreq_register_driver(&pxa_cpufreq_driver); |
480 | return ret; | |
481 | } | |
482 | ||
483 | static void __exit pxa_cpu_exit(void) | |
484 | { | |
592eb999 | 485 | cpufreq_unregister_driver(&pxa_cpufreq_driver); |
9e2697ff RK |
486 | } |
487 | ||
488 | ||
3679389b RJ |
489 | MODULE_AUTHOR("Intrinsyc Software Inc."); |
490 | MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture"); | |
9e2697ff RK |
491 | MODULE_LICENSE("GPL"); |
492 | module_init(pxa_cpu_init); | |
493 | module_exit(pxa_cpu_exit); |