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ARM: pxa: add memory resource to SA1100 RTC device
[deliverable/linux.git] / arch / arm / mach-pxa / devices.c
CommitLineData
8f58de7c 1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/platform_device.h>
5#include <linux/dma-mapping.h>
8348c259 6#include <linux/spi/pxa2xx_spi.h>
b459396e 7#include <linux/i2c/pxa-i2c.h>
8f58de7c 8
a09e64fb 9#include <mach/udc.h>
293b2da1
AB		 10#include <linux/platform_data/usb-pxa3xx-ulpi.h>
11#include <linux/platform_data/video-pxafb.h>
12#include <linux/platform_data/mmc-pxamci.h>
13#include <linux/platform_data/irda-pxaficp.h>
4e611091 14#include <mach/irqs.h>
293b2da1
AB		 15#include <linux/platform_data/usb-ohci-pxa27x.h>
16#include <linux/platform_data/keypad-pxa27x.h>
17#include <linux/platform_data/camera-pxa.h>
a09e64fb 18#include <mach/audio.h>
75e874c6 19#include <mach/hardware.h>
4be0856f 20#include <linux/platform_data/mmp_dma.h>
293b2da1 21#include <linux/platform_data/mtd-nand-pxa3xx.h>
8f58de7c 22
23#include "devices.h"
bc3a5959 24#include "generic.h"
8f58de7c 25
26void __init pxa_register_device(struct platform_device *dev, void *data)
27{
28 int ret;
29
30 dev->dev.platform_data = data;
31
32 ret = platform_device_register(dev);
33 if (ret)
34 dev_err(&dev->dev, "unable to register device: %d\n", ret);
35}
36
09a5358d
EM		 37static struct resource pxa_resource_pmu = {
38 .start = IRQ_PMU,
39 .end = IRQ_PMU,
40 .flags = IORESOURCE_IRQ,
41};
42
43struct platform_device pxa_device_pmu = {
f9eff219 44 .name = "xscale-pmu",
df3d17e0 45 .id = -1,
09a5358d
EM		 46 .resource = &pxa_resource_pmu,
47 .num_resources = 1,
48};
49
8f58de7c 50static struct resource pxamci_resources[] = {
51 [0] = {
52 .start = 0x41100000,
53 .end = 0x41100fff,
54 .flags = IORESOURCE_MEM,
55 },
56 [1] = {
57 .start = IRQ_MMC,
58 .end = IRQ_MMC,
59 .flags = IORESOURCE_IRQ,
60 },
61 [2] = {
62 .start = 21,
63 .end = 21,
64 .flags = IORESOURCE_DMA,
65 },
66 [3] = {
67 .start = 22,
68 .end = 22,
69 .flags = IORESOURCE_DMA,
70 },
71};
72
73static u64 pxamci_dmamask = 0xffffffffUL;
74
75struct platform_device pxa_device_mci = {
76 .name = "pxa2xx-mci",
fafc9d3f 77 .id = 0,
8f58de7c 78 .dev = {
79 .dma_mask = &pxamci_dmamask,
80 .coherent_dma_mask = 0xffffffff,
81 },
82 .num_resources = ARRAY_SIZE(pxamci_resources),
83 .resource = pxamci_resources,
84};
85
86void __init pxa_set_mci_info(struct pxamci_platform_data *info)
87{
88 pxa_register_device(&pxa_device_mci, info);
89}
90
91
1257629b
PZ		 92static struct pxa2xx_udc_mach_info pxa_udc_info = {
93 .gpio_pullup = -1,
1257629b 94};
8f58de7c 95
96void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
97{
98 memcpy(&pxa_udc_info, info, sizeof *info);
99}
100
101static struct resource pxa2xx_udc_resources[] = {
102 [0] = {
103 .start = 0x40600000,
104 .end = 0x4060ffff,
105 .flags = IORESOURCE_MEM,
106 },
107 [1] = {
108 .start = IRQ_USB,
109 .end = IRQ_USB,
110 .flags = IORESOURCE_IRQ,
111 },
112};
113
114static u64 udc_dma_mask = ~(u32)0;
115
7a857620
PZ		 116struct platform_device pxa25x_device_udc = {
117 .name = "pxa25x-udc",
118 .id = -1,
119 .resource = pxa2xx_udc_resources,
120 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
121 .dev = {
122 .platform_data = &pxa_udc_info,
123 .dma_mask = &udc_dma_mask,
124 }
125};
126
127struct platform_device pxa27x_device_udc = {
128 .name = "pxa27x-udc",
8f58de7c 129 .id = -1,
130 .resource = pxa2xx_udc_resources,
131 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
132 .dev = {
133 .platform_data = &pxa_udc_info,
134 .dma_mask = &udc_dma_mask,
135 }
136};
137
69f22be7
IG		 138#ifdef CONFIG_PXA3xx
139static struct resource pxa3xx_u2d_resources[] = {
140 [0] = {
141 .start = 0x54100000,
142 .end = 0x54100fff,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = IRQ_USB2,
147 .end = IRQ_USB2,
148 .flags = IORESOURCE_IRQ,
149 },
150};
151
152struct platform_device pxa3xx_device_u2d = {
153 .name = "pxa3xx-u2d",
154 .id = -1,
155 .resource = pxa3xx_u2d_resources,
156 .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
157};
158
159void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
160{
161 pxa_register_device(&pxa3xx_device_u2d, info);
162}
163#endif /* CONFIG_PXA3xx */
164
8f58de7c 165static struct resource pxafb_resources[] = {
166 [0] = {
167 .start = 0x44000000,
168 .end = 0x4400ffff,
169 .flags = IORESOURCE_MEM,
170 },
171 [1] = {
172 .start = IRQ_LCD,
173 .end = IRQ_LCD,
174 .flags = IORESOURCE_IRQ,
175 },
176};
177
178static u64 fb_dma_mask = ~(u64)0;
179
180struct platform_device pxa_device_fb = {
181 .name = "pxa2xx-fb",
182 .id = -1,
183 .dev = {
184 .dma_mask = &fb_dma_mask,
185 .coherent_dma_mask = 0xffffffff,
186 },
187 .num_resources = ARRAY_SIZE(pxafb_resources),
188 .resource = pxafb_resources,
189};
190
4321e1a1 191void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
8f58de7c 192{
4321e1a1 193 pxa_device_fb.dev.parent = parent;
8f58de7c 194 pxa_register_device(&pxa_device_fb, info);
195}
196
8f58de7c 197static struct resource pxa_resource_ffuart[] = {
198 {
02f65262
EM		 199 .start = 0x40100000,
200 .end = 0x40100023,
8f58de7c 201 .flags = IORESOURCE_MEM,
202 }, {
203 .start = IRQ_FFUART,
204 .end = IRQ_FFUART,
205 .flags = IORESOURCE_IRQ,
206 }
207};
208
cc155c6f 209struct platform_device pxa_device_ffuart = {
8f58de7c 210 .name = "pxa2xx-uart",
211 .id = 0,
212 .resource = pxa_resource_ffuart,
213 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
214};
215
cc155c6f
RK		 216void __init pxa_set_ffuart_info(void *info)
217{
218 pxa_register_device(&pxa_device_ffuart, info);
219}
220
8f58de7c 221static struct resource pxa_resource_btuart[] = {
222 {
02f65262
EM		 223 .start = 0x40200000,
224 .end = 0x40200023,
8f58de7c 225 .flags = IORESOURCE_MEM,
226 }, {
227 .start = IRQ_BTUART,
228 .end = IRQ_BTUART,
229 .flags = IORESOURCE_IRQ,
230 }
231};
232
233struct platform_device pxa_device_btuart = {
234 .name = "pxa2xx-uart",
235 .id = 1,
236 .resource = pxa_resource_btuart,
237 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
238};
239
cc155c6f
RK		 240void __init pxa_set_btuart_info(void *info)
241{
242 pxa_register_device(&pxa_device_btuart, info);
243}
244
8f58de7c 245static struct resource pxa_resource_stuart[] = {
246 {
02f65262
EM		 247 .start = 0x40700000,
248 .end = 0x40700023,
8f58de7c 249 .flags = IORESOURCE_MEM,
250 }, {
251 .start = IRQ_STUART,
252 .end = IRQ_STUART,
253 .flags = IORESOURCE_IRQ,
254 }
255};
256
257struct platform_device pxa_device_stuart = {
258 .name = "pxa2xx-uart",
259 .id = 2,
260 .resource = pxa_resource_stuart,
261 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
262};
263
cc155c6f
RK		 264void __init pxa_set_stuart_info(void *info)
265{
266 pxa_register_device(&pxa_device_stuart, info);
267}
268
8f58de7c 269static struct resource pxa_resource_hwuart[] = {
270 {
02f65262
EM		 271 .start = 0x41600000,
272 .end = 0x4160002F,
8f58de7c 273 .flags = IORESOURCE_MEM,
274 }, {
275 .start = IRQ_HWUART,
276 .end = IRQ_HWUART,
277 .flags = IORESOURCE_IRQ,
278 }
279};
280
281struct platform_device pxa_device_hwuart = {
282 .name = "pxa2xx-uart",
283 .id = 3,
284 .resource = pxa_resource_hwuart,
285 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
286};
287
cc155c6f
RK		 288void __init pxa_set_hwuart_info(void *info)
289{
290 if (cpu_is_pxa255())
291 pxa_register_device(&pxa_device_hwuart, info);
292 else
293 pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
294}
295
8f58de7c 296static struct resource pxai2c_resources[] = {
297 {
298 .start = 0x40301680,
299 .end = 0x403016a3,
300 .flags = IORESOURCE_MEM,
301 }, {
302 .start = IRQ_I2C,
303 .end = IRQ_I2C,
304 .flags = IORESOURCE_IRQ,
305 },
306};
307
308struct platform_device pxa_device_i2c = {
309 .name = "pxa2xx-i2c",
310 .id = 0,
311 .resource = pxai2c_resources,
312 .num_resources = ARRAY_SIZE(pxai2c_resources),
313};
314
315void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
316{
317 pxa_register_device(&pxa_device_i2c, info);
318}
319
99464293
EM		 320#ifdef CONFIG_PXA27x
321static struct resource pxa27x_resources_i2c_power[] = {
322 {
323 .start = 0x40f00180,
324 .end = 0x40f001a3,
325 .flags = IORESOURCE_MEM,
326 }, {
327 .start = IRQ_PWRI2C,
328 .end = IRQ_PWRI2C,
329 .flags = IORESOURCE_IRQ,
330 },
331};
332
333struct platform_device pxa27x_device_i2c_power = {
334 .name = "pxa2xx-i2c",
335 .id = 1,
336 .resource = pxa27x_resources_i2c_power,
337 .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
338};
339#endif
340
8f58de7c 341static struct resource pxai2s_resources[] = {
342 {
343 .start = 0x40400000,
344 .end = 0x40400083,
345 .flags = IORESOURCE_MEM,
346 }, {
347 .start = IRQ_I2S,
348 .end = IRQ_I2S,
349 .flags = IORESOURCE_IRQ,
350 },
351};
352
353struct platform_device pxa_device_i2s = {
354 .name = "pxa2xx-i2s",
355 .id = -1,
356 .resource = pxai2s_resources,
357 .num_resources = ARRAY_SIZE(pxai2s_resources),
358};
359
f0fba2ad
LG		 360struct platform_device pxa_device_asoc_ssp1 = {
361 .name = "pxa-ssp-dai",
362 .id = 0,
363};
364
365struct platform_device pxa_device_asoc_ssp2= {
366 .name = "pxa-ssp-dai",
367 .id = 1,
368};
369
370struct platform_device pxa_device_asoc_ssp3 = {
371 .name = "pxa-ssp-dai",
372 .id = 2,
373};
374
375struct platform_device pxa_device_asoc_ssp4 = {
376 .name = "pxa-ssp-dai",
377 .id = 3,
378};
379
380struct platform_device pxa_device_asoc_platform = {
381 .name = "pxa-pcm-audio",
382 .id = -1,
383};
384
8f58de7c 385static u64 pxaficp_dmamask = ~(u32)0;
386
121f3f9b
RH		 387static struct resource pxa_ir_resources[] = {
388 [0] = {
389 .start = IRQ_STUART,
390 .end = IRQ_STUART,
391 .flags = IORESOURCE_IRQ,
392 },
393 [1] = {
394 .start = IRQ_ICP,
395 .end = IRQ_ICP,
396 .flags = IORESOURCE_IRQ,
397 },
398};
399
8f58de7c 400struct platform_device pxa_device_ficp = {
401 .name = "pxa2xx-ir",
402 .id = -1,
121f3f9b
RH		 403 .num_resources = ARRAY_SIZE(pxa_ir_resources),
404 .resource = pxa_ir_resources,
8f58de7c 405 .dev = {
406 .dma_mask = &pxaficp_dmamask,
407 .coherent_dma_mask = 0xffffffff,
408 },
409};
410
411void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
412{
413 pxa_register_device(&pxa_device_ficp, info);
414}
415
72493146
RJ		 416static struct resource pxa_rtc_resources[] = {
417 [0] = {
418 .start = 0x40900000,
419 .end = 0x40900000 + 0x3b,
420 .flags = IORESOURCE_MEM,
421 },
422 [1] = {
423 .start = IRQ_RTC1Hz,
424 .end = IRQ_RTC1Hz,
3888c090 425 .name = "rtc 1Hz",
72493146
RJ		 426 .flags = IORESOURCE_IRQ,
427 },
428 [2] = {
429 .start = IRQ_RTCAlrm,
430 .end = IRQ_RTCAlrm,
3888c090 431 .name = "rtc alarm",
72493146
RJ		 432 .flags = IORESOURCE_IRQ,
433 },
434};
435
72493146
RJ		 436struct platform_device pxa_device_rtc = {
437 .name = "pxa-rtc",
438 .id = -1,
439 .num_resources = ARRAY_SIZE(pxa_rtc_resources),
440 .resource = pxa_rtc_resources,
441};
442
3888c090
HZ		 443struct platform_device sa1100_device_rtc = {
444 .name = "sa1100-rtc",
445 .id = -1,
2c4fabec
RH		 446 .num_resources = ARRAY_SIZE(pxa_rtc_resources),
447 .resource = pxa_rtc_resources,
3888c090
HZ		 448};
449
9f19d638
MB		 450static struct resource pxa_ac97_resources[] = {
451 [0] = {
452 .start = 0x40500000,
453 .end = 0x40500000 + 0xfff,
454 .flags = IORESOURCE_MEM,
455 },
456 [1] = {
457 .start = IRQ_AC97,
458 .end = IRQ_AC97,
459 .flags = IORESOURCE_IRQ,
460 },
461};
462
463static u64 pxa_ac97_dmamask = 0xffffffffUL;
464
465struct platform_device pxa_device_ac97 = {
466 .name = "pxa2xx-ac97",
467 .id = -1,
468 .dev = {
469 .dma_mask = &pxa_ac97_dmamask,
470 .coherent_dma_mask = 0xffffffff,
471 },
472 .num_resources = ARRAY_SIZE(pxa_ac97_resources),
473 .resource = pxa_ac97_resources,
474};
475
476void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
477{
478 pxa_register_device(&pxa_device_ac97, ops);
479}
480
8f58de7c 481#ifdef CONFIG_PXA25x
482
75540c1a 483static struct resource pxa25x_resource_pwm0[] = {
484 [0] = {
485 .start = 0x40b00000,
486 .end = 0x40b0000f,
487 .flags = IORESOURCE_MEM,
488 },
489};
490
491struct platform_device pxa25x_device_pwm0 = {
492 .name = "pxa25x-pwm",
493 .id = 0,
494 .resource = pxa25x_resource_pwm0,
495 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
496};
497
498static struct resource pxa25x_resource_pwm1[] = {
499 [0] = {
500 .start = 0x40c00000,
501 .end = 0x40c0000f,
502 .flags = IORESOURCE_MEM,
503 },
504};
505
506struct platform_device pxa25x_device_pwm1 = {
507 .name = "pxa25x-pwm",
508 .id = 1,
509 .resource = pxa25x_resource_pwm1,
510 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
511};
512
8f58de7c 513static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
514
515static struct resource pxa25x_resource_ssp[] = {
516 [0] = {
517 .start = 0x41000000,
518 .end = 0x4100001f,
519 .flags = IORESOURCE_MEM,
520 },
521 [1] = {
522 .start = IRQ_SSP,
523 .end = IRQ_SSP,
524 .flags = IORESOURCE_IRQ,
525 },
526 [2] = {
527 /* DRCMR for RX */
528 .start = 13,
529 .end = 13,
530 .flags = IORESOURCE_DMA,
531 },
532 [3] = {
533 /* DRCMR for TX */
534 .start = 14,
535 .end = 14,
536 .flags = IORESOURCE_DMA,
537 },
538};
539
540struct platform_device pxa25x_device_ssp = {
541 .name = "pxa25x-ssp",
542 .id = 0,
543 .dev = {
544 .dma_mask = &pxa25x_ssp_dma_mask,
545 .coherent_dma_mask = DMA_BIT_MASK(32),
546 },
547 .resource = pxa25x_resource_ssp,
548 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
549};
550
551static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
552
553static struct resource pxa25x_resource_nssp[] = {
554 [0] = {
555 .start = 0x41400000,
556 .end = 0x4140002f,
557 .flags = IORESOURCE_MEM,
558 },
559 [1] = {
560 .start = IRQ_NSSP,
561 .end = IRQ_NSSP,
562 .flags = IORESOURCE_IRQ,
563 },
564 [2] = {
565 /* DRCMR for RX */
566 .start = 15,
567 .end = 15,
568 .flags = IORESOURCE_DMA,
569 },
570 [3] = {
571 /* DRCMR for TX */
572 .start = 16,
573 .end = 16,
574 .flags = IORESOURCE_DMA,
575 },
576};
577
578struct platform_device pxa25x_device_nssp = {
579 .name = "pxa25x-nssp",
580 .id = 1,
581 .dev = {
582 .dma_mask = &pxa25x_nssp_dma_mask,
583 .coherent_dma_mask = DMA_BIT_MASK(32),
584 },
585 .resource = pxa25x_resource_nssp,
586 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
587};
588
589static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
590
591static struct resource pxa25x_resource_assp[] = {
592 [0] = {
593 .start = 0x41500000,
594 .end = 0x4150002f,
595 .flags = IORESOURCE_MEM,
596 },
597 [1] = {
598 .start = IRQ_ASSP,
599 .end = IRQ_ASSP,
600 .flags = IORESOURCE_IRQ,
601 },
602 [2] = {
603 /* DRCMR for RX */
604 .start = 23,
605 .end = 23,
606 .flags = IORESOURCE_DMA,
607 },
608 [3] = {
609 /* DRCMR for TX */
610 .start = 24,
611 .end = 24,
612 .flags = IORESOURCE_DMA,
613 },
614};
615
616struct platform_device pxa25x_device_assp = {
617 /* ASSP is basically equivalent to NSSP */
618 .name = "pxa25x-nssp",
619 .id = 2,
620 .dev = {
621 .dma_mask = &pxa25x_assp_dma_mask,
622 .coherent_dma_mask = DMA_BIT_MASK(32),
623 },
624 .resource = pxa25x_resource_assp,
625 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
626};
627#endif /* CONFIG_PXA25x */
628
629#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
a4553358 630static struct resource pxa27x_resource_camera[] = {
37320980 631 [0] = {
a4553358
HZ		 632 .start = 0x50000000,
633 .end = 0x50000fff,
37320980 634 .flags = IORESOURCE_MEM,
635 },
636 [1] = {
a4553358
HZ		 637 .start = IRQ_CAMERA,
638 .end = IRQ_CAMERA,
37320980 639 .flags = IORESOURCE_IRQ,
640 },
641};
642
a4553358
HZ		 643static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
644
645static struct platform_device pxa27x_device_camera = {
646 .name = "pxa27x-camera",
647 .id = 0, /* This is used to put cameras on this interface */
648 .dev = {
649 .dma_mask = &pxa27x_dma_mask_camera,
650 .coherent_dma_mask = 0xffffffff,
651 },
652 .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
653 .resource = pxa27x_resource_camera,
37320980 654};
655
a4553358 656void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
37320980 657{
a4553358 658 pxa_register_device(&pxa27x_device_camera, info);
37320980 659}
660
ec68e45b 661static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
662
663static struct resource pxa27x_resource_ohci[] = {
664 [0] = {
665 .start = 0x4C000000,
666 .end = 0x4C00ff6f,
667 .flags = IORESOURCE_MEM,
668 },
669 [1] = {
670 .start = IRQ_USBH1,
671 .end = IRQ_USBH1,
672 .flags = IORESOURCE_IRQ,
673 },
674};
675
676struct platform_device pxa27x_device_ohci = {
677 .name = "pxa27x-ohci",
678 .id = -1,
679 .dev = {
680 .dma_mask = &pxa27x_ohci_dma_mask,
681 .coherent_dma_mask = DMA_BIT_MASK(32),
682 },
683 .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
684 .resource = pxa27x_resource_ohci,
685};
686
687void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
688{
689 pxa_register_device(&pxa27x_device_ohci, info);
690}
a4553358
HZ		 691#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
692
49ea7fc0 693#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
a4553358
HZ		 694static struct resource pxa27x_resource_keypad[] = {
695 [0] = {
696 .start = 0x41500000,
697 .end = 0x4150004c,
698 .flags = IORESOURCE_MEM,
699 },
700 [1] = {
701 .start = IRQ_KEYPAD,
702 .end = IRQ_KEYPAD,
703 .flags = IORESOURCE_IRQ,
704 },
705};
706
707struct platform_device pxa27x_device_keypad = {
708 .name = "pxa27x-keypad",
709 .id = -1,
710 .resource = pxa27x_resource_keypad,
711 .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
712};
713
714void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
715{
716 pxa_register_device(&pxa27x_device_keypad, info);
717}
ec68e45b 718
8f58de7c 719static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
720
721static struct resource pxa27x_resource_ssp1[] = {
722 [0] = {
723 .start = 0x41000000,
724 .end = 0x4100003f,
725 .flags = IORESOURCE_MEM,
726 },
727 [1] = {
728 .start = IRQ_SSP,
729 .end = IRQ_SSP,
730 .flags = IORESOURCE_IRQ,
731 },
732 [2] = {
733 /* DRCMR for RX */
734 .start = 13,
735 .end = 13,
736 .flags = IORESOURCE_DMA,
737 },
738 [3] = {
739 /* DRCMR for TX */
740 .start = 14,
741 .end = 14,
742 .flags = IORESOURCE_DMA,
743 },
744};
745
746struct platform_device pxa27x_device_ssp1 = {
747 .name = "pxa27x-ssp",
748 .id = 0,
749 .dev = {
750 .dma_mask = &pxa27x_ssp1_dma_mask,
751 .coherent_dma_mask = DMA_BIT_MASK(32),
752 },
753 .resource = pxa27x_resource_ssp1,
754 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
755};
756
757static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
758
759static struct resource pxa27x_resource_ssp2[] = {
760 [0] = {
761 .start = 0x41700000,
762 .end = 0x4170003f,
763 .flags = IORESOURCE_MEM,
764 },
765 [1] = {
766 .start = IRQ_SSP2,
767 .end = IRQ_SSP2,
768 .flags = IORESOURCE_IRQ,
769 },
770 [2] = {
771 /* DRCMR for RX */
772 .start = 15,
773 .end = 15,
774 .flags = IORESOURCE_DMA,
775 },
776 [3] = {
777 /* DRCMR for TX */
778 .start = 16,
779 .end = 16,
780 .flags = IORESOURCE_DMA,
781 },
782};
783
784struct platform_device pxa27x_device_ssp2 = {
785 .name = "pxa27x-ssp",
786 .id = 1,
787 .dev = {
788 .dma_mask = &pxa27x_ssp2_dma_mask,
789 .coherent_dma_mask = DMA_BIT_MASK(32),
790 },
791 .resource = pxa27x_resource_ssp2,
792 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
793};
794
795static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
796
797static struct resource pxa27x_resource_ssp3[] = {
798 [0] = {
799 .start = 0x41900000,
800 .end = 0x4190003f,
801 .flags = IORESOURCE_MEM,
802 },
803 [1] = {
804 .start = IRQ_SSP3,
805 .end = IRQ_SSP3,
806 .flags = IORESOURCE_IRQ,
807 },
808 [2] = {
809 /* DRCMR for RX */
810 .start = 66,
811 .end = 66,
812 .flags = IORESOURCE_DMA,
813 },
814 [3] = {
815 /* DRCMR for TX */
816 .start = 67,
817 .end = 67,
818 .flags = IORESOURCE_DMA,
819 },
820};
821
822struct platform_device pxa27x_device_ssp3 = {
823 .name = "pxa27x-ssp",
824 .id = 2,
825 .dev = {
826 .dma_mask = &pxa27x_ssp3_dma_mask,
827 .coherent_dma_mask = DMA_BIT_MASK(32),
828 },
829 .resource = pxa27x_resource_ssp3,
830 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
831};
3f3acefb 832
75540c1a 833static struct resource pxa27x_resource_pwm0[] = {
834 [0] = {
835 .start = 0x40b00000,
836 .end = 0x40b0001f,
837 .flags = IORESOURCE_MEM,
838 },
839};
840
841struct platform_device pxa27x_device_pwm0 = {
842 .name = "pxa27x-pwm",
843 .id = 0,
844 .resource = pxa27x_resource_pwm0,
845 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
846};
847
848static struct resource pxa27x_resource_pwm1[] = {
849 [0] = {
850 .start = 0x40c00000,
851 .end = 0x40c0001f,
852 .flags = IORESOURCE_MEM,
853 },
854};
855
856struct platform_device pxa27x_device_pwm1 = {
857 .name = "pxa27x-pwm",
858 .id = 1,
859 .resource = pxa27x_resource_pwm1,
860 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
861};
49ea7fc0 862#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
8f58de7c 863
864#ifdef CONFIG_PXA3xx
8d33b055
BW		 865static struct resource pxa3xx_resources_mci2[] = {
866 [0] = {
867 .start = 0x42000000,
868 .end = 0x42000fff,
869 .flags = IORESOURCE_MEM,
870 },
871 [1] = {
872 .start = IRQ_MMC2,
873 .end = IRQ_MMC2,
874 .flags = IORESOURCE_IRQ,
875 },
876 [2] = {
877 .start = 93,
878 .end = 93,
879 .flags = IORESOURCE_DMA,
880 },
881 [3] = {
882 .start = 94,
883 .end = 94,
884 .flags = IORESOURCE_DMA,
885 },
886};
887
888struct platform_device pxa3xx_device_mci2 = {
889 .name = "pxa2xx-mci",
890 .id = 1,
891 .dev = {
892 .dma_mask = &pxamci_dmamask,
893 .coherent_dma_mask = 0xffffffff,
894 },
895 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
896 .resource = pxa3xx_resources_mci2,
897};
898
899void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
900{
901 pxa_register_device(&pxa3xx_device_mci2, info);
902}
903
5a1f21b1
BW		 904static struct resource pxa3xx_resources_mci3[] = {
905 [0] = {
906 .start = 0x42500000,
907 .end = 0x42500fff,
908 .flags = IORESOURCE_MEM,
909 },
910 [1] = {
911 .start = IRQ_MMC3,
912 .end = IRQ_MMC3,
913 .flags = IORESOURCE_IRQ,
914 },
915 [2] = {
916 .start = 100,
917 .end = 100,
918 .flags = IORESOURCE_DMA,
919 },
920 [3] = {
921 .start = 101,
922 .end = 101,
923 .flags = IORESOURCE_DMA,
924 },
925};
926
927struct platform_device pxa3xx_device_mci3 = {
928 .name = "pxa2xx-mci",
929 .id = 2,
930 .dev = {
931 .dma_mask = &pxamci_dmamask,
932 .coherent_dma_mask = 0xffffffff,
933 },
934 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
935 .resource = pxa3xx_resources_mci3,
936};
937
938void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
939{
940 pxa_register_device(&pxa3xx_device_mci3, info);
941}
942
a4553358
HZ		 943static struct resource pxa3xx_resources_gcu[] = {
944 {
945 .start = 0x54000000,
946 .end = 0x54000fff,
947 .flags = IORESOURCE_MEM,
948 },
949 {
950 .start = IRQ_GCU,
951 .end = IRQ_GCU,
952 .flags = IORESOURCE_IRQ,
953 },
954};
955
956static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
957
958struct platform_device pxa3xx_device_gcu = {
959 .name = "pxa3xx-gcu",
960 .id = -1,
961 .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
962 .resource = pxa3xx_resources_gcu,
963 .dev = {
964 .dma_mask = &pxa3xx_gcu_dmamask,
965 .coherent_dma_mask = 0xffffffff,
966 },
967};
968
969#endif /* CONFIG_PXA3xx */
970
49ea7fc0 971#if defined(CONFIG_PXA3xx)
a4553358
HZ		 972static struct resource pxa3xx_resources_i2c_power[] = {
973 {
974 .start = 0x40f500c0,
975 .end = 0x40f500d3,
976 .flags = IORESOURCE_MEM,
977 }, {
978 .start = IRQ_PWRI2C,
979 .end = IRQ_PWRI2C,
980 .flags = IORESOURCE_IRQ,
981 },
982};
983
984struct platform_device pxa3xx_device_i2c_power = {
985 .name = "pxa3xx-pwri2c",
986 .id = 1,
987 .resource = pxa3xx_resources_i2c_power,
988 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
989};
990
9ae819a8
EM		 991static struct resource pxa3xx_resources_nand[] = {
992 [0] = {
993 .start = 0x43100000,
994 .end = 0x43100053,
995 .flags = IORESOURCE_MEM,
996 },
997 [1] = {
998 .start = IRQ_NAND,
999 .end = IRQ_NAND,
1000 .flags = IORESOURCE_IRQ,
1001 },
1002 [2] = {
1003 /* DRCMR for Data DMA */
1004 .start = 97,
1005 .end = 97,
1006 .flags = IORESOURCE_DMA,
1007 },
1008 [3] = {
1009 /* DRCMR for Command DMA */
1010 .start = 99,
1011 .end = 99,
1012 .flags = IORESOURCE_DMA,
1013 },
1014};
1015
1016static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
1017
1018struct platform_device pxa3xx_device_nand = {
1019 .name = "pxa3xx-nand",
1020 .id = -1,
1021 .dev = {
1022 .dma_mask = &pxa3xx_nand_dma_mask,
1023 .coherent_dma_mask = DMA_BIT_MASK(32),
1024 },
1025 .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
1026 .resource = pxa3xx_resources_nand,
1027};
1028
1029void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
1030{
1031 pxa_register_device(&pxa3xx_device_nand, info);
1032}
1ff2c33e 1033
a4553358
HZ		 1034static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
1035
1036static struct resource pxa3xx_resource_ssp4[] = {
1037 [0] = {
1038 .start = 0x41a00000,
1039 .end = 0x41a0003f,
1ff2c33e
DM		 1040 .flags = IORESOURCE_MEM,
1041 },
a4553358
HZ		 1042 [1] = {
1043 .start = IRQ_SSP4,
1044 .end = IRQ_SSP4,
1ff2c33e
DM		 1045 .flags = IORESOURCE_IRQ,
1046 },
a4553358
HZ		 1047 [2] = {
1048 /* DRCMR for RX */
1049 .start = 2,
1050 .end = 2,
1051 .flags = IORESOURCE_DMA,
1052 },
1053 [3] = {
1054 /* DRCMR for TX */
1055 .start = 3,
1056 .end = 3,
1057 .flags = IORESOURCE_DMA,
1058 },
1ff2c33e
DM		 1059};
1060
0da0e227
DM		 1061/*
1062 * PXA3xx SSP is basically equivalent to PXA27x.
1063 * However, we need to register the device by the correct name in order to
1064 * make the driver set the correct internal type, hence we provide specific
1065 * platform_devices for each of them.
1066 */
1067struct platform_device pxa3xx_device_ssp1 = {
1068 .name = "pxa3xx-ssp",
1069 .id = 0,
1070 .dev = {
1071 .dma_mask = &pxa27x_ssp1_dma_mask,
1072 .coherent_dma_mask = DMA_BIT_MASK(32),
1073 },
1074 .resource = pxa27x_resource_ssp1,
1075 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
1076};
1077
1078struct platform_device pxa3xx_device_ssp2 = {
1079 .name = "pxa3xx-ssp",
1080 .id = 1,
1081 .dev = {
1082 .dma_mask = &pxa27x_ssp2_dma_mask,
1083 .coherent_dma_mask = DMA_BIT_MASK(32),
1084 },
1085 .resource = pxa27x_resource_ssp2,
1086 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
1087};
1088
1089struct platform_device pxa3xx_device_ssp3 = {
1090 .name = "pxa3xx-ssp",
1091 .id = 2,
1092 .dev = {
1093 .dma_mask = &pxa27x_ssp3_dma_mask,
1094 .coherent_dma_mask = DMA_BIT_MASK(32),
1095 },
1096 .resource = pxa27x_resource_ssp3,
1097 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
1098};
1099
a4553358 1100struct platform_device pxa3xx_device_ssp4 = {
0da0e227 1101 .name = "pxa3xx-ssp",
a4553358 1102 .id = 3,
1ff2c33e 1103 .dev = {
a4553358
HZ		 1104 .dma_mask = &pxa3xx_ssp4_dma_mask,
1105 .coherent_dma_mask = DMA_BIT_MASK(32),
1ff2c33e 1106 },
a4553358
HZ		 1107 .resource = pxa3xx_resource_ssp4,
1108 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
1ff2c33e 1109};
49ea7fc0 1110#endif /* CONFIG_PXA3xx */
e172274c 1111
157d2644
HZ		 1112struct resource pxa_resource_gpio[] = {
1113 {
1114 .start = 0x40e00000,
1115 .end = 0x40e0ffff,
1116 .flags = IORESOURCE_MEM,
1117 }, {
1118 .start = IRQ_GPIO0,
1119 .end = IRQ_GPIO0,
1120 .name = "gpio0",
1121 .flags = IORESOURCE_IRQ,
1122 }, {
1123 .start = IRQ_GPIO1,
1124 .end = IRQ_GPIO1,
1125 .name = "gpio1",
1126 .flags = IORESOURCE_IRQ,
1127 }, {
1128 .start = IRQ_GPIO_2_x,
1129 .end = IRQ_GPIO_2_x,
1130 .name = "gpio_mux",
1131 .flags = IORESOURCE_IRQ,
1132 },
1133};
1134
2cab0292
HZ		 1135struct platform_device pxa25x_device_gpio = {
1136#ifdef CONFIG_CPU_PXA26x
1137 .name = "pxa26x-gpio",
1138#else
1139 .name = "pxa25x-gpio",
1140#endif
1141 .id = -1,
1142 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1143 .resource = pxa_resource_gpio,
1144};
1145
1146struct platform_device pxa27x_device_gpio = {
1147 .name = "pxa27x-gpio",
1148 .id = -1,
1149 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1150 .resource = pxa_resource_gpio,
1151};
1152
1153struct platform_device pxa3xx_device_gpio = {
1154 .name = "pxa3xx-gpio",
1155 .id = -1,
1156 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1157 .resource = pxa_resource_gpio,
1158};
1159
1160struct platform_device pxa93x_device_gpio = {
1161 .name = "pxa93x-gpio",
157d2644
HZ		 1162 .id = -1,
1163 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1164 .resource = pxa_resource_gpio,
1165};
1166
e172274c
GL		 1167/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
1168 * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
1169void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
1170{
1171 struct platform_device *pd;
1172
1173 pd = platform_device_alloc("pxa2xx-spi", id);
1174 if (pd == NULL) {
1175 printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
1176 id);
1177 return;
1178 }
1179
1180 pd->dev.platform_data = info;
1181 platform_device_add(pd);
1182}
4be0856f
RJ		 1183
1184static struct mmp_dma_platdata pxa_dma_pdata = {
1185 .dma_channels = 0,
1186};
1187
1188static struct resource pxa_dma_resource[] = {
1189 [0] = {
1190 .start = 0x40000000,
1191 .end = 0x4000ffff,
1192 .flags = IORESOURCE_MEM,
1193 },
1194 [1] = {
1195 .start = IRQ_DMA,
1196 .end = IRQ_DMA,
1197 .flags = IORESOURCE_IRQ,
1198 },
1199};
1200
1201static u64 pxadma_dmamask = 0xffffffffUL;
1202
1203static struct platform_device pxa2xx_pxa_dma = {
1204 .name = "pxa-dma",
1205 .id = 0,
1206 .dev = {
1207 .dma_mask = &pxadma_dmamask,
1208 .coherent_dma_mask = 0xffffffff,
1209 },
1210 .num_resources = ARRAY_SIZE(pxa_dma_resource),
1211 .resource = pxa_dma_resource,
1212};
1213
1214void __init pxa2xx_set_dmac_info(int nb_channels)
1215{
1216 pxa_dma_pdata.dma_channels = nb_channels;
1217 pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
1218}
Linux kernel - Deliverables
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