[deliverable/linux.git] / arch / arm / mach-pxa / devices.c

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>

#include <asm/arch/gpio.h>
#include <asm/arch/udc.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/i2c.h>

#include "devices.h"

void __init pxa_register_device(struct platform_device *dev, void *data)
{
	int ret;

	dev->dev.platform_data = data;

	ret = platform_device_register(dev);
	if (ret)
		dev_err(&dev->dev, "unable to register device: %d\n", ret);
}

static struct resource pxamci_resources[] = {
	[0] = {
		.start	= 0x41100000,
		.end	= 0x41100fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_MMC,
		.end	= IRQ_MMC,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		.start	= 21,
		.end	= 21,
		.flags	= IORESOURCE_DMA,
	},
	[3] = {
		.start	= 22,
		.end	= 22,
		.flags	= IORESOURCE_DMA,
	},
};

static u64 pxamci_dmamask = 0xffffffffUL;

struct platform_device pxa_device_mci = {
	.name		= "pxa2xx-mci",
	.id		= 0,
	.dev		= {
		.dma_mask = &pxamci_dmamask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(pxamci_resources),
	.resource	= pxamci_resources,
};

void __init pxa_set_mci_info(struct pxamci_platform_data *info)
{
	pxa_register_device(&pxa_device_mci, info);
}


static struct pxa2xx_udc_mach_info pxa_udc_info;

void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
{
	memcpy(&pxa_udc_info, info, sizeof *info);
}

static struct resource pxa2xx_udc_resources[] = {
	[0] = {
		.start	= 0x40600000,
		.end	= 0x4060ffff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_USB,
		.end	= IRQ_USB,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 udc_dma_mask = ~(u32)0;

struct platform_device pxa_device_udc = {
	.name		= "pxa2xx-udc",
	.id		= -1,
	.resource	= pxa2xx_udc_resources,
	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
	.dev		=  {
		.platform_data	= &pxa_udc_info,
		.dma_mask	= &udc_dma_mask,
	}
};

static struct resource pxafb_resources[] = {
	[0] = {
		.start	= 0x44000000,
		.end	= 0x4400ffff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_LCD,
		.end	= IRQ_LCD,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 fb_dma_mask = ~(u64)0;

struct platform_device pxa_device_fb = {
	.name		= "pxa2xx-fb",
	.id		= -1,
	.dev		= {
		.dma_mask	= &fb_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(pxafb_resources),
	.resource	= pxafb_resources,
};

void __init set_pxa_fb_info(struct pxafb_mach_info *info)
{
	pxa_register_device(&pxa_device_fb, info);
}

void __init set_pxa_fb_parent(struct device *parent_dev)
{
	pxa_device_fb.dev.parent = parent_dev;
}

static struct resource pxa_resource_ffuart[] = {
	{
		.start	= __PREG(FFUART),
		.end	= __PREG(FFUART) + 35,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_FFUART,
		.end	= IRQ_FFUART,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device pxa_device_ffuart= {
	.name		= "pxa2xx-uart",
	.id		= 0,
	.resource	= pxa_resource_ffuart,
	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
};

static struct resource pxa_resource_btuart[] = {
	{
		.start	= __PREG(BTUART),
		.end	= __PREG(BTUART) + 35,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_BTUART,
		.end	= IRQ_BTUART,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device pxa_device_btuart = {
	.name		= "pxa2xx-uart",
	.id		= 1,
	.resource	= pxa_resource_btuart,
	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
};

static struct resource pxa_resource_stuart[] = {
	{
		.start	= __PREG(STUART),
		.end	= __PREG(STUART) + 35,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_STUART,
		.end	= IRQ_STUART,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device pxa_device_stuart = {
	.name		= "pxa2xx-uart",
	.id		= 2,
	.resource	= pxa_resource_stuart,
	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
};

static struct resource pxa_resource_hwuart[] = {
	{
		.start	= __PREG(HWUART),
		.end	= __PREG(HWUART) + 47,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_HWUART,
		.end	= IRQ_HWUART,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device pxa_device_hwuart = {
	.name		= "pxa2xx-uart",
	.id		= 3,
	.resource	= pxa_resource_hwuart,
	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
};

static struct resource pxai2c_resources[] = {
	{
		.start	= 0x40301680,
		.end	= 0x403016a3,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_I2C,
		.end	= IRQ_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device pxa_device_i2c = {
	.name		= "pxa2xx-i2c",
	.id		= 0,
	.resource	= pxai2c_resources,
	.num_resources	= ARRAY_SIZE(pxai2c_resources),
};

void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa_device_i2c, info);
}

static struct resource pxai2s_resources[] = {
	{
		.start	= 0x40400000,
		.end	= 0x40400083,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_I2S,
		.end	= IRQ_I2S,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device pxa_device_i2s = {
	.name		= "pxa2xx-i2s",
	.id		= -1,
	.resource	= pxai2s_resources,
	.num_resources	= ARRAY_SIZE(pxai2s_resources),
};

static u64 pxaficp_dmamask = ~(u32)0;

struct platform_device pxa_device_ficp = {
	.name		= "pxa2xx-ir",
	.id		= -1,
	.dev		= {
		.dma_mask = &pxaficp_dmamask,
		.coherent_dma_mask = 0xffffffff,
	},
};

void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
{
	pxa_register_device(&pxa_device_ficp, info);
}

struct platform_device pxa_device_rtc = {
	.name		= "sa1100-rtc",
	.id		= -1,
};

#ifdef CONFIG_PXA25x

static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);

static struct resource pxa25x_resource_ssp[] = {
	[0] = {
		.start	= 0x41000000,
		.end	= 0x4100001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_SSP,
		.end	= IRQ_SSP,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* DRCMR for RX */
		.start	= 13,
		.end	= 13,
		.flags	= IORESOURCE_DMA,
	},
	[3] = {
		/* DRCMR for TX */
		.start	= 14,
		.end	= 14,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device pxa25x_device_ssp = {
	.name		= "pxa25x-ssp",
	.id		= 0,
	.dev		= {
		.dma_mask = &pxa25x_ssp_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.resource	= pxa25x_resource_ssp,
	.num_resources	= ARRAY_SIZE(pxa25x_resource_ssp),
};

static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);

static struct resource pxa25x_resource_nssp[] = {
	[0] = {
		.start	= 0x41400000,
		.end	= 0x4140002f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_NSSP,
		.end	= IRQ_NSSP,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* DRCMR for RX */
		.start	= 15,
		.end	= 15,
		.flags	= IORESOURCE_DMA,
	},
	[3] = {
		/* DRCMR for TX */
		.start	= 16,
		.end	= 16,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device pxa25x_device_nssp = {
	.name		= "pxa25x-nssp",
	.id		= 1,
	.dev		= {
		.dma_mask = &pxa25x_nssp_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.resource	= pxa25x_resource_nssp,
	.num_resources	= ARRAY_SIZE(pxa25x_resource_nssp),
};

static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);

static struct resource pxa25x_resource_assp[] = {
	[0] = {
		.start	= 0x41500000,
		.end	= 0x4150002f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_ASSP,
		.end	= IRQ_ASSP,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* DRCMR for RX */
		.start	= 23,
		.end	= 23,
		.flags	= IORESOURCE_DMA,
	},
	[3] = {
		/* DRCMR for TX */
		.start	= 24,
		.end	= 24,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device pxa25x_device_assp = {
	/* ASSP is basically equivalent to NSSP */
	.name		= "pxa25x-nssp",
	.id		= 2,
	.dev		= {
		.dma_mask = &pxa25x_assp_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.resource	= pxa25x_resource_assp,
	.num_resources	= ARRAY_SIZE(pxa25x_resource_assp),
};
#endif /* CONFIG_PXA25x */

#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)

static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);

static struct resource pxa27x_resource_ssp1[] = {
	[0] = {
		.start	= 0x41000000,
		.end	= 0x4100003f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_SSP,
		.end	= IRQ_SSP,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* DRCMR for RX */
		.start	= 13,
		.end	= 13,
		.flags	= IORESOURCE_DMA,
	},
	[3] = {
		/* DRCMR for TX */
		.start	= 14,
		.end	= 14,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device pxa27x_device_ssp1 = {
	.name		= "pxa27x-ssp",
	.id		= 0,
	.dev		= {
		.dma_mask = &pxa27x_ssp1_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.resource	= pxa27x_resource_ssp1,
	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp1),
};

static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);

static struct resource pxa27x_resource_ssp2[] = {
	[0] = {
		.start	= 0x41700000,
		.end	= 0x4170003f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_SSP2,
		.end	= IRQ_SSP2,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* DRCMR for RX */
		.start	= 15,
		.end	= 15,
		.flags	= IORESOURCE_DMA,
	},
	[3] = {
		/* DRCMR for TX */
		.start	= 16,
		.end	= 16,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device pxa27x_device_ssp2 = {
	.name		= "pxa27x-ssp",
	.id		= 1,
	.dev		= {
		.dma_mask = &pxa27x_ssp2_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.resource	= pxa27x_resource_ssp2,
	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp2),
};

static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);

static struct resource pxa27x_resource_ssp3[] = {
	[0] = {
		.start	= 0x41900000,
		.end	= 0x4190003f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_SSP3,
		.end	= IRQ_SSP3,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* DRCMR for RX */
		.start	= 66,
		.end	= 66,
		.flags	= IORESOURCE_DMA,
	},
	[3] = {
		/* DRCMR for TX */
		.start	= 67,
		.end	= 67,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device pxa27x_device_ssp3 = {
	.name		= "pxa27x-ssp",
	.id		= 2,
	.dev		= {
		.dma_mask = &pxa27x_ssp3_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.resource	= pxa27x_resource_ssp3,
	.num_resources	= ARRAY_SIZE(pxa27x_resource_ssp3),
};
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */

#ifdef CONFIG_PXA3xx
static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);

static struct resource pxa3xx_resource_ssp4[] = {
	[0] = {
		.start	= 0x41a00000,
		.end	= 0x41a0003f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_SSP4,
		.end	= IRQ_SSP4,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* DRCMR for RX */
		.start	= 2,
		.end	= 2,
		.flags	= IORESOURCE_DMA,
	},
	[3] = {
		/* DRCMR for TX */
		.start	= 3,
		.end	= 3,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device pxa3xx_device_ssp4 = {
	/* PXA3xx SSP is basically equivalent to PXA27x */
	.name		= "pxa27x-ssp",
	.id		= 3,
	.dev		= {
		.dma_mask = &pxa3xx_ssp4_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.resource	= pxa3xx_resource_ssp4,
	.num_resources	= ARRAY_SIZE(pxa3xx_resource_ssp4),
};
#endif /* CONFIG_PXA3xx */
Commit	Line	Data
8f58de7c	1	#include <linux/module.h>
	2	#include <linux/kernel.h>
	3	#include <linux/init.h>
	4	#include <linux/platform_device.h>
	5	#include <linux/dma-mapping.h>
	6
	7	#include <asm/arch/gpio.h>
	8	#include <asm/arch/udc.h>
	9	#include <asm/arch/pxafb.h>
	10	#include <asm/arch/mmc.h>
	11	#include <asm/arch/irda.h>
	12	#include <asm/arch/i2c.h>
	13
	14	#include "devices.h"
	15
	16	void __init pxa_register_device(struct platform_device dev, void data)
	17	{
	18	int ret;
	19
	20	dev->dev.platform_data = data;
	21
	22	ret = platform_device_register(dev);
	23	if (ret)
	24	dev_err(&dev->dev, "unable to register device: %d\n", ret);
	25	}
	26
	27	static struct resource pxamci_resources[] = {
	28	[0] = {
	29	.start = 0x41100000,
	30	.end = 0x41100fff,
	31	.flags = IORESOURCE_MEM,
	32	},
	33	[1] = {
	34	.start = IRQ_MMC,
	35	.end = IRQ_MMC,
	36	.flags = IORESOURCE_IRQ,
	37	},
	38	[2] = {
	39	.start = 21,
	40	.end = 21,
	41	.flags = IORESOURCE_DMA,
	42	},
	43	[3] = {
	44	.start = 22,
	45	.end = 22,
	46	.flags = IORESOURCE_DMA,
	47	},
	48	};
	49
	50	static u64 pxamci_dmamask = 0xffffffffUL;
	51
	52	struct platform_device pxa_device_mci = {
	53	.name = "pxa2xx-mci",
fafc9d3f	54	.id = 0,
8f58de7c	55	.dev = {
	56	.dma_mask = &pxamci_dmamask,
	57	.coherent_dma_mask = 0xffffffff,
	58	},
	59	.num_resources = ARRAY_SIZE(pxamci_resources),
	60	.resource = pxamci_resources,
	61	};
	62
	63	void __init pxa_set_mci_info(struct pxamci_platform_data *info)
	64	{
	65	pxa_register_device(&pxa_device_mci, info);
	66	}
	67
	68
	69	static struct pxa2xx_udc_mach_info pxa_udc_info;
	70
	71	void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
	72	{
	73	memcpy(&pxa_udc_info, info, sizeof *info);
	74	}
	75
	76	static struct resource pxa2xx_udc_resources[] = {
	77	[0] = {
	78	.start = 0x40600000,
	79	.end = 0x4060ffff,
	80	.flags = IORESOURCE_MEM,
	81	},
	82	[1] = {
	83	.start = IRQ_USB,
	84	.end = IRQ_USB,
	85	.flags = IORESOURCE_IRQ,
	86	},
	87	};
	88
	89	static u64 udc_dma_mask = ~(u32)0;
	90
	91	struct platform_device pxa_device_udc = {
	92	.name = "pxa2xx-udc",
	93	.id = -1,
	94	.resource = pxa2xx_udc_resources,
	95	.num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
	96	.dev = {
	97	.platform_data = &pxa_udc_info,
	98	.dma_mask = &udc_dma_mask,
	99	}
	100	};
	101
	102	static struct resource pxafb_resources[] = {
	103	[0] = {
	104	.start = 0x44000000,
	105	.end = 0x4400ffff,
	106	.flags = IORESOURCE_MEM,
	107	},
	108	[1] = {
	109	.start = IRQ_LCD,
	110	.end = IRQ_LCD,
	111	.flags = IORESOURCE_IRQ,
	112	},
	113	};
	114
	115	static u64 fb_dma_mask = ~(u64)0;
	116
	117	struct platform_device pxa_device_fb = {
	118	.name = "pxa2xx-fb",
119	.id = -1,
120	.dev = {
121	.dma_mask = &fb_dma_mask,
122	.coherent_dma_mask = 0xffffffff,
123	},
124	.num_resources = ARRAY_SIZE(pxafb_resources),
125	.resource = pxafb_resources,
126	};
127
128	void __init set_pxa_fb_info(struct pxafb_mach_info *info)
129	{
130	pxa_register_device(&pxa_device_fb, info);
131	}
132
133	void __init set_pxa_fb_parent(struct device *parent_dev)
134	{
135	pxa_device_fb.dev.parent = parent_dev;
136	}
137
138	static struct resource pxa_resource_ffuart[] = {
139	{
140	.start = __PREG(FFUART),
141	.end = __PREG(FFUART) + 35,
142	.flags = IORESOURCE_MEM,
143	}, {
144	.start = IRQ_FFUART,
145	.end = IRQ_FFUART,
146	.flags = IORESOURCE_IRQ,
147	}
148	};
149
150	struct platform_device pxa_device_ffuart= {
151	.name = "pxa2xx-uart",
152	.id = 0,
153	.resource = pxa_resource_ffuart,
154	.num_resources = ARRAY_SIZE(pxa_resource_ffuart),
155	};
156
157	static struct resource pxa_resource_btuart[] = {
158	{
159	.start = __PREG(BTUART),
160	.end = __PREG(BTUART) + 35,
161	.flags = IORESOURCE_MEM,
162	}, {
163	.start = IRQ_BTUART,
164	.end = IRQ_BTUART,
165	.flags = IORESOURCE_IRQ,
166	}
167	};
168
169	struct platform_device pxa_device_btuart = {
170	.name = "pxa2xx-uart",
171	.id = 1,
172	.resource = pxa_resource_btuart,
173	.num_resources = ARRAY_SIZE(pxa_resource_btuart),
174	};
175
176	static struct resource pxa_resource_stuart[] = {
177	{
178	.start = __PREG(STUART),
179	.end = __PREG(STUART) + 35,
180	.flags = IORESOURCE_MEM,
181	}, {
182	.start = IRQ_STUART,
183	.end = IRQ_STUART,
184	.flags = IORESOURCE_IRQ,
185	}
186	};
187
188	struct platform_device pxa_device_stuart = {
189	.name = "pxa2xx-uart",
190	.id = 2,
191	.resource = pxa_resource_stuart,
192	.num_resources = ARRAY_SIZE(pxa_resource_stuart),
193	};
194
195	static struct resource pxa_resource_hwuart[] = {
196	{
197	.start = __PREG(HWUART),
198	.end = __PREG(HWUART) + 47,
199	.flags = IORESOURCE_MEM,
200	}, {
201	.start = IRQ_HWUART,
202	.end = IRQ_HWUART,
203	.flags = IORESOURCE_IRQ,
204	}
205	};
206
207	struct platform_device pxa_device_hwuart = {
208	.name = "pxa2xx-uart",
209	.id = 3,
210	.resource = pxa_resource_hwuart,
211	.num_resources = ARRAY_SIZE(pxa_resource_hwuart),
212	};
213
214	static struct resource pxai2c_resources[] = {
215	{
216	.start = 0x40301680,
217	.end = 0x403016a3,
218	.flags = IORESOURCE_MEM,
219	}, {
220	.start = IRQ_I2C,
221	.end = IRQ_I2C,
222	.flags = IORESOURCE_IRQ,
223	},
224	};
225
226	struct platform_device pxa_device_i2c = {
227	.name = "pxa2xx-i2c",
228	.id = 0,
229	.resource = pxai2c_resources,
230	.num_resources = ARRAY_SIZE(pxai2c_resources),
231	};
232
233	void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
234	{
235	pxa_register_device(&pxa_device_i2c, info);
236	}
237
238	static struct resource pxai2s_resources[] = {
239	{
240	.start = 0x40400000,
241	.end = 0x40400083,
242	.flags = IORESOURCE_MEM,
243	}, {
244	.start = IRQ_I2S,
245	.end = IRQ_I2S,
246	.flags = IORESOURCE_IRQ,
247	},
248	};
249
250	struct platform_device pxa_device_i2s = {
251	.name = "pxa2xx-i2s",
252	.id = -1,
253	.resource = pxai2s_resources,
254	.num_resources = ARRAY_SIZE(pxai2s_resources),
255	};
256
257	static u64 pxaficp_dmamask = ~(u32)0;
258
259	struct platform_device pxa_device_ficp = {
260	.name = "pxa2xx-ir",
261	.id = -1,
262	.dev = {
263	.dma_mask = &pxaficp_dmamask,
264	.coherent_dma_mask = 0xffffffff,
265	},
266	};
267
268	void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
269	{
270	pxa_register_device(&pxa_device_ficp, info);
271	}
272
273	struct platform_device pxa_device_rtc = {
274	.name = "sa1100-rtc",
275	.id = -1,
276	};
277
278	#ifdef CONFIG_PXA25x
279
280	static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
281
282	static struct resource pxa25x_resource_ssp[] = {
283	[0] = {
284	.start = 0x41000000,
285	.end = 0x4100001f,
286	.flags = IORESOURCE_MEM,
287	},
288	[1] = {
289	.start = IRQ_SSP,
290	.end = IRQ_SSP,
291	.flags = IORESOURCE_IRQ,
292	},
293	[2] = {
294	/* DRCMR for RX */
295	.start = 13,
296	.end = 13,
297	.flags = IORESOURCE_DMA,
298	},
299	[3] = {
300	/* DRCMR for TX */
301	.start = 14,
302	.end = 14,
303	.flags = IORESOURCE_DMA,
304	},
305	};
306
307	struct platform_device pxa25x_device_ssp = {
308	.name = "pxa25x-ssp",
309	.id = 0,
310	.dev = {
311	.dma_mask = &pxa25x_ssp_dma_mask,
312	.coherent_dma_mask = DMA_BIT_MASK(32),
313	},
314	.resource = pxa25x_resource_ssp,
315	.num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
316	};
317
318	static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
319
320	static struct resource pxa25x_resource_nssp[] = {
321	[0] = {
322	.start = 0x41400000,
323	.end = 0x4140002f,
324	.flags = IORESOURCE_MEM,
325	},
326	[1] = {
327	.start = IRQ_NSSP,
328	.end = IRQ_NSSP,
329	.flags = IORESOURCE_IRQ,
330	},
331	[2] = {
332	/* DRCMR for RX */
333	.start = 15,
334	.end = 15,
335	.flags = IORESOURCE_DMA,
336	},
337	[3] = {
338	/* DRCMR for TX */
339	.start = 16,
340	.end = 16,
341	.flags = IORESOURCE_DMA,
342	},
343	};
344
345	struct platform_device pxa25x_device_nssp = {
346	.name = "pxa25x-nssp",
347	.id = 1,
348	.dev = {
349	.dma_mask = &pxa25x_nssp_dma_mask,
350	.coherent_dma_mask = DMA_BIT_MASK(32),
351	},
352	.resource = pxa25x_resource_nssp,
353	.num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
354	};
355
356	static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
357
358	static struct resource pxa25x_resource_assp[] = {
359	[0] = {
360	.start = 0x41500000,
361	.end = 0x4150002f,
362	.flags = IORESOURCE_MEM,
363	},
364	[1] = {
365	.start = IRQ_ASSP,
366	.end = IRQ_ASSP,
367	.flags = IORESOURCE_IRQ,
368	},
369	[2] = {
370	/* DRCMR for RX */
371	.start = 23,
372	.end = 23,
373	.flags = IORESOURCE_DMA,
374	},
375	[3] = {
376	/* DRCMR for TX */
377	.start = 24,
378	.end = 24,
379	.flags = IORESOURCE_DMA,
380	},
381	};
382
383	struct platform_device pxa25x_device_assp = {
384	/* ASSP is basically equivalent to NSSP */
385	.name = "pxa25x-nssp",
386	.id = 2,
387	.dev = {
388	.dma_mask = &pxa25x_assp_dma_mask,
389	.coherent_dma_mask = DMA_BIT_MASK(32),
390	},
391	.resource = pxa25x_resource_assp,
392	.num_resources = ARRAY_SIZE(pxa25x_resource_assp),
393	};
394	#endif /* CONFIG_PXA25x */
395
396	#if defined(CONFIG_PXA27x) \|\| defined(CONFIG_PXA3xx)
397
398	static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
399
400	static struct resource pxa27x_resource_ssp1[] = {
401	[0] = {
402	.start = 0x41000000,
403	.end = 0x4100003f,
404	.flags = IORESOURCE_MEM,
405	},
406	[1] = {
407	.start = IRQ_SSP,
408	.end = IRQ_SSP,
409	.flags = IORESOURCE_IRQ,
410	},
411	[2] = {
412	/* DRCMR for RX */
413	.start = 13,
414	.end = 13,
415	.flags = IORESOURCE_DMA,
416	},
417	[3] = {
418	/* DRCMR for TX */
419	.start = 14,
420	.end = 14,
421	.flags = IORESOURCE_DMA,
422	},
423	};
424
425	struct platform_device pxa27x_device_ssp1 = {
426	.name = "pxa27x-ssp",
427	.id = 0,
428	.dev = {
429	.dma_mask = &pxa27x_ssp1_dma_mask,
430	.coherent_dma_mask = DMA_BIT_MASK(32),
431	},
432	.resource = pxa27x_resource_ssp1,
433	.num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
434	};
435
436	static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
437
438	static struct resource pxa27x_resource_ssp2[] = {
439	[0] = {
440	.start = 0x41700000,
441	.end = 0x4170003f,
442	.flags = IORESOURCE_MEM,
443	},
444	[1] = {
445	.start = IRQ_SSP2,
446	.end = IRQ_SSP2,
447	.flags = IORESOURCE_IRQ,
448	},
449	[2] = {
450	/* DRCMR for RX */
451	.start = 15,
452	.end = 15,
453	.flags = IORESOURCE_DMA,
454	},
455	[3] = {
456	/* DRCMR for TX */
457	.start = 16,
458	.end = 16,
459	.flags = IORESOURCE_DMA,
460	},
461	};
462
463	struct platform_device pxa27x_device_ssp2 = {
464	.name = "pxa27x-ssp",
465	.id = 1,
466	.dev = {
467	.dma_mask = &pxa27x_ssp2_dma_mask,
468	.coherent_dma_mask = DMA_BIT_MASK(32),
469	},
470	.resource = pxa27x_resource_ssp2,
471	.num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
472	};
473
474	static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
475
476	static struct resource pxa27x_resource_ssp3[] = {
477	[0] = {
478	.start = 0x41900000,
479	.end = 0x4190003f,
480	.flags = IORESOURCE_MEM,
481	},
482	[1] = {
483	.start = IRQ_SSP3,
484	.end = IRQ_SSP3,
485	.flags = IORESOURCE_IRQ,
486	},
487	[2] = {
488	/* DRCMR for RX */
489	.start = 66,
490	.end = 66,
491	.flags = IORESOURCE_DMA,
492	},
493	[3] = {
494	/* DRCMR for TX */
495	.start = 67,
496	.end = 67,
497	.flags = IORESOURCE_DMA,
498	},
499	};
500
501	struct platform_device pxa27x_device_ssp3 = {
502	.name = "pxa27x-ssp",
503	.id = 2,
504	.dev = {
505	.dma_mask = &pxa27x_ssp3_dma_mask,
506	.coherent_dma_mask = DMA_BIT_MASK(32),
507	},
508	.resource = pxa27x_resource_ssp3,
509	.num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
510	};
511	#endif /* CONFIG_PXA27x \|\| CONFIG_PXA3xx */
512
513	#ifdef CONFIG_PXA3xx
514	static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
515
516	static struct resource pxa3xx_resource_ssp4[] = {
517	[0] = {
518	.start = 0x41a00000,
519	.end = 0x41a0003f,
520	.flags = IORESOURCE_MEM,
521	},
522	[1] = {
523	.start = IRQ_SSP4,
524	.end = IRQ_SSP4,
525	.flags = IORESOURCE_IRQ,
526	},
527	[2] = {
528	/* DRCMR for RX */
529	.start = 2,
530	.end = 2,
531	.flags = IORESOURCE_DMA,
532	},
533	[3] = {
534	/* DRCMR for TX */
535	.start = 3,
536	.end = 3,
537	.flags = IORESOURCE_DMA,
538	},
539	};
540
541	struct platform_device pxa3xx_device_ssp4 = {
542	/* PXA3xx SSP is basically equivalent to PXA27x */
543	.name = "pxa27x-ssp",
544	.id = 3,
545	.dev = {
546	.dma_mask = &pxa3xx_ssp4_dma_mask,
547	.coherent_dma_mask = DMA_BIT_MASK(32),
548	},
549	.resource = pxa3xx_resource_ssp4,
550	.num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
551	};
552	#endif /* CONFIG_PXA3xx */