[deliverable/linux.git] / arch / arm / mach-pxa / gpio.c

/*
 *  linux/arch/arm/mach-pxa/gpio.c
 *
 *  Generic PXA GPIO handling
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/sysdev.h>
#include <linux/io.h>

#include <asm/gpio.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>

#include "generic.h"

#define GPIO0_BASE	((void __iomem *)io_p2v(0x40E00000))
#define GPIO1_BASE	((void __iomem *)io_p2v(0x40E00004))
#define GPIO2_BASE	((void __iomem *)io_p2v(0x40E00008))
#define GPIO3_BASE	((void __iomem *)io_p2v(0x40E00100))

#define GPLR_OFFSET	0x00
#define GPDR_OFFSET	0x0C
#define GPSR_OFFSET	0x18
#define GPCR_OFFSET	0x24
#define GRER_OFFSET	0x30
#define GFER_OFFSET	0x3C
#define GEDR_OFFSET	0x48

struct pxa_gpio_chip {
	struct gpio_chip chip;
	void __iomem     *regbase;
};

int pxa_last_gpio;

/*
 * Configure pins for GPIO or other functions
 */
int pxa_gpio_mode(int gpio_mode)
{
	unsigned long flags;
	int gpio = gpio_mode & GPIO_MD_MASK_NR;
	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
	int gafr;

	if (gpio > pxa_last_gpio)
		return -EINVAL;

	local_irq_save(flags);
	if (gpio_mode & GPIO_DFLT_LOW)
		GPCR(gpio) = GPIO_bit(gpio);
	else if (gpio_mode & GPIO_DFLT_HIGH)
		GPSR(gpio) = GPIO_bit(gpio);
	if (gpio_mode & GPIO_MD_MASK_DIR)
		GPDR(gpio) |= GPIO_bit(gpio);
	else
		GPDR(gpio) &= ~GPIO_bit(gpio);
	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
	local_irq_restore(flags);

	return 0;
}
EXPORT_SYMBOL(pxa_gpio_mode);

static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	unsigned long        flags;
	u32                  mask = 1 << offset;
	u32                  value;
	struct pxa_gpio_chip *pxa;
	void __iomem         *gpdr;

	pxa = container_of(chip, struct pxa_gpio_chip, chip);
	gpdr = pxa->regbase + GPDR_OFFSET;
	local_irq_save(flags);
	value = __raw_readl(gpdr);
	if (__gpio_is_inverted(chip->base + offset))
		value |= mask;
	else
		value &= ~mask;
	__raw_writel(value, gpdr);
	local_irq_restore(flags);

	return 0;
}

static int pxa_gpio_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	unsigned long        flags;
	u32                  mask = 1 << offset;
	u32                  tmp;
	struct pxa_gpio_chip *pxa;
	void __iomem         *gpdr;

	pxa = container_of(chip, struct pxa_gpio_chip, chip);
	__raw_writel(mask,
			pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
	gpdr = pxa->regbase + GPDR_OFFSET;
	local_irq_save(flags);
	tmp = __raw_readl(gpdr);
	if (__gpio_is_inverted(chip->base + offset))
		tmp &= ~mask;
	else
		tmp |= mask;
	__raw_writel(tmp, gpdr);
	local_irq_restore(flags);

	return 0;
}

/*
 * Return GPIO level
 */
static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	u32                  mask = 1 << offset;
	struct pxa_gpio_chip *pxa;

	pxa = container_of(chip, struct pxa_gpio_chip, chip);
	return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
}

/*
 * Set output GPIO level
 */
static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	u32                  mask = 1 << offset;
	struct pxa_gpio_chip *pxa;

	pxa = container_of(chip, struct pxa_gpio_chip, chip);

	if (value)
		__raw_writel(mask, pxa->regbase + GPSR_OFFSET);
	else
		__raw_writel(mask, pxa->regbase + GPCR_OFFSET);
}

#define GPIO_CHIP(_n)							\
	[_n] = {							\
		.regbase = GPIO##_n##_BASE,				\
		.chip = {						\
			.label		  = "gpio-" #_n,		\
			.direction_input  = pxa_gpio_direction_input,	\
			.direction_output = pxa_gpio_direction_output,	\
			.get		  = pxa_gpio_get,		\
			.set		  = pxa_gpio_set,		\
			.base		  = (_n) * 32,			\
			.ngpio		  = 32,				\
		},							\
	}

static struct pxa_gpio_chip pxa_gpio_chip[] = {
	GPIO_CHIP(0),
	GPIO_CHIP(1),
	GPIO_CHIP(2),
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
	GPIO_CHIP(3),
#endif
};

static void __init pxa_init_gpio_chip(int gpio_nr)
{
	int i, gpio;

	/* add a GPIO chip for each register bank.
	 * the last PXA25x register only contains 21 GPIOs
	 */
	for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
		if (gpio + 32 > gpio_nr)
			pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
		gpiochip_add(&pxa_gpio_chip[i].chip);
	}
}

/*
 * PXA GPIO edge detection for IRQs:
 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 * Use this instead of directly setting GRER/GFER.
 */

static unsigned long GPIO_IRQ_rising_edge[4];
static unsigned long GPIO_IRQ_falling_edge[4];
static unsigned long GPIO_IRQ_mask[4];

static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
{
	int gpio, idx;

	gpio = IRQ_TO_GPIO(irq);
	idx = gpio >> 5;

	if (type == IRQ_TYPE_PROBE) {
		/* Don't mess with enabled GPIOs using preconfigured edges or
		 * GPIOs set to alternate function or to output during probe
		 */
		if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) ||
		    (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio)))
			return 0;

		if (__gpio_is_occupied(gpio))
			return 0;

		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	if (__gpio_is_inverted(gpio))
		GPDR(gpio) |= GPIO_bit(gpio);
	else
		GPDR(gpio) &= ~GPIO_bit(gpio);

	if (type & IRQ_TYPE_EDGE_RISING)
		__set_bit(gpio, GPIO_IRQ_rising_edge);
	else
		__clear_bit(gpio, GPIO_IRQ_rising_edge);

	if (type & IRQ_TYPE_EDGE_FALLING)
		__set_bit(gpio, GPIO_IRQ_falling_edge);
	else
		__clear_bit(gpio, GPIO_IRQ_falling_edge);

	GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
	GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];

	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
		((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
		((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	return 0;
}

/*
 * Demux handler for GPIO>=2 edge detect interrupts
 */

#define GEDR_BITS	(sizeof(gedr) * BITS_PER_BYTE)

static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
	int loop, bit, n;
	unsigned long gedr[4];

	do {
		gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
		gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
		gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
		gedr[3] = GEDR3 & GPIO_IRQ_mask[3];

		GEDR0 = gedr[0]; GEDR1 = gedr[1];
		GEDR2 = gedr[2]; GEDR3 = gedr[3];

		loop = 0;
		bit = find_first_bit(gedr, GEDR_BITS);
		while (bit < GEDR_BITS) {
			loop = 1;

			n = PXA_GPIO_IRQ_BASE + bit;
			generic_handle_irq(n);

			bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
		}
	} while (loop);
}

static void pxa_ack_muxed_gpio(unsigned int irq)
{
	int gpio = irq - IRQ_GPIO(2) + 2;
	GEDR(gpio) = GPIO_bit(gpio);
}

static void pxa_mask_muxed_gpio(unsigned int irq)
{
	int gpio = irq - IRQ_GPIO(2) + 2;
	__clear_bit(gpio, GPIO_IRQ_mask);
	GRER(gpio) &= ~GPIO_bit(gpio);
	GFER(gpio) &= ~GPIO_bit(gpio);
}

static void pxa_unmask_muxed_gpio(unsigned int irq)
{
	int gpio = irq - IRQ_GPIO(2) + 2;
	int idx = gpio >> 5;
	__set_bit(gpio, GPIO_IRQ_mask);
	GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
	GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
}

static struct irq_chip pxa_muxed_gpio_chip = {
	.name		= "GPIO",
	.ack		= pxa_ack_muxed_gpio,
	.mask		= pxa_mask_muxed_gpio,
	.unmask		= pxa_unmask_muxed_gpio,
	.set_type	= pxa_gpio_irq_type,
};

void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
{
	int irq, i;

	pxa_last_gpio = end;

	/* clear all GPIO edge detects */
	for (i = start; i <= end; i += 32) {
		GFER(i) &= ~GPIO_IRQ_mask[i];
		GRER(i) &= ~GPIO_IRQ_mask[i];
		GEDR(i) = GPIO_IRQ_mask[i];
	}

	for (irq  = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
		set_irq_chip(irq, &pxa_muxed_gpio_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	/* Install handler for GPIO>=2 edge detect interrupts */
	set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
	pxa_muxed_gpio_chip.set_wake = fn;

	/* Initialize GPIO chips */
	pxa_init_gpio_chip(end + 1);
}

#ifdef CONFIG_PM

static unsigned long saved_gplr[4];
static unsigned long saved_gpdr[4];
static unsigned long saved_grer[4];
static unsigned long saved_gfer[4];

static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
{
	int i, gpio;

	for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
		saved_gplr[i] = GPLR(gpio);
		saved_gpdr[i] = GPDR(gpio);
		saved_grer[i] = GRER(gpio);
		saved_gfer[i] = GFER(gpio);

		/* Clear GPIO transition detect bits */
		GEDR(gpio) = GEDR(gpio);
	}
	return 0;
}

static int pxa_gpio_resume(struct sys_device *dev)
{
	int i, gpio;

	for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
		/* restore level with set/clear */
		GPSR(gpio) = saved_gplr[i];
		GPCR(gpio) = ~saved_gplr[i];

		GRER(gpio) = saved_grer[i];
		GFER(gpio) = saved_gfer[i];
		GPDR(gpio) = saved_gpdr[i];
	}
	return 0;
}
#else
#define pxa_gpio_suspend	NULL
#define pxa_gpio_resume		NULL
#endif

struct sysdev_class pxa_gpio_sysclass = {
	.name		= "gpio",
	.suspend	= pxa_gpio_suspend,
	.resume		= pxa_gpio_resume,
};

static int __init pxa_gpio_init(void)
{
	return sysdev_class_register(&pxa_gpio_sysclass);
}

core_initcall(pxa_gpio_init);
Commit	Line	Data
1c44f5f1 PZ	1	/*
	2	* linux/arch/arm/mach-pxa/gpio.c
	3	*
	4	* Generic PXA GPIO handling
	5	*
	6	* Author: Nicolas Pitre
	7	* Created: Jun 15, 2001
	8	* Copyright: MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/module.h>
e3630db1	17	#include <linux/irq.h>
663707c1	18	#include <linux/sysdev.h>
fced80c7	19	#include <linux/io.h>
1c44f5f1 PZ	20
1c44f5f1 PZ	21	#include <asm/gpio.h>
a09e64fb	22	#include <mach/hardware.h>
a09e64fb RK	23	#include <mach/pxa-regs.h>
a09e64fb RK	24	#include <mach/pxa2xx-gpio.h>
1c44f5f1 PZ	25
	26	#include "generic.h"
	27
f1647e4c EM	28	#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
	29	#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
	30	#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
	31	#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
	32
	33	#define GPLR_OFFSET 0x00
	34	#define GPDR_OFFSET 0x0C
	35	#define GPSR_OFFSET 0x18
	36	#define GPCR_OFFSET 0x24
	37	#define GRER_OFFSET 0x30
	38	#define GFER_OFFSET 0x3C
	39	#define GEDR_OFFSET 0x48
1c44f5f1 PZ	40
	41	struct pxa_gpio_chip {
	42	struct gpio_chip chip;
	43	void __iomem *regbase;
	44	};
	45
	46	int pxa_last_gpio;
	47
	48	/*
	49	* Configure pins for GPIO or other functions
	50	*/
	51	int pxa_gpio_mode(int gpio_mode)
	52	{
	53	unsigned long flags;
	54	int gpio = gpio_mode & GPIO_MD_MASK_NR;
	55	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
	56	int gafr;
	57
	58	if (gpio > pxa_last_gpio)
	59	return -EINVAL;
	60
	61	local_irq_save(flags);
	62	if (gpio_mode & GPIO_DFLT_LOW)
	63	GPCR(gpio) = GPIO_bit(gpio);
	64	else if (gpio_mode & GPIO_DFLT_HIGH)
	65	GPSR(gpio) = GPIO_bit(gpio);
	66	if (gpio_mode & GPIO_MD_MASK_DIR)
	67	GPDR(gpio) \|= GPIO_bit(gpio);
	68	else
	69	GPDR(gpio) &= ~GPIO_bit(gpio);
	70	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
	71	GAFR(gpio) = gafr \| (fn << (((gpio) & 0xf)*2));
	72	local_irq_restore(flags);
	73
	74	return 0;
	75	}
	76	EXPORT_SYMBOL(pxa_gpio_mode);
	77
	78	static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	79	{
	80	unsigned long flags;
	81	u32 mask = 1 << offset;
	82	u32 value;
	83	struct pxa_gpio_chip *pxa;
	84	void __iomem *gpdr;
	85
	86	pxa = container_of(chip, struct pxa_gpio_chip, chip);
	87	gpdr = pxa->regbase + GPDR_OFFSET;
	88	local_irq_save(flags);
	89	value = __raw_readl(gpdr);
067455aa EM	90	if (__gpio_is_inverted(chip->base + offset))
	91	value \|= mask;
	92	else
	93	value &= ~mask;
1c44f5f1 PZ	94	__raw_writel(value, gpdr);
	95	local_irq_restore(flags);
	96
	97	return 0;
	98	}
	99
	100	static int pxa_gpio_direction_output(struct gpio_chip *chip,
	101	unsigned offset, int value)
	102	{
	103	unsigned long flags;
	104	u32 mask = 1 << offset;
	105	u32 tmp;
	106	struct pxa_gpio_chip *pxa;
	107	void __iomem *gpdr;
	108
	109	pxa = container_of(chip, struct pxa_gpio_chip, chip);
	110	__raw_writel(mask,
	111	pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
	112	gpdr = pxa->regbase + GPDR_OFFSET;
	113	local_irq_save(flags);
	114	tmp = __raw_readl(gpdr);
067455aa EM	115	if (__gpio_is_inverted(chip->base + offset))
	116	tmp &= ~mask;
	117	else
	118	tmp \|= mask;
1c44f5f1 PZ	119	__raw_writel(tmp, gpdr);
	120	local_irq_restore(flags);
	121
	122	return 0;
	123	}
	124
	125	/*
	126	* Return GPIO level
	127	*/
	128	static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
	129	{
	130	u32 mask = 1 << offset;
	131	struct pxa_gpio_chip *pxa;
	132
	133	pxa = container_of(chip, struct pxa_gpio_chip, chip);
	134	return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
	135	}
	136
	137	/*
	138	* Set output GPIO level
	139	*/
	140	static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	141	{
	142	u32 mask = 1 << offset;
	143	struct pxa_gpio_chip *pxa;
	144
	145	pxa = container_of(chip, struct pxa_gpio_chip, chip);
	146
	147	if (value)
	148	__raw_writel(mask, pxa->regbase + GPSR_OFFSET);
	149	else
	150	__raw_writel(mask, pxa->regbase + GPCR_OFFSET);
	151	}
	152
0e037bbb	153	#define GPIO_CHIP(_n) \
	154	[_n] = { \
	155	.regbase = GPIO##_n##_BASE, \
	156	.chip = { \
	157	.label = "gpio-" #_n, \
	158	.direction_input = pxa_gpio_direction_input, \
	159	.direction_output = pxa_gpio_direction_output, \
	160	.get = pxa_gpio_get, \
	161	.set = pxa_gpio_set, \
	162	.base = (_n) * 32, \
	163	.ngpio = 32, \
	164	}, \
	165	}
	166
1c44f5f1	167	static struct pxa_gpio_chip pxa_gpio_chip[] = {
0e037bbb	168	GPIO_CHIP(0),
	169	GPIO_CHIP(1),
	170	GPIO_CHIP(2),
1c44f5f1	171	#if defined(CONFIG_PXA27x) \|\| defined(CONFIG_PXA3xx)
0e037bbb	172	GPIO_CHIP(3),
1c44f5f1 PZ	173	#endif
	174	};
	175
a58fbcd8 EM	176	static void __init pxa_init_gpio_chip(int gpio_nr)
	177	{
	178	int i, gpio;
	179
	180	/* add a GPIO chip for each register bank.
	181	* the last PXA25x register only contains 21 GPIOs
	182	*/
	183	for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
	184	if (gpio + 32 > gpio_nr)
	185	pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
	186	gpiochip_add(&pxa_gpio_chip[i].chip);
	187	}
	188	}
	189
e3630db1	190	/*
	191	* PXA GPIO edge detection for IRQs:
	192	* IRQs are generated on Falling-Edge, Rising-Edge, or both.
	193	* Use this instead of directly setting GRER/GFER.
	194	*/
	195
d8a42fc4 DB	196	static unsigned long GPIO_IRQ_rising_edge[4];
	197	static unsigned long GPIO_IRQ_falling_edge[4];
	198	static unsigned long GPIO_IRQ_mask[4];
e3630db1	199
	200	static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
	201	{
	202	int gpio, idx;
	203
	204	gpio = IRQ_TO_GPIO(irq);
	205	idx = gpio >> 5;
	206
	207	if (type == IRQ_TYPE_PROBE) {
	208	/* Don't mess with enabled GPIOs using preconfigured edges or
	209	* GPIOs set to alternate function or to output during probe
	210	*/
067455aa EM	211	if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) \|\|
067455aa EM	212	(GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio)))
e3630db1	213	return 0;
689c04a3	214
689c04a3	215	if (__gpio_is_occupied(gpio))
e3630db1	216	return 0;
689c04a3	217
e3630db1	218	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
	219	}
	220
067455aa EM	221	if (__gpio_is_inverted(gpio))
	222	GPDR(gpio) \|= GPIO_bit(gpio);
	223	else
	224	GPDR(gpio) &= ~GPIO_bit(gpio);
e3630db1	225
	226	if (type & IRQ_TYPE_EDGE_RISING)
	227	__set_bit(gpio, GPIO_IRQ_rising_edge);
	228	else
	229	__clear_bit(gpio, GPIO_IRQ_rising_edge);
	230
	231	if (type & IRQ_TYPE_EDGE_FALLING)
	232	__set_bit(gpio, GPIO_IRQ_falling_edge);
	233	else
	234	__clear_bit(gpio, GPIO_IRQ_falling_edge);
	235
	236	GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
	237	GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
	238
	239	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
	240	((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
	241	((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	242	return 0;
	243	}
	244
e3630db1	245	/*
	246	* Demux handler for GPIO>=2 edge detect interrupts
	247	*/
	248
	249	#define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
	250
	251	static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
	252	{
	253	int loop, bit, n;
	254	unsigned long gedr[4];
	255
	256	do {
	257	gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
	258	gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
	259	gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
	260	gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
	261
	262	GEDR0 = gedr[0]; GEDR1 = gedr[1];
	263	GEDR2 = gedr[2]; GEDR3 = gedr[3];
	264
	265	loop = 0;
	266	bit = find_first_bit(gedr, GEDR_BITS);
	267	while (bit < GEDR_BITS) {
	268	loop = 1;
	269
	270	n = PXA_GPIO_IRQ_BASE + bit;
d8aa0251	271	generic_handle_irq(n);
e3630db1	272
	273	bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
	274	}
	275	} while (loop);
	276	}
	277
	278	static void pxa_ack_muxed_gpio(unsigned int irq)
	279	{
	280	int gpio = irq - IRQ_GPIO(2) + 2;
	281	GEDR(gpio) = GPIO_bit(gpio);
	282	}
	283
	284	static void pxa_mask_muxed_gpio(unsigned int irq)
	285	{
	286	int gpio = irq - IRQ_GPIO(2) + 2;
	287	__clear_bit(gpio, GPIO_IRQ_mask);
	288	GRER(gpio) &= ~GPIO_bit(gpio);
	289	GFER(gpio) &= ~GPIO_bit(gpio);
	290	}
	291
	292	static void pxa_unmask_muxed_gpio(unsigned int irq)
	293	{
	294	int gpio = irq - IRQ_GPIO(2) + 2;
	295	int idx = gpio >> 5;
	296	__set_bit(gpio, GPIO_IRQ_mask);
	297	GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
	298	GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
	299	}
	300
	301	static struct irq_chip pxa_muxed_gpio_chip = {
	302	.name = "GPIO",
	303	.ack = pxa_ack_muxed_gpio,
	304	.mask = pxa_mask_muxed_gpio,
	305	.unmask = pxa_unmask_muxed_gpio,
	306	.set_type = pxa_gpio_irq_type,
	307	};
	308
a58fbcd8	309	void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
e3630db1	310	{
a58fbcd8	311	int irq, i;
e3630db1	312
a58fbcd8	313	pxa_last_gpio = end;
e3630db1	314
e3630db1	315	/* clear all GPIO edge detects */
a58fbcd8 EM	316	for (i = start; i <= end; i += 32) {
	317	GFER(i) &= ~GPIO_IRQ_mask[i];
	318	GRER(i) &= ~GPIO_IRQ_mask[i];
	319	GEDR(i) = GPIO_IRQ_mask[i];
e3630db1	320	}
e3630db1	321
a58fbcd8	322	for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
e3630db1	323	set_irq_chip(irq, &pxa_muxed_gpio_chip);
	324	set_irq_handler(irq, handle_edge_irq);
	325	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	326	}
	327
	328	/* Install handler for GPIO>=2 edge detect interrupts */
a58fbcd8	329	set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
b9e25ace	330	pxa_muxed_gpio_chip.set_wake = fn;
e3630db1	331
a58fbcd8 EM	332	/* Initialize GPIO chips */
a58fbcd8 EM	333	pxa_init_gpio_chip(end + 1);
e3630db1	334	}
663707c1	335
	336	#ifdef CONFIG_PM
	337
	338	static unsigned long saved_gplr[4];
	339	static unsigned long saved_gpdr[4];
	340	static unsigned long saved_grer[4];
	341	static unsigned long saved_gfer[4];
	342
	343	static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
	344	{
	345	int i, gpio;
	346
	347	for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
	348	saved_gplr[i] = GPLR(gpio);
	349	saved_gpdr[i] = GPDR(gpio);
	350	saved_grer[i] = GRER(gpio);
	351	saved_gfer[i] = GFER(gpio);
	352
	353	/* Clear GPIO transition detect bits */
	354	GEDR(gpio) = GEDR(gpio);
	355	}
	356	return 0;
	357	}
	358
	359	static int pxa_gpio_resume(struct sys_device *dev)
	360	{
	361	int i, gpio;
	362
	363	for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
	364	/* restore level with set/clear */
	365	GPSR(gpio) = saved_gplr[i];
	366	GPCR(gpio) = ~saved_gplr[i];
	367
	368	GRER(gpio) = saved_grer[i];
	369	GFER(gpio) = saved_gfer[i];
	370	GPDR(gpio) = saved_gpdr[i];
	371	}
	372	return 0;
	373	}
	374	#else
	375	#define pxa_gpio_suspend NULL
	376	#define pxa_gpio_resume NULL
	377	#endif
	378
	379	struct sysdev_class pxa_gpio_sysclass = {
	380	.name = "gpio",
	381	.suspend = pxa_gpio_suspend,
	382	.resume = pxa_gpio_resume,
	383	};
	384
	385	static int __init pxa_gpio_init(void)
	386	{
	387	return sysdev_class_register(&pxa_gpio_sysclass);
	388	}
	389
	390	core_initcall(pxa_gpio_init);