projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f55be1bf LW |
1 | /* |
| 2 | * Written by Philipp Zabel <philipp.zabel@gmail.com> | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License as published by | |
| 6 | * the Free Software Foundation; either version 2 of the License, or | |
| 7 | * (at your option) any later version. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program; if not, write to the Free Software | |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 17 | * | |
| 18 | */ | |
| 19 | #ifndef __MACH_PXA_GPIO_PXA_H | |
| 20 | #define __MACH_PXA_GPIO_PXA_H | |
| 21 | ||
| 22 | #include <mach/irqs.h> | |
| 23 | #include <mach/hardware.h> | |
| 24 | ||
| 25 | #define GPIO_REGS_VIRT io_p2v(0x40E00000) | |
| 26 | ||
| 27 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) | |
| 7124cb96 | 28 | #define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) |
| f55be1bf LW |
29 | |
| 30 | /* GPIO Pin Level Registers */ | |
| 31 | #define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) | |
| 32 | #define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00) | |
| 33 | #define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00) | |
| 34 | #define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00) | |
| 35 | ||
| 36 | /* GPIO Pin Direction Registers */ | |
| 37 | #define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c) | |
| 38 | #define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c) | |
| 39 | #define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c) | |
| 40 | #define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c) | |
| 41 | ||
| 42 | /* GPIO Pin Output Set Registers */ | |
| 43 | #define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18) | |
| 44 | #define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18) | |
| 45 | #define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18) | |
| 46 | #define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18) | |
| 47 | ||
| 48 | /* GPIO Pin Output Clear Registers */ | |
| 49 | #define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24) | |
| 50 | #define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24) | |
| 51 | #define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24) | |
| 52 | #define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24) | |
| 53 | ||
| 54 | /* GPIO Rising Edge Detect Registers */ | |
| 55 | #define GRER0 GPIO_REG(BANK_OFF(0) + 0x30) | |
| 56 | #define GRER1 GPIO_REG(BANK_OFF(1) + 0x30) | |
| 57 | #define GRER2 GPIO_REG(BANK_OFF(2) + 0x30) | |
| 58 | #define GRER3 GPIO_REG(BANK_OFF(3) + 0x30) | |
| 59 | ||
| 60 | /* GPIO Falling Edge Detect Registers */ | |
| 61 | #define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c) | |
| 62 | #define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c) | |
| 63 | #define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c) | |
| 64 | #define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c) | |
| 65 | ||
| 66 | /* GPIO Edge Detect Status Registers */ | |
| 67 | #define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48) | |
| 68 | #define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48) | |
| 69 | #define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48) | |
| 70 | #define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48) | |
| 71 | ||
| 72 | /* GPIO Alternate Function Select Registers */ | |
| 73 | #define GAFR0_L GPIO_REG(0x0054) | |
| 74 | #define GAFR0_U GPIO_REG(0x0058) | |
| 75 | #define GAFR1_L GPIO_REG(0x005C) | |
| 76 | #define GAFR1_U GPIO_REG(0x0060) | |
| 77 | #define GAFR2_L GPIO_REG(0x0064) | |
| 78 | #define GAFR2_U GPIO_REG(0x0068) | |
| 79 | #define GAFR3_L GPIO_REG(0x006C) | |
| 80 | #define GAFR3_U GPIO_REG(0x0070) | |
| 81 | ||
| 82 | /* More handy macros. The argument is a literal GPIO number. */ | |
| 83 | ||
| 84 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | |
| 85 | ||
| 86 | #define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) | |
| 87 | #define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) | |
| 88 | #define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) | |
| 89 | #define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) | |
| 90 | #define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) | |
| 91 | #define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) | |
| 92 | #define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) | |
| 93 | #define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) | |
| 94 | ||
| 95 | ||
| f55be1bf LW |
96 | #define gpio_to_bank(gpio) ((gpio) >> 5) |
| 97 | ||
| 98 | #ifdef CONFIG_CPU_PXA26x | |
| 99 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, | |
| 100 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | |
| 101 | */ | |
| 102 | static inline int __gpio_is_inverted(unsigned gpio) | |
| 103 | { | |
| 104 | return cpu_is_pxa25x() && gpio > 85; | |
| 105 | } | |
| 106 | #else | |
| 107 | static inline int __gpio_is_inverted(unsigned gpio) { return 0; } | |
| 108 | #endif | |
| 109 | ||
| 110 | /* | |
| 111 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | |
| 112 | * function of a GPIO, and GPDRx cannot be altered once configured. It | |
| 113 | * is attributed as "occupied" here (I know this terminology isn't | |
| 114 | * accurate, you are welcome to propose a better one :-) | |
| 115 | */ | |
| 116 | static inline int __gpio_is_occupied(unsigned gpio) | |
| 117 | { | |
| 118 | if (cpu_is_pxa27x() || cpu_is_pxa25x()) { | |
| 119 | int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; | |
| 120 | int dir = GPDR(gpio) & GPIO_bit(gpio); | |
| 121 | ||
| 122 | if (__gpio_is_inverted(gpio)) | |
| 123 | return af != 1 || dir == 0; | |
| 124 | else | |
| 125 | return af != 0 || dir != 0; | |
| 126 | } else | |
| 127 | return GPDR(gpio) & GPIO_bit(gpio); | |
| 128 | } | |
| 129 | ||
| 130 | #include <plat/gpio-pxa.h> | |
| 131 | #endif /* __MACH_PXA_GPIO_PXA_H */ |