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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/irq.c | |
3 | * | |
4 | * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc. | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/ptrace.h> | |
19 | ||
20 | #include <asm/hardware.h> | |
21 | #include <asm/irq.h> | |
22 | #include <asm/mach/irq.h> | |
23 | #include <asm/arch/pxa-regs.h> | |
24 | ||
25 | #include "generic.h" | |
26 | ||
27 | ||
28 | /* | |
29 | * This is for peripheral IRQs internal to the PXA chip. | |
30 | */ | |
31 | ||
32 | static void pxa_mask_low_irq(unsigned int irq) | |
33 | { | |
34 | ICMR &= ~(1 << (irq + PXA_IRQ_SKIP)); | |
35 | } | |
36 | ||
37 | static void pxa_unmask_low_irq(unsigned int irq) | |
38 | { | |
39 | ICMR |= (1 << (irq + PXA_IRQ_SKIP)); | |
40 | } | |
41 | ||
38c677cb DB |
42 | static struct irq_chip pxa_internal_chip_low = { |
43 | .name = "SC", | |
1da177e4 LT |
44 | .ack = pxa_mask_low_irq, |
45 | .mask = pxa_mask_low_irq, | |
46 | .unmask = pxa_unmask_low_irq, | |
47 | }; | |
48 | ||
49 | #if PXA_INTERNAL_IRQS > 32 | |
50 | ||
51 | /* | |
52 | * This is for the second set of internal IRQs as found on the PXA27x. | |
53 | */ | |
54 | ||
55 | static void pxa_mask_high_irq(unsigned int irq) | |
56 | { | |
57 | ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP)); | |
58 | } | |
59 | ||
60 | static void pxa_unmask_high_irq(unsigned int irq) | |
61 | { | |
62 | ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP)); | |
63 | } | |
64 | ||
38c677cb DB |
65 | static struct irq_chip pxa_internal_chip_high = { |
66 | .name = "SC-hi", | |
1da177e4 LT |
67 | .ack = pxa_mask_high_irq, |
68 | .mask = pxa_mask_high_irq, | |
69 | .unmask = pxa_unmask_high_irq, | |
70 | }; | |
71 | ||
72 | #endif | |
73 | ||
74 | /* | |
75 | * PXA GPIO edge detection for IRQs: | |
76 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | |
77 | * Use this instead of directly setting GRER/GFER. | |
78 | */ | |
79 | ||
80 | static long GPIO_IRQ_rising_edge[4]; | |
81 | static long GPIO_IRQ_falling_edge[4]; | |
82 | static long GPIO_IRQ_mask[4]; | |
83 | ||
84 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | |
85 | { | |
86 | int gpio, idx; | |
87 | ||
88 | gpio = IRQ_TO_GPIO(irq); | |
89 | idx = gpio >> 5; | |
90 | ||
91 | if (type == IRQT_PROBE) { | |
92 | /* Don't mess with enabled GPIOs using preconfigured edges or | |
e033108b GL |
93 | GPIOs set to alternate function or to output during probe */ |
94 | if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) & | |
1da177e4 LT |
95 | GPIO_bit(gpio)) |
96 | return 0; | |
97 | if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) | |
98 | return 0; | |
99 | type = __IRQT_RISEDGE | __IRQT_FALEDGE; | |
100 | } | |
101 | ||
102 | /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */ | |
103 | ||
104 | pxa_gpio_mode(gpio | GPIO_IN); | |
105 | ||
106 | if (type & __IRQT_RISEDGE) { | |
107 | /* printk("rising "); */ | |
108 | __set_bit (gpio, GPIO_IRQ_rising_edge); | |
109 | } else | |
110 | __clear_bit (gpio, GPIO_IRQ_rising_edge); | |
111 | ||
112 | if (type & __IRQT_FALEDGE) { | |
113 | /* printk("falling "); */ | |
114 | __set_bit (gpio, GPIO_IRQ_falling_edge); | |
115 | } else | |
116 | __clear_bit (gpio, GPIO_IRQ_falling_edge); | |
117 | ||
118 | /* printk("edges\n"); */ | |
119 | ||
120 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | |
121 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | |
122 | return 0; | |
123 | } | |
124 | ||
125 | /* | |
126 | * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. | |
127 | */ | |
128 | ||
129 | static void pxa_ack_low_gpio(unsigned int irq) | |
130 | { | |
131 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | |
132 | } | |
133 | ||
38c677cb DB |
134 | static struct irq_chip pxa_low_gpio_chip = { |
135 | .name = "GPIO-l", | |
1da177e4 LT |
136 | .ack = pxa_ack_low_gpio, |
137 | .mask = pxa_mask_low_irq, | |
138 | .unmask = pxa_unmask_low_irq, | |
7801907b | 139 | .set_type = pxa_gpio_irq_type, |
1da177e4 LT |
140 | }; |
141 | ||
142 | /* | |
143 | * Demux handler for GPIO>=2 edge detect interrupts | |
144 | */ | |
145 | ||
10dd5ce2 | 146 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
147 | { |
148 | unsigned int mask; | |
149 | int loop; | |
150 | ||
151 | do { | |
152 | loop = 0; | |
153 | ||
154 | mask = GEDR0 & ~3; | |
155 | if (mask) { | |
156 | GEDR0 = mask; | |
157 | irq = IRQ_GPIO(2); | |
158 | desc = irq_desc + irq; | |
159 | mask >>= 2; | |
160 | do { | |
161 | if (mask & 1) | |
0cd61b68 | 162 | desc_handle_irq(irq, desc); |
1da177e4 LT |
163 | irq++; |
164 | desc++; | |
165 | mask >>= 1; | |
166 | } while (mask); | |
167 | loop = 1; | |
168 | } | |
169 | ||
170 | mask = GEDR1; | |
171 | if (mask) { | |
172 | GEDR1 = mask; | |
173 | irq = IRQ_GPIO(32); | |
174 | desc = irq_desc + irq; | |
175 | do { | |
176 | if (mask & 1) | |
0cd61b68 | 177 | desc_handle_irq(irq, desc); |
1da177e4 LT |
178 | irq++; |
179 | desc++; | |
180 | mask >>= 1; | |
181 | } while (mask); | |
182 | loop = 1; | |
183 | } | |
184 | ||
185 | mask = GEDR2; | |
186 | if (mask) { | |
187 | GEDR2 = mask; | |
188 | irq = IRQ_GPIO(64); | |
189 | desc = irq_desc + irq; | |
190 | do { | |
191 | if (mask & 1) | |
0cd61b68 | 192 | desc_handle_irq(irq, desc); |
1da177e4 LT |
193 | irq++; |
194 | desc++; | |
195 | mask >>= 1; | |
196 | } while (mask); | |
197 | loop = 1; | |
198 | } | |
199 | ||
200 | #if PXA_LAST_GPIO >= 96 | |
201 | mask = GEDR3; | |
202 | if (mask) { | |
203 | GEDR3 = mask; | |
204 | irq = IRQ_GPIO(96); | |
205 | desc = irq_desc + irq; | |
206 | do { | |
207 | if (mask & 1) | |
0cd61b68 | 208 | desc_handle_irq(irq, desc); |
1da177e4 LT |
209 | irq++; |
210 | desc++; | |
211 | mask >>= 1; | |
212 | } while (mask); | |
213 | loop = 1; | |
214 | } | |
215 | #endif | |
216 | } while (loop); | |
217 | } | |
218 | ||
219 | static void pxa_ack_muxed_gpio(unsigned int irq) | |
220 | { | |
221 | int gpio = irq - IRQ_GPIO(2) + 2; | |
222 | GEDR(gpio) = GPIO_bit(gpio); | |
223 | } | |
224 | ||
225 | static void pxa_mask_muxed_gpio(unsigned int irq) | |
226 | { | |
227 | int gpio = irq - IRQ_GPIO(2) + 2; | |
228 | __clear_bit(gpio, GPIO_IRQ_mask); | |
229 | GRER(gpio) &= ~GPIO_bit(gpio); | |
230 | GFER(gpio) &= ~GPIO_bit(gpio); | |
231 | } | |
232 | ||
233 | static void pxa_unmask_muxed_gpio(unsigned int irq) | |
234 | { | |
235 | int gpio = irq - IRQ_GPIO(2) + 2; | |
236 | int idx = gpio >> 5; | |
237 | __set_bit(gpio, GPIO_IRQ_mask); | |
238 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | |
239 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | |
240 | } | |
241 | ||
38c677cb DB |
242 | static struct irq_chip pxa_muxed_gpio_chip = { |
243 | .name = "GPIO", | |
1da177e4 LT |
244 | .ack = pxa_ack_muxed_gpio, |
245 | .mask = pxa_mask_muxed_gpio, | |
246 | .unmask = pxa_unmask_muxed_gpio, | |
7801907b | 247 | .set_type = pxa_gpio_irq_type, |
1da177e4 LT |
248 | }; |
249 | ||
250 | ||
251 | void __init pxa_init_irq(void) | |
252 | { | |
253 | int irq; | |
254 | ||
255 | /* disable all IRQs */ | |
256 | ICMR = 0; | |
257 | ||
258 | /* all IRQs are IRQ, not FIQ */ | |
259 | ICLR = 0; | |
260 | ||
261 | /* clear all GPIO edge detects */ | |
262 | GFER0 = 0; | |
263 | GFER1 = 0; | |
264 | GFER2 = 0; | |
265 | GRER0 = 0; | |
266 | GRER1 = 0; | |
267 | GRER2 = 0; | |
268 | GEDR0 = GEDR0; | |
269 | GEDR1 = GEDR1; | |
270 | GEDR2 = GEDR2; | |
271 | ||
272 | #ifdef CONFIG_PXA27x | |
273 | /* And similarly for the extra regs on the PXA27x */ | |
274 | ICMR2 = 0; | |
275 | ICLR2 = 0; | |
276 | GFER3 = 0; | |
277 | GRER3 = 0; | |
278 | GEDR3 = GEDR3; | |
279 | #endif | |
280 | ||
281 | /* only unmasked interrupts kick us out of idle */ | |
282 | ICCR = 1; | |
283 | ||
284 | /* GPIO 0 and 1 must have their mask bit always set */ | |
285 | GPIO_IRQ_mask[0] = 3; | |
286 | ||
287 | for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { | |
288 | set_irq_chip(irq, &pxa_internal_chip_low); | |
10dd5ce2 | 289 | set_irq_handler(irq, handle_level_irq); |
1da177e4 LT |
290 | set_irq_flags(irq, IRQF_VALID); |
291 | } | |
292 | ||
293 | #if PXA_INTERNAL_IRQS > 32 | |
294 | for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { | |
295 | set_irq_chip(irq, &pxa_internal_chip_high); | |
10dd5ce2 | 296 | set_irq_handler(irq, handle_level_irq); |
1da177e4 LT |
297 | set_irq_flags(irq, IRQF_VALID); |
298 | } | |
299 | #endif | |
300 | ||
301 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | |
302 | set_irq_chip(irq, &pxa_low_gpio_chip); | |
10dd5ce2 | 303 | set_irq_handler(irq, handle_edge_irq); |
1da177e4 LT |
304 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
305 | } | |
306 | ||
307 | for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { | |
308 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | |
10dd5ce2 | 309 | set_irq_handler(irq, handle_edge_irq); |
1da177e4 LT |
310 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
311 | } | |
312 | ||
313 | /* Install handler for GPIO>=2 edge detect interrupts */ | |
314 | set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); | |
315 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | |
316 | } |