[deliverable/linux.git] / arch / arm / mach-pxa / lpd270.c

/*
 * linux/arch/arm/mach-pxa/lpd270.c
 *
 * Support for the LogicPD PXA270 Card Engine.
 * Derived from the mainstone code, which carries these notices:
 *
 * Author:	Nicolas Pitre
 * Created:	Nov 05, 2002
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>

#include "pxa27x.h"
#include "lpd270.h"
#include <mach/audio.h>
#include <linux/platform_data/video-pxafb.h>
#include <linux/platform_data/mmc-pxamci.h>
#include <linux/platform_data/irda-pxaficp.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"

static unsigned long lpd270_pin_config[] __initdata = {
	/* Chip Selects */
	GPIO15_nCS_1,	/* Mainboard Flash */
	GPIO78_nCS_2,	/* CPLD + Ethernet */

	/* LCD - 16bpp Active TFT */
	GPIO58_LCD_LDD_0,
	GPIO59_LCD_LDD_1,
	GPIO60_LCD_LDD_2,
	GPIO61_LCD_LDD_3,
	GPIO62_LCD_LDD_4,
	GPIO63_LCD_LDD_5,
	GPIO64_LCD_LDD_6,
	GPIO65_LCD_LDD_7,
	GPIO66_LCD_LDD_8,
	GPIO67_LCD_LDD_9,
	GPIO68_LCD_LDD_10,
	GPIO69_LCD_LDD_11,
	GPIO70_LCD_LDD_12,
	GPIO71_LCD_LDD_13,
	GPIO72_LCD_LDD_14,
	GPIO73_LCD_LDD_15,
	GPIO74_LCD_FCLK,
	GPIO75_LCD_LCLK,
	GPIO76_LCD_PCLK,
	GPIO77_LCD_BIAS,
	GPIO16_PWM0_OUT,	/* Backlight */

	/* USB Host */
	GPIO88_USBH1_PWR,
	GPIO89_USBH1_PEN,

	/* AC97 */
	GPIO28_AC97_BITCLK,
	GPIO29_AC97_SDATA_IN_0,
	GPIO30_AC97_SDATA_OUT,
	GPIO31_AC97_SYNC,
	GPIO45_AC97_SYSCLK,

	GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
};

static unsigned int lpd270_irq_enabled;

static void lpd270_mask_irq(struct irq_data *d)
{
	int lpd270_irq = d->irq - LPD270_IRQ(0);

	__raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);

	lpd270_irq_enabled &= ~(1 << lpd270_irq);
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static void lpd270_unmask_irq(struct irq_data *d)
{
	int lpd270_irq = d->irq - LPD270_IRQ(0);

	lpd270_irq_enabled |= 1 << lpd270_irq;
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static struct irq_chip lpd270_irq_chip = {
	.name		= "CPLD",
	.irq_ack	= lpd270_mask_irq,
	.irq_mask	= lpd270_mask_irq,
	.irq_unmask	= lpd270_unmask_irq,
};

static void lpd270_irq_handler(struct irq_desc *desc)
{
	unsigned int irq;
	unsigned long pending;

	pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
	do {
		/* clear useless edge notification */
		desc->irq_data.chip->irq_ack(&desc->irq_data);
		if (likely(pending)) {
			irq = LPD270_IRQ(0) + __ffs(pending);
			generic_handle_irq(irq);

			pending = __raw_readw(LPD270_INT_STATUS) &
						lpd270_irq_enabled;
		}
	} while (pending);
}

static void __init lpd270_init_irq(void)
{
	int irq;

	pxa27x_init_irq();

	__raw_writew(0, LPD270_INT_MASK);
	__raw_writew(0, LPD270_INT_STATUS);

	/* setup extra LogicPD PXA270 irqs */
	for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
		irq_set_chip_and_handler(irq, &lpd270_irq_chip,
					 handle_level_irq);
		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
	}
	irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
	irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
}


#ifdef CONFIG_PM
static void lpd270_irq_resume(void)
{
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static struct syscore_ops lpd270_irq_syscore_ops = {
	.resume = lpd270_irq_resume,
};

static int __init lpd270_irq_device_init(void)
{
	if (machine_is_logicpd_pxa270()) {
		register_syscore_ops(&lpd270_irq_syscore_ops);
		return 0;
	}
	return -ENODEV;
}

device_initcall(lpd270_irq_device_init);
#endif


static struct resource smc91x_resources[] = {
	[0] = {
		.start	= LPD270_ETH_PHYS,
		.end	= (LPD270_ETH_PHYS + 0xfffff),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= LPD270_ETHERNET_IRQ,
		.end	= LPD270_ETHERNET_IRQ,
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	},
};

struct smc91x_platdata smc91x_platdata = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
	.dev.platform_data = &smc91x_platdata,
};

static struct resource lpd270_flash_resources[] = {
	[0] = {
		.start	= PXA_CS0_PHYS,
		.end	= PXA_CS0_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= PXA_CS1_PHYS,
		.end	= PXA_CS1_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct mtd_partition lpd270_flash0_partitions[] = {
	{
		.name =		"Bootloader",
		.size =		0x00040000,
		.offset =	0,
		.mask_flags =	MTD_WRITEABLE  /* force read-only */
	}, {
		.name =		"Kernel",
		.size =		0x00400000,
		.offset =	0x00040000,
	}, {
		.name =		"Filesystem",
		.size =		MTDPART_SIZ_FULL,
		.offset =	0x00440000
	},
};

static struct flash_platform_data lpd270_flash_data[2] = {
	{
		.name		= "processor-flash",
		.map_name	= "cfi_probe",
		.parts		= lpd270_flash0_partitions,
		.nr_parts	= ARRAY_SIZE(lpd270_flash0_partitions),
	}, {
		.name		= "mainboard-flash",
		.map_name	= "cfi_probe",
		.parts		= NULL,
		.nr_parts	= 0,
	}
};

static struct platform_device lpd270_flash_device[2] = {
	{
		.name		= "pxa2xx-flash",
		.id		= 0,
		.dev = {
			.platform_data	= &lpd270_flash_data[0],
		},
		.resource	= &lpd270_flash_resources[0],
		.num_resources	= 1,
	}, {
		.name		= "pxa2xx-flash",
		.id		= 1,
		.dev = {
			.platform_data	= &lpd270_flash_data[1],
		},
		.resource	= &lpd270_flash_resources[1],
		.num_resources	= 1,
	},
};

static struct pwm_lookup lpd270_pwm_lookup[] = {
	PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
		   PWM_POLARITY_NORMAL),
};

static struct platform_pwm_backlight_data lpd270_backlight_data = {
	.max_brightness	= 1,
	.dft_brightness	= 1,
	.enable_gpio	= -1,
};

static struct platform_device lpd270_backlight_device = {
	.name		= "pwm-backlight",
	.dev		= {
		.parent	= &pxa27x_device_pwm0.dev,
		.platform_data = &lpd270_backlight_data,
	},
};

/* 5.7" TFT QVGA (LoLo display number 1) */
static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
	.pixclock		= 150000,
	.xres			= 320,
	.yres			= 240,
	.bpp			= 16,
	.hsync_len		= 0x14,
	.left_margin		= 0x28,
	.right_margin		= 0x0a,
	.vsync_len		= 0x02,
	.upper_margin		= 0x08,
	.lower_margin		= 0x14,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq057q3dc02 = {
	.modes			= &sharp_lq057q3dc02_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 12.1" TFT SVGA (LoLo display number 2) */
static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
	.pixclock		= 50000,
	.xres			= 800,
	.yres			= 600,
	.bpp			= 16,
	.hsync_len		= 0x05,
	.left_margin		= 0x52,
	.right_margin		= 0x05,
	.vsync_len		= 0x04,
	.upper_margin		= 0x14,
	.lower_margin		= 0x0a,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq121s1dg31 = {
	.modes			= &sharp_lq121s1dg31_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 3.6" TFT QVGA (LoLo display number 3) */
static struct pxafb_mode_info sharp_lq036q1da01_mode = {
	.pixclock		= 150000,
	.xres			= 320,
	.yres			= 240,
	.bpp			= 16,
	.hsync_len		= 0x0e,
	.left_margin		= 0x04,
	.right_margin		= 0x0a,
	.vsync_len		= 0x03,
	.upper_margin		= 0x03,
	.lower_margin		= 0x03,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq036q1da01 = {
	.modes			= &sharp_lq036q1da01_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 6.4" TFT VGA (LoLo display number 5) */
static struct pxafb_mode_info sharp_lq64d343_mode = {
	.pixclock		= 25000,
	.xres			= 640,
	.yres			= 480,
	.bpp			= 16,
	.hsync_len		= 0x31,
	.left_margin		= 0x89,
	.right_margin		= 0x19,
	.vsync_len		= 0x12,
	.upper_margin		= 0x22,
	.lower_margin		= 0x00,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq64d343 = {
	.modes			= &sharp_lq64d343_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 10.4" TFT VGA (LoLo display number 7) */
static struct pxafb_mode_info sharp_lq10d368_mode = {
	.pixclock		= 25000,
	.xres			= 640,
	.yres			= 480,
	.bpp			= 16,
	.hsync_len		= 0x31,
	.left_margin		= 0x89,
	.right_margin		= 0x19,
	.vsync_len		= 0x12,
	.upper_margin		= 0x22,
	.lower_margin		= 0x00,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq10d368 = {
	.modes			= &sharp_lq10d368_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 3.5" TFT QVGA (LoLo display number 8) */
static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
	.pixclock		= 150000,
	.xres			= 240,
	.yres			= 320,
	.bpp			= 16,
	.hsync_len		= 0x0e,
	.left_margin		= 0x0a,
	.right_margin		= 0x0a,
	.vsync_len		= 0x03,
	.upper_margin		= 0x05,
	.lower_margin		= 0x14,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq035q7db02_20 = {
	.modes			= &sharp_lq035q7db02_20_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

static struct pxafb_mach_info *lpd270_lcd_to_use;

static int __init lpd270_set_lcd(char *str)
{
	if (!strncasecmp(str, "lq057q3dc02", 11)) {
		lpd270_lcd_to_use = &sharp_lq057q3dc02;
	} else if (!strncasecmp(str, "lq121s1dg31", 11)) {
		lpd270_lcd_to_use = &sharp_lq121s1dg31;
	} else if (!strncasecmp(str, "lq036q1da01", 11)) {
		lpd270_lcd_to_use = &sharp_lq036q1da01;
	} else if (!strncasecmp(str, "lq64d343", 8)) {
		lpd270_lcd_to_use = &sharp_lq64d343;
	} else if (!strncasecmp(str, "lq10d368", 8)) {
		lpd270_lcd_to_use = &sharp_lq10d368;
	} else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
		lpd270_lcd_to_use = &sharp_lq035q7db02_20;
	} else {
		printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
	}

	return 1;
}

__setup("lcd=", lpd270_set_lcd);

static struct platform_device *platform_devices[] __initdata = {
	&smc91x_device,
	&lpd270_backlight_device,
	&lpd270_flash_device[0],
	&lpd270_flash_device[1],
};

static struct pxaohci_platform_data lpd270_ohci_platform_data = {
	.port_mode	= PMM_PERPORT_MODE,
	.flags		= ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
};

static void __init lpd270_init(void)
{
	pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));

	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);

	lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
	lpd270_flash_data[1].width = 4;

	/*
	 * System bus arbiter setting:
	 * - Core_Park
	 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	 */
	ARB_CNTRL = ARB_CORE_PARK | 0x234;

	pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

	pxa_set_ac97_info(NULL);

	if (lpd270_lcd_to_use != NULL)
		pxa_set_fb_info(NULL, lpd270_lcd_to_use);

	pxa_set_ohci_info(&lpd270_ohci_platform_data);
}


static struct map_desc lpd270_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long)LPD270_CPLD_VIRT,
		.pfn		= __phys_to_pfn(LPD270_CPLD_PHYS),
		.length		= LPD270_CPLD_SIZE,
		.type		= MT_DEVICE,
	},
};

static void __init lpd270_map_io(void)
{
	pxa27x_map_io();
	iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));

	/* for use I SRAM as framebuffer.  */
	PSLR |= 0x00000F04;
	PCFR  = 0x00000066;
}

MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
	/* Maintainer: Peter Barada */
	.atag_offset	= 0x100,
	.map_io		= lpd270_map_io,
	.nr_irqs	= LPD270_NR_IRQS,
	.init_irq	= lpd270_init_irq,
	.handle_irq	= pxa27x_handle_irq,
	.init_time	= pxa_timer_init,
	.init_machine	= lpd270_init,
	.restart	= pxa_restart,
MACHINE_END
Commit	Line	Data
e9937d4b LB	1	/*
	2	* linux/arch/arm/mach-pxa/lpd270.c
	3	*
	4	* Support for the LogicPD PXA270 Card Engine.
	5	* Derived from the mainstone code, which carries these notices:
	6	*
	7	* Author: Nicolas Pitre
	8	* Created: Nov 05, 2002
	9	* Copyright: MontaVista Software Inc.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
2f8163ba	15	#include <linux/gpio.h>
e9937d4b LB	16	#include <linux/init.h>
e9937d4b LB	17	#include <linux/platform_device.h>
2eaa03b5	18	#include <linux/syscore_ops.h>
e9937d4b LB	19	#include <linux/interrupt.h>
	20	#include <linux/sched.h>
	21	#include <linux/bitops.h>
	22	#include <linux/fb.h>
	23	#include <linux/ioport.h>
	24	#include <linux/mtd/mtd.h>
	25	#include <linux/mtd/partitions.h>
2dc9975a	26	#include <linux/pwm.h>
4a730719	27	#include <linux/pwm_backlight.h>
b70661c7	28	#include <linux/smc91x.h>
e9937d4b LB	29
	30	#include <asm/types.h>
	31	#include <asm/setup.h>
	32	#include <asm/memory.h>
	33	#include <asm/mach-types.h>
a09e64fb	34	#include <mach/hardware.h>
e9937d4b LB	35	#include <asm/irq.h>
	36	#include <asm/sizes.h>
	37
	38	#include <asm/mach/arch.h>
	39	#include <asm/mach/map.h>
	40	#include <asm/mach/irq.h>
	41	#include <asm/mach/flash.h>
	42
4c25c5d2 AB	43	#include "pxa27x.h"
4c25c5d2 AB	44	#include "lpd270.h"
a09e64fb	45	#include <mach/audio.h>
293b2da1 AB	46	#include <linux/platform_data/video-pxafb.h>
	47	#include <linux/platform_data/mmc-pxamci.h>
	48	#include <linux/platform_data/irda-pxaficp.h>
	49	#include <linux/platform_data/usb-ohci-pxa27x.h>
ad68bb9f	50	#include <mach/smemc.h>
e9937d4b LB	51
e9937d4b LB	52	#include "generic.h"
46c41e62	53	#include "devices.h"
e9937d4b	54
fd90ff20 EM	55	static unsigned long lpd270_pin_config[] __initdata = {
	56	/* Chip Selects */
	57	GPIO15_nCS_1, /* Mainboard Flash */
	58	GPIO78_nCS_2, /* CPLD + Ethernet */
	59
	60	/* LCD - 16bpp Active TFT */
	61	GPIO58_LCD_LDD_0,
	62	GPIO59_LCD_LDD_1,
	63	GPIO60_LCD_LDD_2,
	64	GPIO61_LCD_LDD_3,
	65	GPIO62_LCD_LDD_4,
	66	GPIO63_LCD_LDD_5,
	67	GPIO64_LCD_LDD_6,
	68	GPIO65_LCD_LDD_7,
	69	GPIO66_LCD_LDD_8,
	70	GPIO67_LCD_LDD_9,
	71	GPIO68_LCD_LDD_10,
	72	GPIO69_LCD_LDD_11,
	73	GPIO70_LCD_LDD_12,
	74	GPIO71_LCD_LDD_13,
	75	GPIO72_LCD_LDD_14,
	76	GPIO73_LCD_LDD_15,
	77	GPIO74_LCD_FCLK,
	78	GPIO75_LCD_LCLK,
	79	GPIO76_LCD_PCLK,
	80	GPIO77_LCD_BIAS,
	81	GPIO16_PWM0_OUT, /* Backlight */
	82
	83	/* USB Host */
	84	GPIO88_USBH1_PWR,
	85	GPIO89_USBH1_PEN,
	86
	87	/* AC97 */
c11b6a42 EM	88	GPIO28_AC97_BITCLK,
	89	GPIO29_AC97_SDATA_IN_0,
	90	GPIO30_AC97_SDATA_OUT,
	91	GPIO31_AC97_SYNC,
fd90ff20 EM	92	GPIO45_AC97_SYSCLK,
	93
	94	GPIO1_GPIO \| WAKEUP_ON_EDGE_BOTH,
	95	};
e9937d4b LB	96
	97	static unsigned int lpd270_irq_enabled;
	98
a3f4c927	99	static void lpd270_mask_irq(struct irq_data *d)
e9937d4b	100	{
a3f4c927	101	int lpd270_irq = d->irq - LPD270_IRQ(0);
e9937d4b LB	102
	103	__raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
	104
	105	lpd270_irq_enabled &= ~(1 << lpd270_irq);
	106	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
	107	}
	108
a3f4c927	109	static void lpd270_unmask_irq(struct irq_data *d)
e9937d4b	110	{
a3f4c927	111	int lpd270_irq = d->irq - LPD270_IRQ(0);
e9937d4b LB	112
	113	lpd270_irq_enabled \|= 1 << lpd270_irq;
	114	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
	115	}
	116
38c677cb DB	117	static struct irq_chip lpd270_irq_chip = {
38c677cb DB	118	.name = "CPLD",
a3f4c927 LB	119	.irq_ack = lpd270_mask_irq,
	120	.irq_mask = lpd270_mask_irq,
	121	.irq_unmask = lpd270_unmask_irq,
e9937d4b LB	122	};
e9937d4b LB	123
bd0b9ac4	124	static void lpd270_irq_handler(struct irq_desc *desc)
e9937d4b	125	{
6947d04a	126	unsigned int irq;
e9937d4b LB	127	unsigned long pending;
	128
	129	pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
	130	do {
a3f4c927 LB	131	/* clear useless edge notification */
a3f4c927 LB	132	desc->irq_data.chip->irq_ack(&desc->irq_data);
e9937d4b LB	133	if (likely(pending)) {
e9937d4b LB	134	irq = LPD270_IRQ(0) + __ffs(pending);
d8aa0251	135	generic_handle_irq(irq);
e9937d4b LB	136
	137	pending = __raw_readw(LPD270_INT_STATUS) &
	138	lpd270_irq_enabled;
	139	}
	140	} while (pending);
	141	}
	142
	143	static void __init lpd270_init_irq(void)
	144	{
	145	int irq;
	146
cd49104d	147	pxa27x_init_irq();
e9937d4b LB	148
	149	__raw_writew(0, LPD270_INT_MASK);
	150	__raw_writew(0, LPD270_INT_STATUS);
	151
	152	/* setup extra LogicPD PXA270 irqs */
	153	for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
f38c02f3 TG	154	irq_set_chip_and_handler(irq, &lpd270_irq_chip,
f38c02f3 TG	155	handle_level_irq);
e8d36d5d	156	irq_clear_status_flags(irq, IRQ_NOREQUEST \| IRQ_NOPROBE);
e9937d4b	157	}
6384fdad HZ	158	irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
6384fdad HZ	159	irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
e9937d4b LB	160	}
	161
	162
	163	#ifdef CONFIG_PM
2eaa03b5	164	static void lpd270_irq_resume(void)
e9937d4b LB	165	{
e9937d4b LB	166	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
e9937d4b LB	167	}
e9937d4b LB	168
2eaa03b5	169	static struct syscore_ops lpd270_irq_syscore_ops = {
e9937d4b LB	170	.resume = lpd270_irq_resume,
	171	};
	172
e9937d4b LB	173	static int __init lpd270_irq_device_init(void)
e9937d4b LB	174	{
720046de	175	if (machine_is_logicpd_pxa270()) {
2eaa03b5 RW	176	register_syscore_ops(&lpd270_irq_syscore_ops);
2eaa03b5 RW	177	return 0;
720046de	178	}
2eaa03b5	179	return -ENODEV;
e9937d4b LB	180	}
	181
	182	device_initcall(lpd270_irq_device_init);
	183	#endif
	184
	185
	186	static struct resource smc91x_resources[] = {
	187	[0] = {
	188	.start = LPD270_ETH_PHYS,
	189	.end = (LPD270_ETH_PHYS + 0xfffff),
	190	.flags = IORESOURCE_MEM,
	191	},
	192	[1] = {
	193	.start = LPD270_ETHERNET_IRQ,
	194	.end = LPD270_ETHERNET_IRQ,
b70661c7	195	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
e9937d4b LB	196	},
	197	};
	198
b70661c7	199	struct smc91x_platdata smc91x_platdata = {
04b91701	200	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
b70661c7 AB	201	};
b70661c7 AB	202
e9937d4b LB	203	static struct platform_device smc91x_device = {
	204	.name = "smc91x",
	205	.id = 0,
	206	.num_resources = ARRAY_SIZE(smc91x_resources),
	207	.resource = smc91x_resources,
b70661c7	208	.dev.platform_data = &smc91x_platdata,
e9937d4b LB	209	};
e9937d4b LB	210
e9937d4b LB	211	static struct resource lpd270_flash_resources[] = {
	212	[0] = {
	213	.start = PXA_CS0_PHYS,
	214	.end = PXA_CS0_PHYS + SZ_64M - 1,
	215	.flags = IORESOURCE_MEM,
	216	},
	217	[1] = {
	218	.start = PXA_CS1_PHYS,
	219	.end = PXA_CS1_PHYS + SZ_64M - 1,
	220	.flags = IORESOURCE_MEM,
	221	},
	222	};
	223
	224	static struct mtd_partition lpd270_flash0_partitions[] = {
	225	{
	226	.name = "Bootloader",
	227	.size = 0x00040000,
	228	.offset = 0,
	229	.mask_flags = MTD_WRITEABLE /* force read-only */
	230	}, {
	231	.name = "Kernel",
	232	.size = 0x00400000,
	233	.offset = 0x00040000,
	234	}, {
	235	.name = "Filesystem",
	236	.size = MTDPART_SIZ_FULL,
	237	.offset = 0x00440000
	238	},
	239	};
	240
	241	static struct flash_platform_data lpd270_flash_data[2] = {
	242	{
	243	.name = "processor-flash",
	244	.map_name = "cfi_probe",
	245	.parts = lpd270_flash0_partitions,
	246	.nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
	247	}, {
	248	.name = "mainboard-flash",
	249	.map_name = "cfi_probe",
	250	.parts = NULL,
	251	.nr_parts = 0,
	252	}
	253	};
	254
	255	static struct platform_device lpd270_flash_device[2] = {
	256	{
	257	.name = "pxa2xx-flash",
	258	.id = 0,
	259	.dev = {
	260	.platform_data = &lpd270_flash_data[0],
	261	},
	262	.resource = &lpd270_flash_resources[0],
	263	.num_resources = 1,
	264	}, {
	265	.name = "pxa2xx-flash",
	266	.id = 1,
	267	.dev = {
	268	.platform_data = &lpd270_flash_data[1],
	269	},
	270	.resource = &lpd270_flash_resources[1],
	271	.num_resources = 1,
	272	},
	273	};
	274
2dc9975a TR	275	static struct pwm_lookup lpd270_pwm_lookup[] = {
	276	PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
	277	PWM_POLARITY_NORMAL),
	278	};
	279
4a730719	280	static struct platform_pwm_backlight_data lpd270_backlight_data = {
4a730719 RK	281	.max_brightness = 1,
4a730719 RK	282	.dft_brightness = 1,
db01120c	283	.enable_gpio = -1,
4a730719 RK	284	};
	285
	286	static struct platform_device lpd270_backlight_device = {
	287	.name = "pwm-backlight",
	288	.dev = {
	289	.parent = &pxa27x_device_pwm0.dev,
	290	.platform_data = &lpd270_backlight_data,
	291	},
	292	};
e9937d4b LB	293
e9937d4b LB	294	/* 5.7" TFT QVGA (LoLo display number 1) */
d14b272b	295	static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
65660297 LB	296	.pixclock = 150000,
	297	.xres = 320,
	298	.yres = 240,
e9937d4b	299	.bpp = 16,
65660297 LB	300	.hsync_len = 0x14,
	301	.left_margin = 0x28,
	302	.right_margin = 0x0a,
	303	.vsync_len = 0x02,
e9937d4b LB	304	.upper_margin = 0x08,
e9937d4b LB	305	.lower_margin = 0x14,
65660297	306	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	307	};
	308
	309	static struct pxafb_mach_info sharp_lq057q3dc02 = {
	310	.modes = &sharp_lq057q3dc02_mode,
	311	.num_modes = 1,
0219e835 EM	312	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	313	LCD_ALTERNATE_MAPPING,
65660297 LB	314	};
	315
	316	/* 12.1" TFT SVGA (LoLo display number 2) */
d14b272b	317	static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
65660297 LB	318	.pixclock = 50000,
	319	.xres = 800,
	320	.yres = 600,
	321	.bpp = 16,
	322	.hsync_len = 0x05,
	323	.left_margin = 0x52,
	324	.right_margin = 0x05,
	325	.vsync_len = 0x04,
	326	.upper_margin = 0x14,
	327	.lower_margin = 0x0a,
	328	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	329	};
	330
	331	static struct pxafb_mach_info sharp_lq121s1dg31 = {
	332	.modes = &sharp_lq121s1dg31_mode,
	333	.num_modes = 1,
0219e835 EM	334	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	335	LCD_ALTERNATE_MAPPING,
65660297 LB	336	};
	337
	338	/* 3.6" TFT QVGA (LoLo display number 3) */
d14b272b	339	static struct pxafb_mode_info sharp_lq036q1da01_mode = {
65660297 LB	340	.pixclock = 150000,
	341	.xres = 320,
	342	.yres = 240,
	343	.bpp = 16,
	344	.hsync_len = 0x0e,
	345	.left_margin = 0x04,
	346	.right_margin = 0x0a,
	347	.vsync_len = 0x03,
	348	.upper_margin = 0x03,
	349	.lower_margin = 0x03,
	350	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	351	};
	352
	353	static struct pxafb_mach_info sharp_lq036q1da01 = {
	354	.modes = &sharp_lq036q1da01_mode,
	355	.num_modes = 1,
0219e835 EM	356	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	357	LCD_ALTERNATE_MAPPING,
e9937d4b LB	358	};
	359
	360	/* 6.4" TFT VGA (LoLo display number 5) */
d14b272b	361	static struct pxafb_mode_info sharp_lq64d343_mode = {
65660297	362	.pixclock = 25000,
e9937d4b LB	363	.xres = 640,
	364	.yres = 480,
	365	.bpp = 16,
65660297	366	.hsync_len = 0x31,
e9937d4b LB	367	.left_margin = 0x89,
e9937d4b LB	368	.right_margin = 0x19,
65660297	369	.vsync_len = 0x12,
e9937d4b	370	.upper_margin = 0x22,
65660297	371	.lower_margin = 0x00,
e9937d4b	372	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	373	};
	374
	375	static struct pxafb_mach_info sharp_lq64d343 = {
	376	.modes = &sharp_lq64d343_mode,
	377	.num_modes = 1,
0219e835 EM	378	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	379	LCD_ALTERNATE_MAPPING,
65660297 LB	380	};
	381
	382	/* 10.4" TFT VGA (LoLo display number 7) */
d14b272b	383	static struct pxafb_mode_info sharp_lq10d368_mode = {
65660297 LB	384	.pixclock = 25000,
	385	.xres = 640,
	386	.yres = 480,
	387	.bpp = 16,
	388	.hsync_len = 0x31,
	389	.left_margin = 0x89,
	390	.right_margin = 0x19,
	391	.vsync_len = 0x12,
	392	.upper_margin = 0x22,
	393	.lower_margin = 0x00,
	394	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	395	};
	396
	397	static struct pxafb_mach_info sharp_lq10d368 = {
	398	.modes = &sharp_lq10d368_mode,
	399	.num_modes = 1,
0219e835 EM	400	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	401	LCD_ALTERNATE_MAPPING,
e9937d4b LB	402	};
	403
	404	/* 3.5" TFT QVGA (LoLo display number 8) */
d14b272b	405	static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
65660297	406	.pixclock = 150000,
e9937d4b LB	407	.xres = 240,
	408	.yres = 320,
	409	.bpp = 16,
65660297 LB	410	.hsync_len = 0x0e,
	411	.left_margin = 0x0a,
	412	.right_margin = 0x0a,
	413	.vsync_len = 0x03,
e9937d4b LB	414	.upper_margin = 0x05,
e9937d4b LB	415	.lower_margin = 0x14,
65660297	416	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	417	};
	418
	419	static struct pxafb_mach_info sharp_lq035q7db02_20 = {
	420	.modes = &sharp_lq035q7db02_20_mode,
	421	.num_modes = 1,
0219e835 EM	422	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	423	LCD_ALTERNATE_MAPPING,
e9937d4b LB	424	};
e9937d4b LB	425
65660297 LB	426	static struct pxafb_mach_info *lpd270_lcd_to_use;
	427
	428	static int __init lpd270_set_lcd(char *str)
	429	{
2bebf5cb	430	if (!strncasecmp(str, "lq057q3dc02", 11)) {
65660297	431	lpd270_lcd_to_use = &sharp_lq057q3dc02;
2bebf5cb	432	} else if (!strncasecmp(str, "lq121s1dg31", 11)) {
65660297	433	lpd270_lcd_to_use = &sharp_lq121s1dg31;
2bebf5cb	434	} else if (!strncasecmp(str, "lq036q1da01", 11)) {
65660297	435	lpd270_lcd_to_use = &sharp_lq036q1da01;
2bebf5cb	436	} else if (!strncasecmp(str, "lq64d343", 8)) {
65660297	437	lpd270_lcd_to_use = &sharp_lq64d343;
2bebf5cb	438	} else if (!strncasecmp(str, "lq10d368", 8)) {
65660297	439	lpd270_lcd_to_use = &sharp_lq10d368;
2bebf5cb	440	} else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
65660297 LB	441	lpd270_lcd_to_use = &sharp_lq035q7db02_20;
	442	} else {
	443	printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
	444	}
	445
	446	return 1;
	447	}
	448
	449	__setup("lcd=", lpd270_set_lcd);
	450
e9937d4b LB	451	static struct platform_device *platform_devices[] __initdata = {
e9937d4b LB	452	&smc91x_device,
4a730719	453	&lpd270_backlight_device,
e9937d4b LB	454	&lpd270_flash_device[0],
	455	&lpd270_flash_device[1],
	456	};
	457
e9937d4b LB	458	static struct pxaohci_platform_data lpd270_ohci_platform_data = {
e9937d4b LB	459	.port_mode = PMM_PERPORT_MODE,
097b5334	460	.flags = ENABLE_PORT_ALL \| POWER_CONTROL_LOW \| POWER_SENSE_LOW,
e9937d4b LB	461	};
	462
	463	static void __init lpd270_init(void)
	464	{
fd90ff20 EM	465	pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
fd90ff20 EM	466
cc155c6f RK	467	pxa_set_ffuart_info(NULL);
	468	pxa_set_btuart_info(NULL);
	469	pxa_set_stuart_info(NULL);
	470
ad68bb9f	471	lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
e9937d4b LB	472	lpd270_flash_data[1].width = 4;
	473
	474	/*
	475	* System bus arbiter setting:
	476	* - Core_Park
	477	* - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	478	*/
	479	ARB_CNTRL = ARB_CORE_PARK \| 0x234;
	480
2dc9975a	481	pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
e9937d4b LB	482	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
e9937d4b LB	483
9f19d638 MB	484	pxa_set_ac97_info(NULL);
9f19d638 MB	485
65660297	486	if (lpd270_lcd_to_use != NULL)
4321e1a1	487	pxa_set_fb_info(NULL, lpd270_lcd_to_use);
e9937d4b LB	488
	489	pxa_set_ohci_info(&lpd270_ohci_platform_data);
	490	}
	491
	492
	493	static struct map_desc lpd270_io_desc[] __initdata = {
	494	{
97b09da4	495	.virtual = (unsigned long)LPD270_CPLD_VIRT,
e9937d4b LB	496	.pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
	497	.length = LPD270_CPLD_SIZE,
	498	.type = MT_DEVICE,
	499	},
	500	};
	501
	502	static void __init lpd270_map_io(void)
	503	{
851982c1	504	pxa27x_map_io();
e9937d4b LB	505	iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
e9937d4b LB	506
e9937d4b LB	507	/* for use I SRAM as framebuffer. */
	508	PSLR \|= 0x00000F04;
	509	PCFR = 0x00000066;
	510	}
	511
	512	MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
	513	/* Maintainer: Peter Barada */
7375aba6	514	.atag_offset = 0x100,
e9937d4b	515	.map_io = lpd270_map_io,
6ac6b817	516	.nr_irqs = LPD270_NR_IRQS,
e9937d4b	517	.init_irq = lpd270_init_irq,
8a97ae2f	518	.handle_irq = pxa27x_handle_irq,
6bb27d73	519	.init_time = pxa_timer_init,
e9937d4b	520	.init_machine = lpd270_init,
271a74fc	521	.restart = pxa_restart,
e9937d4b	522	MACHINE_END