[deliverable/linux.git] / arch / arm / mach-pxa / lpd270.c

/*
 * linux/arch/arm/mach-pxa/lpd270.c
 *
 * Support for the LogicPD PXA270 Card Engine.
 * Derived from the mainstone code, which carries these notices:
 *
 * Author:	Nicolas Pitre
 * Created:	Nov 05, 2002
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>

#include <mach/pxa27x.h>
#include <mach/lpd270.h>
#include <mach/audio.h>
#include <linux/platform_data/video-pxafb.h>
#include <linux/platform_data/mmc-pxamci.h>
#include <linux/platform_data/irda-pxaficp.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <mach/smemc.h>

#include "generic.h"
#include "devices.h"

static unsigned long lpd270_pin_config[] __initdata = {
	/* Chip Selects */
	GPIO15_nCS_1,	/* Mainboard Flash */
	GPIO78_nCS_2,	/* CPLD + Ethernet */

	/* LCD - 16bpp Active TFT */
	GPIO58_LCD_LDD_0,
	GPIO59_LCD_LDD_1,
	GPIO60_LCD_LDD_2,
	GPIO61_LCD_LDD_3,
	GPIO62_LCD_LDD_4,
	GPIO63_LCD_LDD_5,
	GPIO64_LCD_LDD_6,
	GPIO65_LCD_LDD_7,
	GPIO66_LCD_LDD_8,
	GPIO67_LCD_LDD_9,
	GPIO68_LCD_LDD_10,
	GPIO69_LCD_LDD_11,
	GPIO70_LCD_LDD_12,
	GPIO71_LCD_LDD_13,
	GPIO72_LCD_LDD_14,
	GPIO73_LCD_LDD_15,
	GPIO74_LCD_FCLK,
	GPIO75_LCD_LCLK,
	GPIO76_LCD_PCLK,
	GPIO77_LCD_BIAS,
	GPIO16_PWM0_OUT,	/* Backlight */

	/* USB Host */
	GPIO88_USBH1_PWR,
	GPIO89_USBH1_PEN,

	/* AC97 */
	GPIO28_AC97_BITCLK,
	GPIO29_AC97_SDATA_IN_0,
	GPIO30_AC97_SDATA_OUT,
	GPIO31_AC97_SYNC,
	GPIO45_AC97_SYSCLK,

	GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
};

static unsigned int lpd270_irq_enabled;

static void lpd270_mask_irq(struct irq_data *d)
{
	int lpd270_irq = d->irq - LPD270_IRQ(0);

	__raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);

	lpd270_irq_enabled &= ~(1 << lpd270_irq);
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static void lpd270_unmask_irq(struct irq_data *d)
{
	int lpd270_irq = d->irq - LPD270_IRQ(0);

	lpd270_irq_enabled |= 1 << lpd270_irq;
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static struct irq_chip lpd270_irq_chip = {
	.name		= "CPLD",
	.irq_ack	= lpd270_mask_irq,
	.irq_mask	= lpd270_mask_irq,
	.irq_unmask	= lpd270_unmask_irq,
};

static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long pending;

	pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
	do {
		/* clear useless edge notification */
		desc->irq_data.chip->irq_ack(&desc->irq_data);
		if (likely(pending)) {
			irq = LPD270_IRQ(0) + __ffs(pending);
			generic_handle_irq(irq);

			pending = __raw_readw(LPD270_INT_STATUS) &
						lpd270_irq_enabled;
		}
	} while (pending);
}

static void __init lpd270_init_irq(void)
{
	int irq;

	pxa27x_init_irq();

	__raw_writew(0, LPD270_INT_MASK);
	__raw_writew(0, LPD270_INT_STATUS);

	/* setup extra LogicPD PXA270 irqs */
	for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
		irq_set_chip_and_handler(irq, &lpd270_irq_chip,
					 handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}
	irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
	irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
}


#ifdef CONFIG_PM
static void lpd270_irq_resume(void)
{
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static struct syscore_ops lpd270_irq_syscore_ops = {
	.resume = lpd270_irq_resume,
};

static int __init lpd270_irq_device_init(void)
{
	if (machine_is_logicpd_pxa270()) {
		register_syscore_ops(&lpd270_irq_syscore_ops);
		return 0;
	}
	return -ENODEV;
}

device_initcall(lpd270_irq_device_init);
#endif


static struct resource smc91x_resources[] = {
	[0] = {
		.start	= LPD270_ETH_PHYS,
		.end	= (LPD270_ETH_PHYS + 0xfffff),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= LPD270_ETHERNET_IRQ,
		.end	= LPD270_ETHERNET_IRQ,
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	},
};

struct smc91x_platdata smc91x_platdata = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
	.dev.platform_data = &smc91x_platdata,
};

static struct resource lpd270_flash_resources[] = {
	[0] = {
		.start	= PXA_CS0_PHYS,
		.end	= PXA_CS0_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= PXA_CS1_PHYS,
		.end	= PXA_CS1_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct mtd_partition lpd270_flash0_partitions[] = {
	{
		.name =		"Bootloader",
		.size =		0x00040000,
		.offset =	0,
		.mask_flags =	MTD_WRITEABLE  /* force read-only */
	}, {
		.name =		"Kernel",
		.size =		0x00400000,
		.offset =	0x00040000,
	}, {
		.name =		"Filesystem",
		.size =		MTDPART_SIZ_FULL,
		.offset =	0x00440000
	},
};

static struct flash_platform_data lpd270_flash_data[2] = {
	{
		.name		= "processor-flash",
		.map_name	= "cfi_probe",
		.parts		= lpd270_flash0_partitions,
		.nr_parts	= ARRAY_SIZE(lpd270_flash0_partitions),
	}, {
		.name		= "mainboard-flash",
		.map_name	= "cfi_probe",
		.parts		= NULL,
		.nr_parts	= 0,
	}
};

static struct platform_device lpd270_flash_device[2] = {
	{
		.name		= "pxa2xx-flash",
		.id		= 0,
		.dev = {
			.platform_data	= &lpd270_flash_data[0],
		},
		.resource	= &lpd270_flash_resources[0],
		.num_resources	= 1,
	}, {
		.name		= "pxa2xx-flash",
		.id		= 1,
		.dev = {
			.platform_data	= &lpd270_flash_data[1],
		},
		.resource	= &lpd270_flash_resources[1],
		.num_resources	= 1,
	},
};

static struct platform_pwm_backlight_data lpd270_backlight_data = {
	.pwm_id		= 0,
	.max_brightness	= 1,
	.dft_brightness	= 1,
	.pwm_period_ns	= 78770,
	.enable_gpio	= -1,
};

static struct platform_device lpd270_backlight_device = {
	.name		= "pwm-backlight",
	.dev		= {
		.parent	= &pxa27x_device_pwm0.dev,
		.platform_data = &lpd270_backlight_data,
	},
};

/* 5.7" TFT QVGA (LoLo display number 1) */
static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
	.pixclock		= 150000,
	.xres			= 320,
	.yres			= 240,
	.bpp			= 16,
	.hsync_len		= 0x14,
	.left_margin		= 0x28,
	.right_margin		= 0x0a,
	.vsync_len		= 0x02,
	.upper_margin		= 0x08,
	.lower_margin		= 0x14,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq057q3dc02 = {
	.modes			= &sharp_lq057q3dc02_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 12.1" TFT SVGA (LoLo display number 2) */
static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
	.pixclock		= 50000,
	.xres			= 800,
	.yres			= 600,
	.bpp			= 16,
	.hsync_len		= 0x05,
	.left_margin		= 0x52,
	.right_margin		= 0x05,
	.vsync_len		= 0x04,
	.upper_margin		= 0x14,
	.lower_margin		= 0x0a,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq121s1dg31 = {
	.modes			= &sharp_lq121s1dg31_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 3.6" TFT QVGA (LoLo display number 3) */
static struct pxafb_mode_info sharp_lq036q1da01_mode = {
	.pixclock		= 150000,
	.xres			= 320,
	.yres			= 240,
	.bpp			= 16,
	.hsync_len		= 0x0e,
	.left_margin		= 0x04,
	.right_margin		= 0x0a,
	.vsync_len		= 0x03,
	.upper_margin		= 0x03,
	.lower_margin		= 0x03,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq036q1da01 = {
	.modes			= &sharp_lq036q1da01_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 6.4" TFT VGA (LoLo display number 5) */
static struct pxafb_mode_info sharp_lq64d343_mode = {
	.pixclock		= 25000,
	.xres			= 640,
	.yres			= 480,
	.bpp			= 16,
	.hsync_len		= 0x31,
	.left_margin		= 0x89,
	.right_margin		= 0x19,
	.vsync_len		= 0x12,
	.upper_margin		= 0x22,
	.lower_margin		= 0x00,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq64d343 = {
	.modes			= &sharp_lq64d343_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 10.4" TFT VGA (LoLo display number 7) */
static struct pxafb_mode_info sharp_lq10d368_mode = {
	.pixclock		= 25000,
	.xres			= 640,
	.yres			= 480,
	.bpp			= 16,
	.hsync_len		= 0x31,
	.left_margin		= 0x89,
	.right_margin		= 0x19,
	.vsync_len		= 0x12,
	.upper_margin		= 0x22,
	.lower_margin		= 0x00,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq10d368 = {
	.modes			= &sharp_lq10d368_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 3.5" TFT QVGA (LoLo display number 8) */
static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
	.pixclock		= 150000,
	.xres			= 240,
	.yres			= 320,
	.bpp			= 16,
	.hsync_len		= 0x0e,
	.left_margin		= 0x0a,
	.right_margin		= 0x0a,
	.vsync_len		= 0x03,
	.upper_margin		= 0x05,
	.lower_margin		= 0x14,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq035q7db02_20 = {
	.modes			= &sharp_lq035q7db02_20_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

static struct pxafb_mach_info *lpd270_lcd_to_use;

static int __init lpd270_set_lcd(char *str)
{
	if (!strncasecmp(str, "lq057q3dc02", 11)) {
		lpd270_lcd_to_use = &sharp_lq057q3dc02;
	} else if (!strncasecmp(str, "lq121s1dg31", 11)) {
		lpd270_lcd_to_use = &sharp_lq121s1dg31;
	} else if (!strncasecmp(str, "lq036q1da01", 11)) {
		lpd270_lcd_to_use = &sharp_lq036q1da01;
	} else if (!strncasecmp(str, "lq64d343", 8)) {
		lpd270_lcd_to_use = &sharp_lq64d343;
	} else if (!strncasecmp(str, "lq10d368", 8)) {
		lpd270_lcd_to_use = &sharp_lq10d368;
	} else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
		lpd270_lcd_to_use = &sharp_lq035q7db02_20;
	} else {
		printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
	}

	return 1;
}

__setup("lcd=", lpd270_set_lcd);

static struct platform_device *platform_devices[] __initdata = {
	&smc91x_device,
	&lpd270_backlight_device,
	&lpd270_flash_device[0],
	&lpd270_flash_device[1],
};

static struct pxaohci_platform_data lpd270_ohci_platform_data = {
	.port_mode	= PMM_PERPORT_MODE,
	.flags		= ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
};

static void __init lpd270_init(void)
{
	pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));

	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);

	lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
	lpd270_flash_data[1].width = 4;

	/*
	 * System bus arbiter setting:
	 * - Core_Park
	 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	 */
	ARB_CNTRL = ARB_CORE_PARK | 0x234;

	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

	pxa_set_ac97_info(NULL);

	if (lpd270_lcd_to_use != NULL)
		pxa_set_fb_info(NULL, lpd270_lcd_to_use);

	pxa_set_ohci_info(&lpd270_ohci_platform_data);
}


static struct map_desc lpd270_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long)LPD270_CPLD_VIRT,
		.pfn		= __phys_to_pfn(LPD270_CPLD_PHYS),
		.length		= LPD270_CPLD_SIZE,
		.type		= MT_DEVICE,
	},
};

static void __init lpd270_map_io(void)
{
	pxa27x_map_io();
	iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));

	/* for use I SRAM as framebuffer.  */
	PSLR |= 0x00000F04;
	PCFR  = 0x00000066;
}

MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
	/* Maintainer: Peter Barada */
	.atag_offset	= 0x100,
	.map_io		= lpd270_map_io,
	.nr_irqs	= LPD270_NR_IRQS,
	.init_irq	= lpd270_init_irq,
	.handle_irq	= pxa27x_handle_irq,
	.init_time	= pxa_timer_init,
	.init_machine	= lpd270_init,
	.restart	= pxa_restart,
MACHINE_END
Commit	Line	Data
e9937d4b LB	1	/*
	2	* linux/arch/arm/mach-pxa/lpd270.c
	3	*
	4	* Support for the LogicPD PXA270 Card Engine.
	5	* Derived from the mainstone code, which carries these notices:
	6	*
	7	* Author: Nicolas Pitre
	8	* Created: Nov 05, 2002
	9	* Copyright: MontaVista Software Inc.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
2f8163ba	15	#include <linux/gpio.h>
e9937d4b LB	16	#include <linux/init.h>
e9937d4b LB	17	#include <linux/platform_device.h>
2eaa03b5	18	#include <linux/syscore_ops.h>
e9937d4b LB	19	#include <linux/interrupt.h>
	20	#include <linux/sched.h>
	21	#include <linux/bitops.h>
	22	#include <linux/fb.h>
	23	#include <linux/ioport.h>
	24	#include <linux/mtd/mtd.h>
	25	#include <linux/mtd/partitions.h>
4a730719	26	#include <linux/pwm_backlight.h>
b70661c7	27	#include <linux/smc91x.h>
e9937d4b LB	28
	29	#include <asm/types.h>
	30	#include <asm/setup.h>
	31	#include <asm/memory.h>
	32	#include <asm/mach-types.h>
a09e64fb	33	#include <mach/hardware.h>
e9937d4b LB	34	#include <asm/irq.h>
	35	#include <asm/sizes.h>
	36
	37	#include <asm/mach/arch.h>
	38	#include <asm/mach/map.h>
	39	#include <asm/mach/irq.h>
	40	#include <asm/mach/flash.h>
	41
51c62982	42	#include <mach/pxa27x.h>
a09e64fb RK	43	#include <mach/lpd270.h>
a09e64fb RK	44	#include <mach/audio.h>
293b2da1 AB	45	#include <linux/platform_data/video-pxafb.h>
	46	#include <linux/platform_data/mmc-pxamci.h>
	47	#include <linux/platform_data/irda-pxaficp.h>
	48	#include <linux/platform_data/usb-ohci-pxa27x.h>
ad68bb9f	49	#include <mach/smemc.h>
e9937d4b LB	50
e9937d4b LB	51	#include "generic.h"
46c41e62	52	#include "devices.h"
e9937d4b	53
fd90ff20 EM	54	static unsigned long lpd270_pin_config[] __initdata = {
	55	/* Chip Selects */
	56	GPIO15_nCS_1, /* Mainboard Flash */
	57	GPIO78_nCS_2, /* CPLD + Ethernet */
	58
	59	/* LCD - 16bpp Active TFT */
	60	GPIO58_LCD_LDD_0,
	61	GPIO59_LCD_LDD_1,
	62	GPIO60_LCD_LDD_2,
	63	GPIO61_LCD_LDD_3,
	64	GPIO62_LCD_LDD_4,
	65	GPIO63_LCD_LDD_5,
	66	GPIO64_LCD_LDD_6,
	67	GPIO65_LCD_LDD_7,
	68	GPIO66_LCD_LDD_8,
	69	GPIO67_LCD_LDD_9,
	70	GPIO68_LCD_LDD_10,
	71	GPIO69_LCD_LDD_11,
	72	GPIO70_LCD_LDD_12,
	73	GPIO71_LCD_LDD_13,
	74	GPIO72_LCD_LDD_14,
	75	GPIO73_LCD_LDD_15,
	76	GPIO74_LCD_FCLK,
	77	GPIO75_LCD_LCLK,
	78	GPIO76_LCD_PCLK,
	79	GPIO77_LCD_BIAS,
	80	GPIO16_PWM0_OUT, /* Backlight */
	81
	82	/* USB Host */
	83	GPIO88_USBH1_PWR,
	84	GPIO89_USBH1_PEN,
	85
	86	/* AC97 */
c11b6a42 EM	87	GPIO28_AC97_BITCLK,
	88	GPIO29_AC97_SDATA_IN_0,
	89	GPIO30_AC97_SDATA_OUT,
	90	GPIO31_AC97_SYNC,
fd90ff20 EM	91	GPIO45_AC97_SYSCLK,
	92
	93	GPIO1_GPIO \| WAKEUP_ON_EDGE_BOTH,
	94	};
e9937d4b LB	95
	96	static unsigned int lpd270_irq_enabled;
	97
a3f4c927	98	static void lpd270_mask_irq(struct irq_data *d)
e9937d4b	99	{
a3f4c927	100	int lpd270_irq = d->irq - LPD270_IRQ(0);
e9937d4b LB	101
	102	__raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
	103
	104	lpd270_irq_enabled &= ~(1 << lpd270_irq);
	105	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
	106	}
	107
a3f4c927	108	static void lpd270_unmask_irq(struct irq_data *d)
e9937d4b	109	{
a3f4c927	110	int lpd270_irq = d->irq - LPD270_IRQ(0);
e9937d4b LB	111
	112	lpd270_irq_enabled \|= 1 << lpd270_irq;
	113	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
	114	}
	115
38c677cb DB	116	static struct irq_chip lpd270_irq_chip = {
38c677cb DB	117	.name = "CPLD",
a3f4c927 LB	118	.irq_ack = lpd270_mask_irq,
	119	.irq_mask = lpd270_mask_irq,
	120	.irq_unmask = lpd270_unmask_irq,
e9937d4b LB	121	};
e9937d4b LB	122
10dd5ce2	123	static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
e9937d4b LB	124	{
	125	unsigned long pending;
	126
	127	pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
	128	do {
a3f4c927 LB	129	/* clear useless edge notification */
a3f4c927 LB	130	desc->irq_data.chip->irq_ack(&desc->irq_data);
e9937d4b LB	131	if (likely(pending)) {
e9937d4b LB	132	irq = LPD270_IRQ(0) + __ffs(pending);
d8aa0251	133	generic_handle_irq(irq);
e9937d4b LB	134
	135	pending = __raw_readw(LPD270_INT_STATUS) &
	136	lpd270_irq_enabled;
	137	}
	138	} while (pending);
	139	}
	140
	141	static void __init lpd270_init_irq(void)
	142	{
	143	int irq;
	144
cd49104d	145	pxa27x_init_irq();
e9937d4b LB	146
	147	__raw_writew(0, LPD270_INT_MASK);
	148	__raw_writew(0, LPD270_INT_STATUS);
	149
	150	/* setup extra LogicPD PXA270 irqs */
	151	for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
f38c02f3 TG	152	irq_set_chip_and_handler(irq, &lpd270_irq_chip,
f38c02f3 TG	153	handle_level_irq);
e9937d4b LB	154	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
e9937d4b LB	155	}
6384fdad HZ	156	irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
6384fdad HZ	157	irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
e9937d4b LB	158	}
	159
	160
	161	#ifdef CONFIG_PM
2eaa03b5	162	static void lpd270_irq_resume(void)
e9937d4b LB	163	{
e9937d4b LB	164	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
e9937d4b LB	165	}
e9937d4b LB	166
2eaa03b5	167	static struct syscore_ops lpd270_irq_syscore_ops = {
e9937d4b LB	168	.resume = lpd270_irq_resume,
	169	};
	170
e9937d4b LB	171	static int __init lpd270_irq_device_init(void)
e9937d4b LB	172	{
720046de	173	if (machine_is_logicpd_pxa270()) {
2eaa03b5 RW	174	register_syscore_ops(&lpd270_irq_syscore_ops);
2eaa03b5 RW	175	return 0;
720046de	176	}
2eaa03b5	177	return -ENODEV;
e9937d4b LB	178	}
	179
	180	device_initcall(lpd270_irq_device_init);
	181	#endif
	182
	183
	184	static struct resource smc91x_resources[] = {
	185	[0] = {
	186	.start = LPD270_ETH_PHYS,
	187	.end = (LPD270_ETH_PHYS + 0xfffff),
	188	.flags = IORESOURCE_MEM,
	189	},
	190	[1] = {
	191	.start = LPD270_ETHERNET_IRQ,
	192	.end = LPD270_ETHERNET_IRQ,
b70661c7	193	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
e9937d4b LB	194	},
	195	};
	196
b70661c7	197	struct smc91x_platdata smc91x_platdata = {
04b91701	198	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
b70661c7 AB	199	};
b70661c7 AB	200
e9937d4b LB	201	static struct platform_device smc91x_device = {
	202	.name = "smc91x",
	203	.id = 0,
	204	.num_resources = ARRAY_SIZE(smc91x_resources),
	205	.resource = smc91x_resources,
b70661c7	206	.dev.platform_data = &smc91x_platdata,
e9937d4b LB	207	};
e9937d4b LB	208
e9937d4b LB	209	static struct resource lpd270_flash_resources[] = {
	210	[0] = {
	211	.start = PXA_CS0_PHYS,
	212	.end = PXA_CS0_PHYS + SZ_64M - 1,
	213	.flags = IORESOURCE_MEM,
	214	},
	215	[1] = {
	216	.start = PXA_CS1_PHYS,
	217	.end = PXA_CS1_PHYS + SZ_64M - 1,
	218	.flags = IORESOURCE_MEM,
	219	},
	220	};
	221
	222	static struct mtd_partition lpd270_flash0_partitions[] = {
	223	{
	224	.name = "Bootloader",
	225	.size = 0x00040000,
	226	.offset = 0,
	227	.mask_flags = MTD_WRITEABLE /* force read-only */
	228	}, {
	229	.name = "Kernel",
	230	.size = 0x00400000,
	231	.offset = 0x00040000,
	232	}, {
	233	.name = "Filesystem",
	234	.size = MTDPART_SIZ_FULL,
	235	.offset = 0x00440000
	236	},
	237	};
	238
	239	static struct flash_platform_data lpd270_flash_data[2] = {
	240	{
	241	.name = "processor-flash",
	242	.map_name = "cfi_probe",
	243	.parts = lpd270_flash0_partitions,
	244	.nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
	245	}, {
	246	.name = "mainboard-flash",
	247	.map_name = "cfi_probe",
	248	.parts = NULL,
	249	.nr_parts = 0,
	250	}
	251	};
	252
	253	static struct platform_device lpd270_flash_device[2] = {
	254	{
	255	.name = "pxa2xx-flash",
	256	.id = 0,
	257	.dev = {
	258	.platform_data = &lpd270_flash_data[0],
	259	},
	260	.resource = &lpd270_flash_resources[0],
	261	.num_resources = 1,
	262	}, {
	263	.name = "pxa2xx-flash",
	264	.id = 1,
	265	.dev = {
	266	.platform_data = &lpd270_flash_data[1],
	267	},
	268	.resource = &lpd270_flash_resources[1],
	269	.num_resources = 1,
	270	},
	271	};
	272
4a730719 RK	273	static struct platform_pwm_backlight_data lpd270_backlight_data = {
	274	.pwm_id = 0,
	275	.max_brightness = 1,
	276	.dft_brightness = 1,
	277	.pwm_period_ns = 78770,
db01120c	278	.enable_gpio = -1,
4a730719 RK	279	};
	280
	281	static struct platform_device lpd270_backlight_device = {
	282	.name = "pwm-backlight",
	283	.dev = {
	284	.parent = &pxa27x_device_pwm0.dev,
	285	.platform_data = &lpd270_backlight_data,
	286	},
	287	};
e9937d4b LB	288
e9937d4b LB	289	/* 5.7" TFT QVGA (LoLo display number 1) */
d14b272b	290	static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
65660297 LB	291	.pixclock = 150000,
	292	.xres = 320,
	293	.yres = 240,
e9937d4b	294	.bpp = 16,
65660297 LB	295	.hsync_len = 0x14,
	296	.left_margin = 0x28,
	297	.right_margin = 0x0a,
	298	.vsync_len = 0x02,
e9937d4b LB	299	.upper_margin = 0x08,
e9937d4b LB	300	.lower_margin = 0x14,
65660297	301	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	302	};
	303
	304	static struct pxafb_mach_info sharp_lq057q3dc02 = {
	305	.modes = &sharp_lq057q3dc02_mode,
	306	.num_modes = 1,
0219e835 EM	307	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	308	LCD_ALTERNATE_MAPPING,
65660297 LB	309	};
	310
	311	/* 12.1" TFT SVGA (LoLo display number 2) */
d14b272b	312	static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
65660297 LB	313	.pixclock = 50000,
	314	.xres = 800,
	315	.yres = 600,
	316	.bpp = 16,
	317	.hsync_len = 0x05,
	318	.left_margin = 0x52,
	319	.right_margin = 0x05,
	320	.vsync_len = 0x04,
	321	.upper_margin = 0x14,
	322	.lower_margin = 0x0a,
	323	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	324	};
	325
	326	static struct pxafb_mach_info sharp_lq121s1dg31 = {
	327	.modes = &sharp_lq121s1dg31_mode,
	328	.num_modes = 1,
0219e835 EM	329	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	330	LCD_ALTERNATE_MAPPING,
65660297 LB	331	};
	332
	333	/* 3.6" TFT QVGA (LoLo display number 3) */
d14b272b	334	static struct pxafb_mode_info sharp_lq036q1da01_mode = {
65660297 LB	335	.pixclock = 150000,
	336	.xres = 320,
	337	.yres = 240,
	338	.bpp = 16,
	339	.hsync_len = 0x0e,
	340	.left_margin = 0x04,
	341	.right_margin = 0x0a,
	342	.vsync_len = 0x03,
	343	.upper_margin = 0x03,
	344	.lower_margin = 0x03,
	345	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	346	};
	347
	348	static struct pxafb_mach_info sharp_lq036q1da01 = {
	349	.modes = &sharp_lq036q1da01_mode,
	350	.num_modes = 1,
0219e835 EM	351	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	352	LCD_ALTERNATE_MAPPING,
e9937d4b LB	353	};
	354
	355	/* 6.4" TFT VGA (LoLo display number 5) */
d14b272b	356	static struct pxafb_mode_info sharp_lq64d343_mode = {
65660297	357	.pixclock = 25000,
e9937d4b LB	358	.xres = 640,
	359	.yres = 480,
	360	.bpp = 16,
65660297	361	.hsync_len = 0x31,
e9937d4b LB	362	.left_margin = 0x89,
e9937d4b LB	363	.right_margin = 0x19,
65660297	364	.vsync_len = 0x12,
e9937d4b	365	.upper_margin = 0x22,
65660297	366	.lower_margin = 0x00,
e9937d4b	367	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	368	};
	369
	370	static struct pxafb_mach_info sharp_lq64d343 = {
	371	.modes = &sharp_lq64d343_mode,
	372	.num_modes = 1,
0219e835 EM	373	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	374	LCD_ALTERNATE_MAPPING,
65660297 LB	375	};
	376
	377	/* 10.4" TFT VGA (LoLo display number 7) */
d14b272b	378	static struct pxafb_mode_info sharp_lq10d368_mode = {
65660297 LB	379	.pixclock = 25000,
	380	.xres = 640,
	381	.yres = 480,
	382	.bpp = 16,
	383	.hsync_len = 0x31,
	384	.left_margin = 0x89,
	385	.right_margin = 0x19,
	386	.vsync_len = 0x12,
	387	.upper_margin = 0x22,
	388	.lower_margin = 0x00,
	389	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	390	};
	391
	392	static struct pxafb_mach_info sharp_lq10d368 = {
	393	.modes = &sharp_lq10d368_mode,
	394	.num_modes = 1,
0219e835 EM	395	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	396	LCD_ALTERNATE_MAPPING,
e9937d4b LB	397	};
	398
	399	/* 3.5" TFT QVGA (LoLo display number 8) */
d14b272b	400	static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
65660297	401	.pixclock = 150000,
e9937d4b LB	402	.xres = 240,
	403	.yres = 320,
	404	.bpp = 16,
65660297 LB	405	.hsync_len = 0x0e,
	406	.left_margin = 0x0a,
	407	.right_margin = 0x0a,
	408	.vsync_len = 0x03,
e9937d4b LB	409	.upper_margin = 0x05,
e9937d4b LB	410	.lower_margin = 0x14,
65660297	411	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	412	};
	413
	414	static struct pxafb_mach_info sharp_lq035q7db02_20 = {
	415	.modes = &sharp_lq035q7db02_20_mode,
	416	.num_modes = 1,
0219e835 EM	417	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_PCLK_EDGE_FALL \|
0219e835 EM	418	LCD_ALTERNATE_MAPPING,
e9937d4b LB	419	};
e9937d4b LB	420
65660297 LB	421	static struct pxafb_mach_info *lpd270_lcd_to_use;
	422
	423	static int __init lpd270_set_lcd(char *str)
	424	{
2bebf5cb	425	if (!strncasecmp(str, "lq057q3dc02", 11)) {
65660297	426	lpd270_lcd_to_use = &sharp_lq057q3dc02;
2bebf5cb	427	} else if (!strncasecmp(str, "lq121s1dg31", 11)) {
65660297	428	lpd270_lcd_to_use = &sharp_lq121s1dg31;
2bebf5cb	429	} else if (!strncasecmp(str, "lq036q1da01", 11)) {
65660297	430	lpd270_lcd_to_use = &sharp_lq036q1da01;
2bebf5cb	431	} else if (!strncasecmp(str, "lq64d343", 8)) {
65660297	432	lpd270_lcd_to_use = &sharp_lq64d343;
2bebf5cb	433	} else if (!strncasecmp(str, "lq10d368", 8)) {
65660297	434	lpd270_lcd_to_use = &sharp_lq10d368;
2bebf5cb	435	} else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
65660297 LB	436	lpd270_lcd_to_use = &sharp_lq035q7db02_20;
	437	} else {
	438	printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
	439	}
	440
	441	return 1;
	442	}
	443
	444	__setup("lcd=", lpd270_set_lcd);
	445
e9937d4b LB	446	static struct platform_device *platform_devices[] __initdata = {
e9937d4b LB	447	&smc91x_device,
4a730719	448	&lpd270_backlight_device,
e9937d4b LB	449	&lpd270_flash_device[0],
	450	&lpd270_flash_device[1],
	451	};
	452
e9937d4b LB	453	static struct pxaohci_platform_data lpd270_ohci_platform_data = {
e9937d4b LB	454	.port_mode = PMM_PERPORT_MODE,
097b5334	455	.flags = ENABLE_PORT_ALL \| POWER_CONTROL_LOW \| POWER_SENSE_LOW,
e9937d4b LB	456	};
	457
	458	static void __init lpd270_init(void)
	459	{
fd90ff20 EM	460	pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
fd90ff20 EM	461
cc155c6f RK	462	pxa_set_ffuart_info(NULL);
	463	pxa_set_btuart_info(NULL);
	464	pxa_set_stuart_info(NULL);
	465
ad68bb9f	466	lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
e9937d4b LB	467	lpd270_flash_data[1].width = 4;
	468
	469	/*
	470	* System bus arbiter setting:
	471	* - Core_Park
	472	* - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	473	*/
	474	ARB_CNTRL = ARB_CORE_PARK \| 0x234;
	475
e9937d4b LB	476	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
e9937d4b LB	477
9f19d638 MB	478	pxa_set_ac97_info(NULL);
9f19d638 MB	479
65660297	480	if (lpd270_lcd_to_use != NULL)
4321e1a1	481	pxa_set_fb_info(NULL, lpd270_lcd_to_use);
e9937d4b LB	482
	483	pxa_set_ohci_info(&lpd270_ohci_platform_data);
	484	}
	485
	486
	487	static struct map_desc lpd270_io_desc[] __initdata = {
	488	{
97b09da4	489	.virtual = (unsigned long)LPD270_CPLD_VIRT,
e9937d4b LB	490	.pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
	491	.length = LPD270_CPLD_SIZE,
	492	.type = MT_DEVICE,
	493	},
	494	};
	495
	496	static void __init lpd270_map_io(void)
	497	{
851982c1	498	pxa27x_map_io();
e9937d4b LB	499	iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
e9937d4b LB	500
e9937d4b LB	501	/* for use I SRAM as framebuffer. */
	502	PSLR \|= 0x00000F04;
	503	PCFR = 0x00000066;
	504	}
	505
	506	MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
	507	/* Maintainer: Peter Barada */
7375aba6	508	.atag_offset = 0x100,
e9937d4b	509	.map_io = lpd270_map_io,
6ac6b817	510	.nr_irqs = LPD270_NR_IRQS,
e9937d4b	511	.init_irq = lpd270_init_irq,
8a97ae2f	512	.handle_irq = pxa27x_handle_irq,
6bb27d73	513	.init_time = pxa_timer_init,
e9937d4b	514	.init_machine = lpd270_init,
271a74fc	515	.restart = pxa_restart,
e9937d4b	516	MACHINE_END