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[ARM] 4450/1: pxa: add pxa25x_init_irq() and pxa27x_init_irq()
[deliverable/linux.git] / arch / arm / mach-pxa / lpd270.c
CommitLineData
e9937d4b
LB		 1/*
2 * linux/arch/arm/mach-pxa/lpd270.c
3 *
4 * Support for the LogicPD PXA270 Card Engine.
5 * Derived from the mainstone code, which carries these notices:
6 *
7 * Author: Nicolas Pitre
8 * Created: Nov 05, 2002
9 * Copyright: MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/sysdev.h>
19#include <linux/interrupt.h>
20#include <linux/sched.h>
21#include <linux/bitops.h>
22#include <linux/fb.h>
23#include <linux/ioport.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26
27#include <asm/types.h>
28#include <asm/setup.h>
29#include <asm/memory.h>
30#include <asm/mach-types.h>
31#include <asm/hardware.h>
32#include <asm/irq.h>
33#include <asm/sizes.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38#include <asm/mach/flash.h>
39
40#include <asm/arch/pxa-regs.h>
41#include <asm/arch/lpd270.h>
42#include <asm/arch/audio.h>
43#include <asm/arch/pxafb.h>
44#include <asm/arch/mmc.h>
45#include <asm/arch/irda.h>
46#include <asm/arch/ohci.h>
47
48#include "generic.h"
49
50
51static unsigned int lpd270_irq_enabled;
52
53static void lpd270_mask_irq(unsigned int irq)
54{
55 int lpd270_irq = irq - LPD270_IRQ(0);
56
57 __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
58
59 lpd270_irq_enabled &= ~(1 << lpd270_irq);
60 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
61}
62
63static void lpd270_unmask_irq(unsigned int irq)
64{
65 int lpd270_irq = irq - LPD270_IRQ(0);
66
67 lpd270_irq_enabled |= 1 << lpd270_irq;
68 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
69}
70
38c677cb
DB		 71static struct irq_chip lpd270_irq_chip = {
72 .name = "CPLD",
e9937d4b
LB		 73 .ack = lpd270_mask_irq,
74 .mask = lpd270_mask_irq,
75 .unmask = lpd270_unmask_irq,
76};
77
10dd5ce2 78static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
e9937d4b
LB		 79{
80 unsigned long pending;
81
82 pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
83 do {
84 GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
85 if (likely(pending)) {
86 irq = LPD270_IRQ(0) + __ffs(pending);
87 desc = irq_desc + irq;
0cd61b68 88 desc_handle_irq(irq, desc);
e9937d4b
LB		 89
90 pending = __raw_readw(LPD270_INT_STATUS) &
91 lpd270_irq_enabled;
92 }
93 } while (pending);
94}
95
96static void __init lpd270_init_irq(void)
97{
98 int irq;
99
cd49104d 100 pxa27x_init_irq();
e9937d4b
LB		 101
102 __raw_writew(0, LPD270_INT_MASK);
103 __raw_writew(0, LPD270_INT_STATUS);
104
105 /* setup extra LogicPD PXA270 irqs */
106 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
107 set_irq_chip(irq, &lpd270_irq_chip);
10dd5ce2 108 set_irq_handler(irq, handle_level_irq);
e9937d4b
LB		 109 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
110 }
111 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
112 set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
113}
114
115
116#ifdef CONFIG_PM
117static int lpd270_irq_resume(struct sys_device *dev)
118{
119 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
120 return 0;
121}
122
123static struct sysdev_class lpd270_irq_sysclass = {
124 set_kset_name("cpld_irq"),
125 .resume = lpd270_irq_resume,
126};
127
128static struct sys_device lpd270_irq_device = {
129 .cls = &lpd270_irq_sysclass,
130};
131
132static int __init lpd270_irq_device_init(void)
133{
134 int ret = sysdev_class_register(&lpd270_irq_sysclass);
135 if (ret == 0)
136 ret = sysdev_register(&lpd270_irq_device);
137 return ret;
138}
139
140device_initcall(lpd270_irq_device_init);
141#endif
142
143
144static struct resource smc91x_resources[] = {
145 [0] = {
146 .start = LPD270_ETH_PHYS,
147 .end = (LPD270_ETH_PHYS + 0xfffff),
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = LPD270_ETHERNET_IRQ,
152 .end = LPD270_ETHERNET_IRQ,
153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device smc91x_device = {
158 .name = "smc91x",
159 .id = 0,
160 .num_resources = ARRAY_SIZE(smc91x_resources),
161 .resource = smc91x_resources,
162};
163
164static struct platform_device lpd270_audio_device = {
165 .name = "pxa2xx-ac97",
166 .id = -1,
167};
168
169static struct resource lpd270_flash_resources[] = {
170 [0] = {
171 .start = PXA_CS0_PHYS,
172 .end = PXA_CS0_PHYS + SZ_64M - 1,
173 .flags = IORESOURCE_MEM,
174 },
175 [1] = {
176 .start = PXA_CS1_PHYS,
177 .end = PXA_CS1_PHYS + SZ_64M - 1,
178 .flags = IORESOURCE_MEM,
179 },
180};
181
182static struct mtd_partition lpd270_flash0_partitions[] = {
183 {
184 .name = "Bootloader",
185 .size = 0x00040000,
186 .offset = 0,
187 .mask_flags = MTD_WRITEABLE /* force read-only */
188 }, {
189 .name = "Kernel",
190 .size = 0x00400000,
191 .offset = 0x00040000,
192 }, {
193 .name = "Filesystem",
194 .size = MTDPART_SIZ_FULL,
195 .offset = 0x00440000
196 },
197};
198
199static struct flash_platform_data lpd270_flash_data[2] = {
200 {
201 .name = "processor-flash",
202 .map_name = "cfi_probe",
203 .parts = lpd270_flash0_partitions,
204 .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
205 }, {
206 .name = "mainboard-flash",
207 .map_name = "cfi_probe",
208 .parts = NULL,
209 .nr_parts = 0,
210 }
211};
212
213static struct platform_device lpd270_flash_device[2] = {
214 {
215 .name = "pxa2xx-flash",
216 .id = 0,
217 .dev = {
218 .platform_data = &lpd270_flash_data[0],
219 },
220 .resource = &lpd270_flash_resources[0],
221 .num_resources = 1,
222 }, {
223 .name = "pxa2xx-flash",
224 .id = 1,
225 .dev = {
226 .platform_data = &lpd270_flash_data[1],
227 },
228 .resource = &lpd270_flash_resources[1],
229 .num_resources = 1,
230 },
231};
232
233static void lpd270_backlight_power(int on)
234{
235 if (on) {
236 pxa_gpio_mode(GPIO16_PWM0_MD);
7053acbd 237 pxa_set_cken(CKEN_PWM0, 1);
e9937d4b
LB		 238 PWM_CTRL0 = 0;
239 PWM_PWDUTY0 = 0x3ff;
240 PWM_PERVAL0 = 0x3ff;
241 } else {
242 PWM_CTRL0 = 0;
243 PWM_PWDUTY0 = 0x0;
244 PWM_PERVAL0 = 0x3FF;
7053acbd 245 pxa_set_cken(CKEN_PWM0, 0);
e9937d4b
LB		 246 }
247}
248
249/* 5.7" TFT QVGA (LoLo display number 1) */
d14b272b 250static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
65660297
LB		 251 .pixclock = 150000,
252 .xres = 320,
253 .yres = 240,
e9937d4b 254 .bpp = 16,
65660297
LB		 255 .hsync_len = 0x14,
256 .left_margin = 0x28,
257 .right_margin = 0x0a,
258 .vsync_len = 0x02,
e9937d4b
LB		 259 .upper_margin = 0x08,
260 .lower_margin = 0x14,
65660297 261 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
d14b272b
RP		 262};
263
264static struct pxafb_mach_info sharp_lq057q3dc02 = {
265 .modes = &sharp_lq057q3dc02_mode,
266 .num_modes = 1,
e9937d4b 267 .lccr0 = 0x07800080,
65660297
LB		 268 .lccr3 = 0x00400000,
269 .pxafb_backlight_power = lpd270_backlight_power,
270};
271
272/* 12.1" TFT SVGA (LoLo display number 2) */
d14b272b 273static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
65660297
LB		 274 .pixclock = 50000,
275 .xres = 800,
276 .yres = 600,
277 .bpp = 16,
278 .hsync_len = 0x05,
279 .left_margin = 0x52,
280 .right_margin = 0x05,
281 .vsync_len = 0x04,
282 .upper_margin = 0x14,
283 .lower_margin = 0x0a,
284 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
d14b272b
RP		 285};
286
287static struct pxafb_mach_info sharp_lq121s1dg31 = {
288 .modes = &sharp_lq121s1dg31_mode,
289 .num_modes = 1,
65660297
LB		 290 .lccr0 = 0x07800080,
291 .lccr3 = 0x00400000,
292 .pxafb_backlight_power = lpd270_backlight_power,
293};
294
295/* 3.6" TFT QVGA (LoLo display number 3) */
d14b272b 296static struct pxafb_mode_info sharp_lq036q1da01_mode = {
65660297
LB		 297 .pixclock = 150000,
298 .xres = 320,
299 .yres = 240,
300 .bpp = 16,
301 .hsync_len = 0x0e,
302 .left_margin = 0x04,
303 .right_margin = 0x0a,
304 .vsync_len = 0x03,
305 .upper_margin = 0x03,
306 .lower_margin = 0x03,
307 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
d14b272b
RP		 308};
309
310static struct pxafb_mach_info sharp_lq036q1da01 = {
311 .modes = &sharp_lq036q1da01_mode,
312 .num_modes = 1,
65660297
LB		 313 .lccr0 = 0x07800080,
314 .lccr3 = 0x00400000,
e9937d4b
LB		 315 .pxafb_backlight_power = lpd270_backlight_power,
316};
317
318/* 6.4" TFT VGA (LoLo display number 5) */
d14b272b 319static struct pxafb_mode_info sharp_lq64d343_mode = {
65660297 320 .pixclock = 25000,
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LB		 321 .xres = 640,
322 .yres = 480,
323 .bpp = 16,
65660297 324 .hsync_len = 0x31,
e9937d4b
LB		 325 .left_margin = 0x89,
326 .right_margin = 0x19,
65660297 327 .vsync_len = 0x12,
e9937d4b 328 .upper_margin = 0x22,
65660297 329 .lower_margin = 0x00,
e9937d4b 330 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
d14b272b
RP		 331};
332
333static struct pxafb_mach_info sharp_lq64d343 = {
334 .modes = &sharp_lq64d343_mode,
335 .num_modes = 1,
e9937d4b 336 .lccr0 = 0x07800080,
65660297
LB		 337 .lccr3 = 0x00400000,
338 .pxafb_backlight_power = lpd270_backlight_power,
339};
340
341/* 10.4" TFT VGA (LoLo display number 7) */
d14b272b 342static struct pxafb_mode_info sharp_lq10d368_mode = {
65660297
LB		 343 .pixclock = 25000,
344 .xres = 640,
345 .yres = 480,
346 .bpp = 16,
347 .hsync_len = 0x31,
348 .left_margin = 0x89,
349 .right_margin = 0x19,
350 .vsync_len = 0x12,
351 .upper_margin = 0x22,
352 .lower_margin = 0x00,
353 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
d14b272b
RP		 354};
355
356static struct pxafb_mach_info sharp_lq10d368 = {
357 .modes = &sharp_lq10d368_mode,
358 .num_modes = 1,
65660297
LB		 359 .lccr0 = 0x07800080,
360 .lccr3 = 0x00400000,
e9937d4b
LB		 361 .pxafb_backlight_power = lpd270_backlight_power,
362};
363
364/* 3.5" TFT QVGA (LoLo display number 8) */
d14b272b 365static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
65660297 366 .pixclock = 150000,
e9937d4b
LB		 367 .xres = 240,
368 .yres = 320,
369 .bpp = 16,
65660297
LB		 370 .hsync_len = 0x0e,
371 .left_margin = 0x0a,
372 .right_margin = 0x0a,
373 .vsync_len = 0x03,
e9937d4b
LB		 374 .upper_margin = 0x05,
375 .lower_margin = 0x14,
65660297 376 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
d14b272b
RP		 377};
378
379static struct pxafb_mach_info sharp_lq035q7db02_20 = {
380 .modes = &sharp_lq035q7db02_20_mode,
381 .num_modes = 1,
e9937d4b 382 .lccr0 = 0x07800080,
65660297 383 .lccr3 = 0x00400000,
e9937d4b
LB		 384 .pxafb_backlight_power = lpd270_backlight_power,
385};
386
65660297
LB		 387static struct pxafb_mach_info *lpd270_lcd_to_use;
388
389static int __init lpd270_set_lcd(char *str)
390{
391 if (!strnicmp(str, "lq057q3dc02", 11)) {
392 lpd270_lcd_to_use = &sharp_lq057q3dc02;
393 } else if (!strnicmp(str, "lq121s1dg31", 11)) {
394 lpd270_lcd_to_use = &sharp_lq121s1dg31;
395 } else if (!strnicmp(str, "lq036q1da01", 11)) {
396 lpd270_lcd_to_use = &sharp_lq036q1da01;
397 } else if (!strnicmp(str, "lq64d343", 8)) {
398 lpd270_lcd_to_use = &sharp_lq64d343;
399 } else if (!strnicmp(str, "lq10d368", 8)) {
400 lpd270_lcd_to_use = &sharp_lq10d368;
401 } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
402 lpd270_lcd_to_use = &sharp_lq035q7db02_20;
403 } else {
404 printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
405 }
406
407 return 1;
408}
409
410__setup("lcd=", lpd270_set_lcd);
411
e9937d4b
LB		 412static struct platform_device *platform_devices[] __initdata = {
413 &smc91x_device,
414 &lpd270_audio_device,
415 &lpd270_flash_device[0],
416 &lpd270_flash_device[1],
417};
418
419static int lpd270_ohci_init(struct device *dev)
420{
421 /* setup Port1 GPIO pin. */
422 pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
423 pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
424
425 /* Set the Power Control Polarity Low and Power Sense
426 Polarity Low to active low. */
427 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
428 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
429
430 return 0;
431}
432
433static struct pxaohci_platform_data lpd270_ohci_platform_data = {
434 .port_mode = PMM_PERPORT_MODE,
435 .init = lpd270_ohci_init,
436};
437
438static void __init lpd270_init(void)
439{
440 lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
441 lpd270_flash_data[1].width = 4;
442
443 /*
444 * System bus arbiter setting:
445 * - Core_Park
446 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
447 */
448 ARB_CNTRL = ARB_CORE_PARK | 0x234;
449
450 /*
451 * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
452 */
453 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
454
455 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
456
65660297
LB		 457 if (lpd270_lcd_to_use != NULL)
458 set_pxa_fb_info(lpd270_lcd_to_use);
e9937d4b
LB		 459
460 pxa_set_ohci_info(&lpd270_ohci_platform_data);
461}
462
463
464static struct map_desc lpd270_io_desc[] __initdata = {
465 {
466 .virtual = LPD270_CPLD_VIRT,
467 .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
468 .length = LPD270_CPLD_SIZE,
469 .type = MT_DEVICE,
470 },
471};
472
473static void __init lpd270_map_io(void)
474{
475 pxa_map_io();
476 iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
477
478 /* initialize sleep mode regs (wake-up sources, etc) */
479 PGSR0 = 0x00008800;
480 PGSR1 = 0x00000002;
481 PGSR2 = 0x0001FC00;
482 PGSR3 = 0x00001F81;
483 PWER = 0xC0000002;
484 PRER = 0x00000002;
485 PFER = 0x00000002;
486
487 /* for use I SRAM as framebuffer. */
488 PSLR |= 0x00000F04;
489 PCFR = 0x00000066;
490}
491
492MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
493 /* Maintainer: Peter Barada */
494 .phys_io = 0x40000000,
495 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
496 .boot_params = 0xa0000100,
497 .map_io = lpd270_map_io,
498 .init_irq = lpd270_init_irq,
499 .timer = &pxa_timer,
500 .init_machine = lpd270_init,
501MACHINE_END
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