[deliverable/linux.git] / arch / arm / mach-pxa / mainstone.c

/*
 *  linux/arch/arm/mach-pxa/mainstone.c
 *
 *  Support for the Intel HCDDBBVA0 Development Platform.
 *  (go figure how they came up with such name...)
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/backlight.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>

#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/mainstone.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/ohci.h>

#include "generic.h"
#include "devices.h"

static unsigned long mainstone_pin_config[] = {
	/* Chip Select */
	GPIO15_nCS_1,

	/* LCD - 16bpp Active TFT */
	GPIO58_LCD_LDD_0,
	GPIO59_LCD_LDD_1,
	GPIO60_LCD_LDD_2,
	GPIO61_LCD_LDD_3,
	GPIO62_LCD_LDD_4,
	GPIO63_LCD_LDD_5,
	GPIO64_LCD_LDD_6,
	GPIO65_LCD_LDD_7,
	GPIO66_LCD_LDD_8,
	GPIO67_LCD_LDD_9,
	GPIO68_LCD_LDD_10,
	GPIO69_LCD_LDD_11,
	GPIO70_LCD_LDD_12,
	GPIO71_LCD_LDD_13,
	GPIO72_LCD_LDD_14,
	GPIO73_LCD_LDD_15,
	GPIO74_LCD_FCLK,
	GPIO75_LCD_LCLK,
	GPIO76_LCD_PCLK,
	GPIO77_LCD_BIAS,
	GPIO16_PWM0_OUT,	/* Backlight */

	/* MMC */
	GPIO32_MMC_CLK,
	GPIO112_MMC_CMD,
	GPIO92_MMC_DAT_0,
	GPIO109_MMC_DAT_1,
	GPIO110_MMC_DAT_2,
	GPIO111_MMC_DAT_3,

	/* USB Host Port 1 */
	GPIO88_USBH1_PWR,
	GPIO89_USBH1_PEN,

	/* PC Card */
	GPIO48_nPOE,
	GPIO49_nPWE,
	GPIO50_nPIOR,
	GPIO51_nPIOW,
	GPIO85_nPCE_1,
	GPIO54_nPCE_2,
	GPIO79_PSKTSEL,
	GPIO55_nPREG,
	GPIO56_nPWAIT,
	GPIO57_nIOIS16,

	/* AC97 */
	GPIO45_AC97_SYSCLK,

	/* Keypad */
	GPIO93_KP_DKIN_0	| WAKEUP_ON_LEVEL_HIGH,
	GPIO94_KP_DKIN_1	| WAKEUP_ON_LEVEL_HIGH,
	GPIO95_KP_DKIN_2	| WAKEUP_ON_LEVEL_HIGH,
	GPIO100_KP_MKIN_0	| WAKEUP_ON_LEVEL_HIGH,
	GPIO101_KP_MKIN_1	| WAKEUP_ON_LEVEL_HIGH,
	GPIO102_KP_MKIN_2	| WAKEUP_ON_LEVEL_HIGH,
	GPIO97_KP_MKIN_3	| WAKEUP_ON_LEVEL_HIGH,
	GPIO98_KP_MKIN_4	| WAKEUP_ON_LEVEL_HIGH,
	GPIO99_KP_MKIN_5	| WAKEUP_ON_LEVEL_HIGH,
	GPIO103_KP_MKOUT_0,
	GPIO104_KP_MKOUT_1,
	GPIO105_KP_MKOUT_2,
	GPIO106_KP_MKOUT_3,
	GPIO107_KP_MKOUT_4,
	GPIO108_KP_MKOUT_5,
	GPIO96_KP_MKOUT_6,

	/* GPIO */
	GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
};

static unsigned long mainstone_irq_enabled;

static void mainstone_mask_irq(unsigned int irq)
{
	int mainstone_irq = (irq - MAINSTONE_IRQ(0));
	MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
}

static void mainstone_unmask_irq(unsigned int irq)
{
	int mainstone_irq = (irq - MAINSTONE_IRQ(0));
	/* the irq can be acknowledged only if deasserted, so it's done here */
	MST_INTSETCLR &= ~(1 << mainstone_irq);
	MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
}

static struct irq_chip mainstone_irq_chip = {
	.name		= "FPGA",
	.ack		= mainstone_mask_irq,
	.mask		= mainstone_mask_irq,
	.unmask		= mainstone_unmask_irq,
};

static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
	do {
		GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
		if (likely(pending)) {
			irq = MAINSTONE_IRQ(0) + __ffs(pending);
			desc = irq_desc + irq;
			desc_handle_irq(irq, desc);
		}
		pending = MST_INTSETCLR & mainstone_irq_enabled;
	} while (pending);
}

static void __init mainstone_init_irq(void)
{
	int irq;

	pxa27x_init_irq();

	/* setup extra Mainstone irqs */
	for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
		set_irq_chip(irq, &mainstone_irq_chip);
		set_irq_handler(irq, handle_level_irq);
		if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
		else
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}
	set_irq_flags(MAINSTONE_IRQ(8), 0);
	set_irq_flags(MAINSTONE_IRQ(12), 0);

	MST_INTMSKENA = 0;
	MST_INTSETCLR = 0;

	set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
	set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
}

#ifdef CONFIG_PM

static int mainstone_irq_resume(struct sys_device *dev)
{
	MST_INTMSKENA = mainstone_irq_enabled;
	return 0;
}

static struct sysdev_class mainstone_irq_sysclass = {
	.name = "cpld_irq",
	.resume = mainstone_irq_resume,
};

static struct sys_device mainstone_irq_device = {
	.cls = &mainstone_irq_sysclass,
};

static int __init mainstone_irq_device_init(void)
{
	int ret = -ENODEV;

	if (machine_is_mainstone()) {
		ret = sysdev_class_register(&mainstone_irq_sysclass);
		if (ret == 0)
			ret = sysdev_register(&mainstone_irq_device);
	}
	return ret;
}

device_initcall(mainstone_irq_device_init);

#endif


static struct resource smc91x_resources[] = {
	[0] = {
		.start	= (MST_ETH_PHYS + 0x300),
		.end	= (MST_ETH_PHYS + 0xfffff),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= MAINSTONE_IRQ(3),
		.end	= MAINSTONE_IRQ(3),
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	}
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
	return 0;
}

static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
}

static long mst_audio_suspend_mask;

static void mst_audio_suspend(void *priv)
{
	mst_audio_suspend_mask = MST_MSCWR2;
	MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
}

static void mst_audio_resume(void *priv)
{
	MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
}

static pxa2xx_audio_ops_t mst_audio_ops = {
	.startup	= mst_audio_startup,
	.shutdown	= mst_audio_shutdown,
	.suspend	= mst_audio_suspend,
	.resume		= mst_audio_resume,
};

static struct platform_device mst_audio_device = {
	.name		= "pxa2xx-ac97",
	.id		= -1,
	.dev		= { .platform_data = &mst_audio_ops },
};

static struct resource flash_resources[] = {
	[0] = {
		.start	= PXA_CS0_PHYS,
		.end	= PXA_CS0_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= PXA_CS1_PHYS,
		.end	= PXA_CS1_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct mtd_partition mainstoneflash0_partitions[] = {
	{
		.name =		"Bootloader",
		.size =		0x00040000,
		.offset =	0,
		.mask_flags =	MTD_WRITEABLE  /* force read-only */
	},{
		.name =		"Kernel",
		.size =		0x00400000,
		.offset =	0x00040000,
	},{
		.name =		"Filesystem",
		.size =		MTDPART_SIZ_FULL,
		.offset =	0x00440000
	}
};

static struct flash_platform_data mst_flash_data[2] = {
	{
		.map_name	= "cfi_probe",
		.parts		= mainstoneflash0_partitions,
		.nr_parts	= ARRAY_SIZE(mainstoneflash0_partitions),
	}, {
		.map_name	= "cfi_probe",
		.parts		= NULL,
		.nr_parts	= 0,
	}
};

static struct platform_device mst_flash_device[2] = {
	{
		.name		= "pxa2xx-flash",
		.id		= 0,
		.dev = {
			.platform_data = &mst_flash_data[0],
		},
		.resource = &flash_resources[0],
		.num_resources = 1,
	},
	{
		.name		= "pxa2xx-flash",
		.id		= 1,
		.dev = {
			.platform_data = &mst_flash_data[1],
		},
		.resource = &flash_resources[1],
		.num_resources = 1,
	},
};

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
static int mainstone_backlight_update_status(struct backlight_device *bl)
{
	int brightness = bl->props.brightness;

	if (bl->props.power != FB_BLANK_UNBLANK ||
	    bl->props.fb_blank != FB_BLANK_UNBLANK)
		brightness = 0;

	if (brightness != 0)
		pxa_set_cken(CKEN_PWM0, 1);

	PWM_CTRL0 = 0;
	PWM_PWDUTY0 = brightness;
	PWM_PERVAL0 = bl->props.max_brightness;

	if (brightness == 0)
		pxa_set_cken(CKEN_PWM0, 0);
	return 0; /* pointless return value */
}

static int mainstone_backlight_get_brightness(struct backlight_device *bl)
{
	return PWM_PWDUTY0;
}

static /*const*/ struct backlight_ops mainstone_backlight_ops = {
	.update_status	= mainstone_backlight_update_status,
	.get_brightness	= mainstone_backlight_get_brightness,
};

static void __init mainstone_backlight_register(void)
{
	struct backlight_device *bl;

	bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev,
				       NULL, &mainstone_backlight_ops);
	if (IS_ERR(bl)) {
		printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
		       PTR_ERR(bl));
		return;
	}

	/*
	 * broken design - register-then-setup interfaces are
	 * utterly broken by definition.
	 */
	bl->props.max_brightness = 1023;
	bl->props.brightness = 1023;
	backlight_update_status(bl);
}
#else
#define mainstone_backlight_register()	do { } while (0)
#endif

static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
	.pixclock		= 50000,
	.xres			= 640,
	.yres			= 480,
	.bpp			= 16,
	.hsync_len		= 1,
	.left_margin		= 0x9f,
	.right_margin		= 1,
	.vsync_len		= 44,
	.upper_margin		= 0,
	.lower_margin		= 0,
	.sync			= FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
	.pixclock		= 110000,
	.xres			= 240,
	.yres			= 320,
	.bpp			= 16,
	.hsync_len		= 4,
	.left_margin		= 8,
	.right_margin		= 20,
	.vsync_len		= 3,
	.upper_margin		= 1,
	.lower_margin		= 10,
	.sync			= FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info mainstone_pxafb_info = {
	.num_modes      	= 1,
	.lccr0			= LCCR0_Act,
	.lccr3			= LCCR3_PCP,
};

static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
{
	int err;

	/* make sure SD/Memory Stick multiplexer's signals
	 * are routed to MMC controller
	 */
	MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;

	err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
			     "MMC card detect", data);
	if (err)
		printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");

	return err;
}

static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
{
	struct pxamci_platform_data* p_d = dev->platform_data;

	if (( 1 << vdd) & p_d->ocr_mask) {
		printk(KERN_DEBUG "%s: on\n", __func__);
		MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
		MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
	} else {
		printk(KERN_DEBUG "%s: off\n", __func__);
		MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
	}
}

static void mainstone_mci_exit(struct device *dev, void *data)
{
	free_irq(MAINSTONE_MMC_IRQ, data);
}

static struct pxamci_platform_data mainstone_mci_platform_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.init 		= mainstone_mci_init,
	.setpower 	= mainstone_mci_setpower,
	.exit		= mainstone_mci_exit,
};

static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
{
	unsigned long flags;

	local_irq_save(flags);
	if (mode & IR_SIRMODE) {
		MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
	} else if (mode & IR_FIRMODE) {
		MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
	}
	if (mode & IR_OFF) {
		MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
	} else {
		MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
	}
	local_irq_restore(flags);
}

static struct pxaficp_platform_data mainstone_ficp_platform_data = {
	.transceiver_cap  = IR_SIRMODE | IR_FIRMODE | IR_OFF,
	.transceiver_mode = mainstone_irda_transceiver_mode,
};

static struct gpio_keys_button gpio_keys_button[] = {
	[0] = {
		.desc	= "wakeup",
		.code	= KEY_SUSPEND,
		.type	= EV_KEY,
		.gpio	= 1,
		.wakeup	= 1,
	},
};

static struct gpio_keys_platform_data mainstone_gpio_keys = {
	.buttons	= gpio_keys_button,
	.nbuttons	= 1,
};

static struct platform_device mst_gpio_keys_device = {
	.name		= "gpio-keys",
	.id		= -1,
	.dev		= {
		.platform_data	= &mainstone_gpio_keys,
	},
};

static struct platform_device *platform_devices[] __initdata = {
	&smc91x_device,
	&mst_audio_device,
	&mst_flash_device[0],
	&mst_flash_device[1],
	&mst_gpio_keys_device,
};

static int mainstone_ohci_init(struct device *dev)
{
	/* Set the Power Control Polarity Low and Power Sense
	   Polarity Low to active low. */
	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
		~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);

	return 0;
}

static struct pxaohci_platform_data mainstone_ohci_platform_data = {
	.port_mode	= PMM_PERPORT_MODE,
	.init		= mainstone_ohci_init,
};

static void __init mainstone_init(void)
{
	int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */

	pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));

	mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
	mst_flash_data[1].width = 4;

	/* Compensate for SW7 which swaps the flash banks */
	mst_flash_data[SW7].name = "processor-flash";
	mst_flash_data[SW7 ^ 1].name = "mainboard-flash";

	printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
	       mst_flash_data[0].name);

	/* system bus arbiter setting
	 * - Core_Park
	 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	 */
	ARB_CNTRL = ARB_CORE_PARK | 0x234;

	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

	/* reading Mainstone's "Virtual Configuration Register"
	   might be handy to select LCD type here */
	if (0)
		mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
	else
		mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;

	set_pxa_fb_info(&mainstone_pxafb_info);
	mainstone_backlight_register();

	pxa_set_mci_info(&mainstone_mci_platform_data);
	pxa_set_ficp_info(&mainstone_ficp_platform_data);
	pxa_set_ohci_info(&mainstone_ohci_platform_data);
}


static struct map_desc mainstone_io_desc[] __initdata = {
  	{	/* CPLD */
		.virtual	=  MST_FPGA_VIRT,
		.pfn		= __phys_to_pfn(MST_FPGA_PHYS),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}
};

static void __init mainstone_map_io(void)
{
	pxa_map_io();
	iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));

 	/*	for use I SRAM as framebuffer.	*/
 	PSLR |= 0xF04;
 	PCFR = 0x66;
}

MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
	/* Maintainer: MontaVista Software Inc. */
	.phys_io	= 0x40000000,
	.boot_params	= 0xa0000100,	/* BLOB boot parameter setting */
	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
	.map_io		= mainstone_map_io,
	.init_irq	= mainstone_init_irq,
	.timer		= &pxa_timer,
	.init_machine	= mainstone_init,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/mainstone.c
	3	*
	4	* Support for the Intel HCDDBBVA0 Development Platform.
	5	* (go figure how they came up with such name...)
	6	*
	7	* Author: Nicolas Pitre
	8	* Created: Nov 05, 2002
	9	* Copyright: MontaVista Software Inc.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
d052d1be	17	#include <linux/platform_device.h>
22f11c4e	18	#include <linux/sysdev.h>
1da177e4 LT	19	#include <linux/interrupt.h>
	20	#include <linux/sched.h>
	21	#include <linux/bitops.h>
	22	#include <linux/fb.h>
74ec71e1 TP	23	#include <linux/ioport.h>
	24	#include <linux/mtd/mtd.h>
	25	#include <linux/mtd/partitions.h>
3777f774	26	#include <linux/backlight.h>
450d2874	27	#include <linux/input.h>
450d2874	28	#include <linux/gpio_keys.h>
1da177e4 LT	29
	30	#include <asm/types.h>
	31	#include <asm/setup.h>
	32	#include <asm/memory.h>
	33	#include <asm/mach-types.h>
	34	#include <asm/hardware.h>
	35	#include <asm/irq.h>
74ec71e1	36	#include <asm/sizes.h>
1da177e4 LT	37
	38	#include <asm/mach/arch.h>
	39	#include <asm/mach/map.h>
	40	#include <asm/mach/irq.h>
74ec71e1	41	#include <asm/mach/flash.h>
1da177e4 LT	42
1da177e4 LT	43	#include <asm/arch/pxa-regs.h>
8785a8fb	44	#include <asm/arch/pxa2xx-regs.h>
fef06d27	45	#include <asm/arch/mfp-pxa27x.h>
1da177e4 LT	46	#include <asm/arch/mainstone.h>
	47	#include <asm/arch/audio.h>
	48	#include <asm/arch/pxafb.h>
	49	#include <asm/arch/mmc.h>
6f475c01	50	#include <asm/arch/irda.h>
81f280e2	51	#include <asm/arch/ohci.h>
1da177e4 LT	52
1da177e4 LT	53	#include "generic.h"
46c41e62	54	#include "devices.h"
1da177e4	55
fef06d27	56	static unsigned long mainstone_pin_config[] = {
	57	/* Chip Select */
	58	GPIO15_nCS_1,
	59
	60	/* LCD - 16bpp Active TFT */
	61	GPIO58_LCD_LDD_0,
	62	GPIO59_LCD_LDD_1,
	63	GPIO60_LCD_LDD_2,
	64	GPIO61_LCD_LDD_3,
	65	GPIO62_LCD_LDD_4,
	66	GPIO63_LCD_LDD_5,
	67	GPIO64_LCD_LDD_6,
	68	GPIO65_LCD_LDD_7,
	69	GPIO66_LCD_LDD_8,
	70	GPIO67_LCD_LDD_9,
	71	GPIO68_LCD_LDD_10,
	72	GPIO69_LCD_LDD_11,
	73	GPIO70_LCD_LDD_12,
	74	GPIO71_LCD_LDD_13,
	75	GPIO72_LCD_LDD_14,
	76	GPIO73_LCD_LDD_15,
	77	GPIO74_LCD_FCLK,
	78	GPIO75_LCD_LCLK,
	79	GPIO76_LCD_PCLK,
	80	GPIO77_LCD_BIAS,
	81	GPIO16_PWM0_OUT, /* Backlight */
	82
	83	/* MMC */
	84	GPIO32_MMC_CLK,
	85	GPIO112_MMC_CMD,
	86	GPIO92_MMC_DAT_0,
	87	GPIO109_MMC_DAT_1,
	88	GPIO110_MMC_DAT_2,
	89	GPIO111_MMC_DAT_3,
	90
	91	/* USB Host Port 1 */
	92	GPIO88_USBH1_PWR,
	93	GPIO89_USBH1_PEN,
	94
	95	/* PC Card */
	96	GPIO48_nPOE,
	97	GPIO49_nPWE,
	98	GPIO50_nPIOR,
	99	GPIO51_nPIOW,
	100	GPIO85_nPCE_1,
	101	GPIO54_nPCE_2,
	102	GPIO79_PSKTSEL,
	103	GPIO55_nPREG,
	104	GPIO56_nPWAIT,
	105	GPIO57_nIOIS16,
	106
	107	/* AC97 */
	108	GPIO45_AC97_SYSCLK,
	109
	110	/* Keypad */
	111	GPIO93_KP_DKIN_0 \| WAKEUP_ON_LEVEL_HIGH,
	112	GPIO94_KP_DKIN_1 \| WAKEUP_ON_LEVEL_HIGH,
	113	GPIO95_KP_DKIN_2 \| WAKEUP_ON_LEVEL_HIGH,
	114	GPIO100_KP_MKIN_0 \| WAKEUP_ON_LEVEL_HIGH,
	115	GPIO101_KP_MKIN_1 \| WAKEUP_ON_LEVEL_HIGH,
	116	GPIO102_KP_MKIN_2 \| WAKEUP_ON_LEVEL_HIGH,
	117	GPIO97_KP_MKIN_3 \| WAKEUP_ON_LEVEL_HIGH,
	118	GPIO98_KP_MKIN_4 \| WAKEUP_ON_LEVEL_HIGH,
	119	GPIO99_KP_MKIN_5 \| WAKEUP_ON_LEVEL_HIGH,
120	GPIO103_KP_MKOUT_0,
121	GPIO104_KP_MKOUT_1,
122	GPIO105_KP_MKOUT_2,
123	GPIO106_KP_MKOUT_3,
124	GPIO107_KP_MKOUT_4,
125	GPIO108_KP_MKOUT_5,
126	GPIO96_KP_MKOUT_6,
127
128	/* GPIO */
129	GPIO1_GPIO \| WAKEUP_ON_EDGE_BOTH,
130	};
1da177e4 LT	131
	132	static unsigned long mainstone_irq_enabled;
	133
	134	static void mainstone_mask_irq(unsigned int irq)
	135	{
	136	int mainstone_irq = (irq - MAINSTONE_IRQ(0));
	137	MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
	138	}
	139
	140	static void mainstone_unmask_irq(unsigned int irq)
	141	{
	142	int mainstone_irq = (irq - MAINSTONE_IRQ(0));
	143	/* the irq can be acknowledged only if deasserted, so it's done here */
	144	MST_INTSETCLR &= ~(1 << mainstone_irq);
	145	MST_INTMSKENA = (mainstone_irq_enabled \|= (1 << mainstone_irq));
	146	}
	147
38c677cb DB	148	static struct irq_chip mainstone_irq_chip = {
38c677cb DB	149	.name = "FPGA",
1da177e4 LT	150	.ack = mainstone_mask_irq,
	151	.mask = mainstone_mask_irq,
	152	.unmask = mainstone_unmask_irq,
	153	};
	154
10dd5ce2	155	static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	156	{
	157	unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
	158	do {
	159	GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
	160	if (likely(pending)) {
	161	irq = MAINSTONE_IRQ(0) + __ffs(pending);
	162	desc = irq_desc + irq;
0cd61b68	163	desc_handle_irq(irq, desc);
1da177e4 LT	164	}
	165	pending = MST_INTSETCLR & mainstone_irq_enabled;
	166	} while (pending);
	167	}
	168
	169	static void __init mainstone_init_irq(void)
	170	{
	171	int irq;
	172
cd49104d	173	pxa27x_init_irq();
1da177e4 LT	174
	175	/* setup extra Mainstone irqs */
	176	for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
	177	set_irq_chip(irq, &mainstone_irq_chip);
10dd5ce2	178	set_irq_handler(irq, handle_level_irq);
ec64152f TG	179	if (irq == MAINSTONE_IRQ(10) \|\| irq == MAINSTONE_IRQ(14))
	180	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE \| IRQF_NOAUTOEN);
	181	else
	182	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
1da177e4 LT	183	}
	184	set_irq_flags(MAINSTONE_IRQ(8), 0);
	185	set_irq_flags(MAINSTONE_IRQ(12), 0);
	186
	187	MST_INTMSKENA = 0;
	188	MST_INTSETCLR = 0;
	189
	190	set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
	191	set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
	192	}
	193
22f11c4e NP	194	#ifdef CONFIG_PM
	195
	196	static int mainstone_irq_resume(struct sys_device *dev)
	197	{
	198	MST_INTMSKENA = mainstone_irq_enabled;
	199	return 0;
	200	}
	201
	202	static struct sysdev_class mainstone_irq_sysclass = {
af5ca3f4	203	.name = "cpld_irq",
22f11c4e NP	204	.resume = mainstone_irq_resume,
	205	};
	206
	207	static struct sys_device mainstone_irq_device = {
	208	.cls = &mainstone_irq_sysclass,
	209	};
	210
	211	static int __init mainstone_irq_device_init(void)
	212	{
16f159b1 RK	213	int ret = -ENODEV;
	214
	215	if (machine_is_mainstone()) {
	216	ret = sysdev_class_register(&mainstone_irq_sysclass);
	217	if (ret == 0)
	218	ret = sysdev_register(&mainstone_irq_device);
	219	}
22f11c4e NP	220	return ret;
	221	}
	222
	223	device_initcall(mainstone_irq_device_init);
	224
	225	#endif
	226
1da177e4 LT	227
	228	static struct resource smc91x_resources[] = {
	229	[0] = {
	230	.start = (MST_ETH_PHYS + 0x300),
	231	.end = (MST_ETH_PHYS + 0xfffff),
	232	.flags = IORESOURCE_MEM,
	233	},
	234	[1] = {
	235	.start = MAINSTONE_IRQ(3),
	236	.end = MAINSTONE_IRQ(3),
e7b3dc7e	237	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
1da177e4 LT	238	}
	239	};
	240
	241	static struct platform_device smc91x_device = {
	242	.name = "smc91x",
	243	.id = 0,
	244	.num_resources = ARRAY_SIZE(smc91x_resources),
	245	.resource = smc91x_resources,
	246	};
	247
f7cbb7fc	248	static int mst_audio_startup(struct snd_pcm_substream substream, void priv)
1da177e4 LT	249	{
	250	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	251	MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
	252	return 0;
	253	}
	254
f7cbb7fc	255	static void mst_audio_shutdown(struct snd_pcm_substream substream, void priv)
1da177e4 LT	256	{
	257	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	258	MST_MSCWR2 \|= MST_MSCWR2_AC97_SPKROFF;
	259	}
	260
	261	static long mst_audio_suspend_mask;
	262
	263	static void mst_audio_suspend(void *priv)
	264	{
	265	mst_audio_suspend_mask = MST_MSCWR2;
	266	MST_MSCWR2 \|= MST_MSCWR2_AC97_SPKROFF;
	267	}
	268
	269	static void mst_audio_resume(void *priv)
	270	{
	271	MST_MSCWR2 &= mst_audio_suspend_mask \| ~MST_MSCWR2_AC97_SPKROFF;
	272	}
	273
	274	static pxa2xx_audio_ops_t mst_audio_ops = {
	275	.startup = mst_audio_startup,
	276	.shutdown = mst_audio_shutdown,
	277	.suspend = mst_audio_suspend,
	278	.resume = mst_audio_resume,
	279	};
	280
	281	static struct platform_device mst_audio_device = {
	282	.name = "pxa2xx-ac97",
	283	.id = -1,
	284	.dev = { .platform_data = &mst_audio_ops },
	285	};
	286
74ec71e1 TP	287	static struct resource flash_resources[] = {
	288	[0] = {
	289	.start = PXA_CS0_PHYS,
	290	.end = PXA_CS0_PHYS + SZ_64M - 1,
	291	.flags = IORESOURCE_MEM,
	292	},
	293	[1] = {
	294	.start = PXA_CS1_PHYS,
	295	.end = PXA_CS1_PHYS + SZ_64M - 1,
	296	.flags = IORESOURCE_MEM,
	297	},
	298	};
	299
	300	static struct mtd_partition mainstoneflash0_partitions[] = {
	301	{
	302	.name = "Bootloader",
	303	.size = 0x00040000,
	304	.offset = 0,
	305	.mask_flags = MTD_WRITEABLE /* force read-only */
	306	},{
	307	.name = "Kernel",
	308	.size = 0x00400000,
	309	.offset = 0x00040000,
	310	},{
	311	.name = "Filesystem",
	312	.size = MTDPART_SIZ_FULL,
	313	.offset = 0x00440000
	314	}
	315	};
	316
	317	static struct flash_platform_data mst_flash_data[2] = {
	318	{
	319	.map_name = "cfi_probe",
	320	.parts = mainstoneflash0_partitions,
	321	.nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
	322	}, {
	323	.map_name = "cfi_probe",
	324	.parts = NULL,
	325	.nr_parts = 0,
	326	}
	327	};
	328
	329	static struct platform_device mst_flash_device[2] = {
	330	{
	331	.name = "pxa2xx-flash",
	332	.id = 0,
	333	.dev = {
	334	.platform_data = &mst_flash_data[0],
	335	},
	336	.resource = &flash_resources[0],
	337	.num_resources = 1,
	338	},
	339	{
	340	.name = "pxa2xx-flash",
	341	.id = 1,
	342	.dev = {
	343	.platform_data = &mst_flash_data[1],
	344	},
	345	.resource = &flash_resources[1],
	346	.num_resources = 1,
	347	},
	348	};
	349
3777f774 RK	350	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
3777f774 RK	351	static int mainstone_backlight_update_status(struct backlight_device *bl)
1da177e4	352	{
3777f774 RK	353	int brightness = bl->props.brightness;
	354
	355	if (bl->props.power != FB_BLANK_UNBLANK \|\|
	356	bl->props.fb_blank != FB_BLANK_UNBLANK)
	357	brightness = 0;
	358
fef06d27	359	if (brightness != 0)
7053acbd	360	pxa_set_cken(CKEN_PWM0, 1);
fef06d27	361
3777f774 RK	362	PWM_CTRL0 = 0;
	363	PWM_PWDUTY0 = brightness;
	364	PWM_PERVAL0 = bl->props.max_brightness;
fef06d27	365
3777f774	366	if (brightness == 0)
7053acbd	367	pxa_set_cken(CKEN_PWM0, 0);
3777f774 RK	368	return 0; /* pointless return value */
	369	}
	370
	371	static int mainstone_backlight_get_brightness(struct backlight_device *bl)
	372	{
	373	return PWM_PWDUTY0;
	374	}
	375
	376	static /const/ struct backlight_ops mainstone_backlight_ops = {
	377	.update_status = mainstone_backlight_update_status,
	378	.get_brightness = mainstone_backlight_get_brightness,
	379	};
	380
	381	static void __init mainstone_backlight_register(void)
	382	{
	383	struct backlight_device *bl;
	384
	385	bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev,
	386	NULL, &mainstone_backlight_ops);
	387	if (IS_ERR(bl)) {
	388	printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
	389	PTR_ERR(bl));
	390	return;
1da177e4	391	}
3777f774 RK	392
	393	/*
	394	* broken design - register-then-setup interfaces are
	395	* utterly broken by definition.
	396	*/
	397	bl->props.max_brightness = 1023;
	398	bl->props.brightness = 1023;
	399	backlight_update_status(bl);
1da177e4	400	}
3777f774 RK	401	#else
	402	#define mainstone_backlight_register() do { } while (0)
	403	#endif
1da177e4	404
d14b272b	405	static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
1da177e4 LT	406	.pixclock = 50000,
	407	.xres = 640,
	408	.yres = 480,
	409	.bpp = 16,
	410	.hsync_len = 1,
	411	.left_margin = 0x9f,
	412	.right_margin = 1,
	413	.vsync_len = 44,
	414	.upper_margin = 0,
	415	.lower_margin = 0,
	416	.sync = FB_SYNC_HOR_HIGH_ACT\|FB_SYNC_VERT_HIGH_ACT,
1da177e4 LT	417	};
1da177e4 LT	418
d14b272b	419	static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
1da177e4 LT	420	.pixclock = 110000,
	421	.xres = 240,
	422	.yres = 320,
	423	.bpp = 16,
	424	.hsync_len = 4,
	425	.left_margin = 8,
	426	.right_margin = 20,
	427	.vsync_len = 3,
	428	.upper_margin = 1,
	429	.lower_margin = 10,
	430	.sync = FB_SYNC_HOR_HIGH_ACT\|FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	431	};
	432
	433	static struct pxafb_mach_info mainstone_pxafb_info = {
	434	.num_modes = 1,
1da177e4 LT	435	.lccr0 = LCCR0_Act,
1da177e4 LT	436	.lccr3 = LCCR3_PCP,
1da177e4 LT	437	};
1da177e4 LT	438
40220c1a	439	static int mainstone_mci_init(struct device dev, irq_handler_t mstone_detect_int, void data)
1da177e4 LT	440	{
	441	int err;
	442
1da177e4 LT	443	/* make sure SD/Memory Stick multiplexer's signals
	444	* are routed to MMC controller
	445	*/
	446	MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
	447
52e405ea	448	err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
1da177e4	449	"MMC card detect", data);
2687bd38	450	if (err)
1da177e4	451	printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
1da177e4	452
2687bd38	453	return err;
1da177e4 LT	454	}
	455
	456	static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
	457	{
	458	struct pxamci_platform_data* p_d = dev->platform_data;
	459
	460	if (( 1 << vdd) & p_d->ocr_mask) {
8e86f427	461	printk(KERN_DEBUG "%s: on\n", __func__);
1da177e4 LT	462	MST_MSCWR1 \|= MST_MSCWR1_MMC_ON;
	463	MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
	464	} else {
8e86f427	465	printk(KERN_DEBUG "%s: off\n", __func__);
1da177e4 LT	466	MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
	467	}
	468	}
	469
	470	static void mainstone_mci_exit(struct device dev, void data)
	471	{
	472	free_irq(MAINSTONE_MMC_IRQ, data);
	473	}
	474
	475	static struct pxamci_platform_data mainstone_mci_platform_data = {
	476	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	477	.init = mainstone_mci_init,
	478	.setpower = mainstone_mci_setpower,
	479	.exit = mainstone_mci_exit,
	480	};
	481
6f475c01 NP	482	static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
	483	{
	484	unsigned long flags;
	485
	486	local_irq_save(flags);
	487	if (mode & IR_SIRMODE) {
	488	MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
	489	} else if (mode & IR_FIRMODE) {
	490	MST_MSCWR1 \|= MST_MSCWR1_IRDA_FIR;
	491	}
	492	if (mode & IR_OFF) {
	493	MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) \| MST_MSCWR1_IRDA_OFF;
	494	} else {
	495	MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) \| MST_MSCWR1_IRDA_FULL;
	496	}
	497	local_irq_restore(flags);
	498	}
	499
	500	static struct pxaficp_platform_data mainstone_ficp_platform_data = {
	501	.transceiver_cap = IR_SIRMODE \| IR_FIRMODE \| IR_OFF,
	502	.transceiver_mode = mainstone_irda_transceiver_mode,
	503	};
	504
450d2874	505	static struct gpio_keys_button gpio_keys_button[] = {
	506	[0] = {
	507	.desc = "wakeup",
	508	.code = KEY_SUSPEND,
	509	.type = EV_KEY,
	510	.gpio = 1,
	511	.wakeup = 1,
	512	},
	513	};
	514
	515	static struct gpio_keys_platform_data mainstone_gpio_keys = {
	516	.buttons = gpio_keys_button,
	517	.nbuttons = 1,
	518	};
	519
	520	static struct platform_device mst_gpio_keys_device = {
	521	.name = "gpio-keys",
	522	.id = -1,
	523	.dev = {
	524	.platform_data = &mainstone_gpio_keys,
	525	},
	526	};
	527
74ec71e1 TP	528	static struct platform_device *platform_devices[] __initdata = {
	529	&smc91x_device,
	530	&mst_audio_device,
	531	&mst_flash_device[0],
	532	&mst_flash_device[1],
450d2874	533	&mst_gpio_keys_device,
74ec71e1 TP	534	};
74ec71e1 TP	535
81f280e2 RP	536	static int mainstone_ohci_init(struct device *dev)
81f280e2 RP	537	{
81f280e2 RP	538	/* Set the Power Control Polarity Low and Power Sense
	539	Polarity Low to active low. */
	540	UHCHR = (UHCHR \| UHCHR_PCPL \| UHCHR_PSPL) &
	541	~(UHCHR_SSEP1 \| UHCHR_SSEP2 \| UHCHR_SSEP3 \| UHCHR_SSE);
	542
	543	return 0;
	544	}
	545
	546	static struct pxaohci_platform_data mainstone_ohci_platform_data = {
	547	.port_mode = PMM_PERPORT_MODE,
	548	.init = mainstone_ohci_init,
	549	};
	550
1da177e4 LT	551	static void __init mainstone_init(void)
1da177e4 LT	552	{
74ec71e1 TP	553	int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
74ec71e1 TP	554
fef06d27	555	pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
fef06d27	556
74ec71e1 TP	557	mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
	558	mst_flash_data[1].width = 4;
	559
	560	/* Compensate for SW7 which swaps the flash banks */
	561	mst_flash_data[SW7].name = "processor-flash";
	562	mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
	563
	564	printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
	565	mst_flash_data[0].name);
	566
5b2e98cd JH	567	/* system bus arbiter setting
	568	* - Core_Park
	569	* - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	570	*/
	571	ARB_CNTRL = ARB_CORE_PARK \| 0x234;
	572
74ec71e1	573	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
1da177e4 LT	574
	575	/* reading Mainstone's "Virtual Configuration Register"
	576	might be handy to select LCD type here */
	577	if (0)
d14b272b	578	mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
1da177e4	579	else
d14b272b RP	580	mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
	581
	582	set_pxa_fb_info(&mainstone_pxafb_info);
3777f774	583	mainstone_backlight_register();
1da177e4 LT	584
1da177e4 LT	585	pxa_set_mci_info(&mainstone_mci_platform_data);
6f475c01	586	pxa_set_ficp_info(&mainstone_ficp_platform_data);
81f280e2	587	pxa_set_ohci_info(&mainstone_ohci_platform_data);
1da177e4 LT	588	}
	589
	590
	591	static struct map_desc mainstone_io_desc[] __initdata = {
6f9182eb DS	592	{ /* CPLD */
	593	.virtual = MST_FPGA_VIRT,
	594	.pfn = __phys_to_pfn(MST_FPGA_PHYS),
	595	.length = 0x00100000,
	596	.type = MT_DEVICE
	597	}
1da177e4 LT	598	};
	599
	600	static void __init mainstone_map_io(void)
	601	{
	602	pxa_map_io();
	603	iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
	604
8775420d TP	605	/* for use I SRAM as framebuffer. */
	606	PSLR \|= 0xF04;
	607	PCFR = 0x66;
1da177e4 LT	608	}
	609
	610	MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
e9dea0c6	611	/* Maintainer: MontaVista Software Inc. */
e9dea0c6	612	.phys_io = 0x40000000,
a7d14f87	613	.boot_params = 0xa0000100, /* BLOB boot parameter setting */
68070bde	614	.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
e9dea0c6 RK	615	.map_io = mainstone_map_io,
e9dea0c6 RK	616	.init_irq = mainstone_init_irq,
1da177e4	617	.timer = &pxa_timer,
e9dea0c6	618	.init_machine = mainstone_init,
1da177e4	619	MACHINE_END