[deliverable/linux.git] / arch / arm / mach-pxa / mfp-pxa2xx.c

/*
 *  linux/arch/arm/mach-pxa/mfp-pxa2xx.c
 *
 *  PXA2xx pin mux configuration support
 *
 *  The GPIOs on PXA2xx can be configured as one of many alternate
 *  functions, this is by concept samilar to the MFP configuration
 *  on PXA3xx,  what's more important, the low power pin state and
 *  wakeup detection are also supported by the same framework.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>

#include <mach/pxa2xx-regs.h>
#include <mach/mfp-pxa2xx.h>

#include "generic.h"

#define PGSR(x)		__REG2(0x40F00020, (x) << 2)
#define __GAFR(u, x)	__REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
#define GAFR_L(x)	__GAFR(0, x)
#define GAFR_U(x)	__GAFR(1, x)

#define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
#define GPLR(x)		__REG2(0x40E00000, BANK_OFF((x) >> 5))
#define GPDR(x)		__REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
#define GPSR(x)		__REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
#define GPCR(x)		__REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)

#define PWER_WE35	(1 << 24)

struct gpio_desc {
	unsigned	valid		: 1;
	unsigned	can_wakeup	: 1;
	unsigned	keypad_gpio	: 1;
	unsigned	dir_inverted	: 1;
	unsigned int	mask; /* bit mask in PWER or PKWR */
	unsigned int	mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
	unsigned long	config;
};

static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];

static unsigned long gpdr_lpm[4];

static int __mfp_config_gpio(unsigned gpio, unsigned long c)
{
	unsigned long gafr, mask = GPIO_bit(gpio);
	int bank = gpio_to_bank(gpio);
	int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
	int shft = (gpio & 0xf) << 1;
	int fn = MFP_AF(c);
	int is_out = (c & MFP_DIR_OUT) ? 1 : 0;

	if (fn > 3)
		return -EINVAL;

	/* alternate function and direction at run-time */
	gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank);
	gafr = (gafr & ~(0x3 << shft)) | (fn << shft);

	if (uorl == 0)
		GAFR_L(bank) = gafr;
	else
		GAFR_U(bank) = gafr;

	if (is_out ^ gpio_desc[gpio].dir_inverted)
		GPDR(gpio) |= mask;
	else
		GPDR(gpio) &= ~mask;

	/* alternate function and direction at low power mode */
	switch (c & MFP_LPM_STATE_MASK) {
	case MFP_LPM_DRIVE_HIGH:
		PGSR(bank) |= mask;
		is_out = 1;
		break;
	case MFP_LPM_DRIVE_LOW:
		PGSR(bank) &= ~mask;
		is_out = 1;
		break;
	case MFP_LPM_INPUT:
	case MFP_LPM_DEFAULT:
		break;
	default:
		/* warning and fall through, treat as MFP_LPM_DEFAULT */
		pr_warning("%s: GPIO%d: unsupported low power mode\n",
				__func__, gpio);
		break;
	}

	if (is_out ^ gpio_desc[gpio].dir_inverted)
		gpdr_lpm[bank] |= mask;
	else
		gpdr_lpm[bank] &= ~mask;

	/* give early warning if MFP_LPM_CAN_WAKEUP is set on the
	 * configurations of those pins not able to wakeup
	 */
	if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) {
		pr_warning("%s: GPIO%d unable to wakeup\n",
				__func__, gpio);
		return -EINVAL;
	}

	if ((c & MFP_LPM_CAN_WAKEUP) && is_out) {
		pr_warning("%s: output GPIO%d unable to wakeup\n",
				__func__, gpio);
		return -EINVAL;
	}

	return 0;
}

static inline int __mfp_validate(int mfp)
{
	int gpio = mfp_to_gpio(mfp);

	if ((mfp > MFP_PIN_GPIO127) || !gpio_desc[gpio].valid) {
		pr_warning("%s: GPIO%d is invalid pin\n", __func__, gpio);
		return -1;
	}

	return gpio;
}

void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
{
	unsigned long flags;
	unsigned long *c;
	int i, gpio;

	for (i = 0, c = mfp_cfgs; i < num; i++, c++) {

		gpio = __mfp_validate(MFP_PIN(*c));
		if (gpio < 0)
			continue;

		local_irq_save(flags);

		gpio_desc[gpio].config = *c;
		__mfp_config_gpio(gpio, *c);

		local_irq_restore(flags);
	}
}

void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
{
	unsigned long flags, c;
	int gpio;

	gpio = __mfp_validate(mfp);
	if (gpio < 0)
		return;

	local_irq_save(flags);

	c = gpio_desc[gpio].config;
	c = (c & ~MFP_LPM_STATE_MASK) | lpm;
	__mfp_config_gpio(gpio, c);

	local_irq_restore(flags);
}

int gpio_set_wake(unsigned int gpio, unsigned int on)
{
	struct gpio_desc *d;
	unsigned long c, mux_taken;

	if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
		return -EINVAL;

	d = &gpio_desc[gpio];
	c = d->config;

	if (!d->valid)
		return -EINVAL;

	/* Allow keypad GPIOs to wakeup system when
	 * configured as generic GPIOs.
	 */
	if (d->keypad_gpio && (MFP_AF(d->config) == 0) &&
	    (d->config & MFP_LPM_CAN_WAKEUP)) {
		if (on)
			PKWR |= d->mask;
		else
			PKWR &= ~d->mask;
		return 0;
	}

	mux_taken = (PWER & d->mux_mask) & (~d->mask);
	if (on && mux_taken)
		return -EBUSY;

	if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
		if (on) {
			PWER = (PWER & ~d->mux_mask) | d->mask;

			if (c & MFP_LPM_EDGE_RISE)
				PRER |= d->mask;
			else
				PRER &= ~d->mask;

			if (c & MFP_LPM_EDGE_FALL)
				PFER |= d->mask;
			else
				PFER &= ~d->mask;
		} else {
			PWER &= ~d->mask;
			PRER &= ~d->mask;
			PFER &= ~d->mask;
		}
	}
	return 0;
}

#ifdef CONFIG_PXA25x
static void __init pxa25x_mfp_init(void)
{
	int i;

	/* running before pxa_gpio_probe() */
#ifdef CONFIG_CPU_PXA26x
	pxa_last_gpio = 89;
#else
	pxa_last_gpio = 84;
#endif
	for (i = 0; i <= pxa_last_gpio; i++)
		gpio_desc[i].valid = 1;

	for (i = 0; i <= 15; i++) {
		gpio_desc[i].can_wakeup = 1;
		gpio_desc[i].mask = GPIO_bit(i);
	}

	/* PXA26x has additional 4 GPIOs (86/87/88/89) which has the
	 * direction bit inverted in GPDR2. See PXA26x DM 4.1.1.
	 */
	for (i = 86; i <= pxa_last_gpio; i++)
		gpio_desc[i].dir_inverted = 1;
}
#else
static inline void pxa25x_mfp_init(void) {}
#endif /* CONFIG_PXA25x */

#ifdef CONFIG_PXA27x
static int pxa27x_pkwr_gpio[] = {
	13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94,
	95, 96, 97, 98, 99, 100, 101, 102
};

int keypad_set_wake(unsigned int on)
{
	unsigned int i, gpio, mask = 0;
	struct gpio_desc *d;

	for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {

		gpio = pxa27x_pkwr_gpio[i];
		d = &gpio_desc[gpio];

		/* skip if configured as generic GPIO */
		if (MFP_AF(d->config) == 0)
			continue;

		if (d->config & MFP_LPM_CAN_WAKEUP)
			mask |= gpio_desc[gpio].mask;
	}

	if (on)
		PKWR |= mask;
	else
		PKWR &= ~mask;
	return 0;
}

#define PWER_WEMUX2_GPIO38	(1 << 16)
#define PWER_WEMUX2_GPIO53	(2 << 16)
#define PWER_WEMUX2_GPIO40	(3 << 16)
#define PWER_WEMUX2_GPIO36	(4 << 16)
#define PWER_WEMUX2_MASK	(7 << 16)
#define PWER_WEMUX3_GPIO31	(1 << 19)
#define PWER_WEMUX3_GPIO113	(2 << 19)
#define PWER_WEMUX3_MASK	(3 << 19)

#define INIT_GPIO_DESC_MUXED(mux, gpio)				\
do {								\
	gpio_desc[(gpio)].can_wakeup = 1;			\
	gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio;	\
	gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK;	\
} while (0)

static void __init pxa27x_mfp_init(void)
{
	int i, gpio;

	pxa_last_gpio = 120;	/* running before pxa_gpio_probe() */
	for (i = 0; i <= pxa_last_gpio; i++) {
		/* skip GPIO2, 5, 6, 7, 8, they are not
		 * valid pins allow configuration
		 */
		if (i == 2 || i == 5 || i == 6 || i == 7 || i == 8)
			continue;

		gpio_desc[i].valid = 1;
	}

	/* Keypad GPIOs */
	for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
		gpio = pxa27x_pkwr_gpio[i];
		gpio_desc[gpio].can_wakeup = 1;
		gpio_desc[gpio].keypad_gpio = 1;
		gpio_desc[gpio].mask = 1 << i;
	}

	/* Overwrite GPIO13 as a PWER wakeup source */
	for (i = 0; i <= 15; i++) {
		/* skip GPIO2, 5, 6, 7, 8 */
		if (GPIO_bit(i) & 0x1e4)
			continue;

		gpio_desc[i].can_wakeup = 1;
		gpio_desc[i].mask = GPIO_bit(i);
	}

	gpio_desc[35].can_wakeup = 1;
	gpio_desc[35].mask = PWER_WE35;

	INIT_GPIO_DESC_MUXED(WEMUX3, 31);
	INIT_GPIO_DESC_MUXED(WEMUX3, 113);
	INIT_GPIO_DESC_MUXED(WEMUX2, 38);
	INIT_GPIO_DESC_MUXED(WEMUX2, 53);
	INIT_GPIO_DESC_MUXED(WEMUX2, 40);
	INIT_GPIO_DESC_MUXED(WEMUX2, 36);
}
#else
static inline void pxa27x_mfp_init(void) {}
#endif /* CONFIG_PXA27x */

#ifdef CONFIG_PM
static unsigned long saved_gafr[2][4];
static unsigned long saved_gpdr[4];
static unsigned long saved_gplr[4];
static unsigned long saved_pgsr[4];

static int pxa2xx_mfp_suspend(void)
{
	int i;

	/* set corresponding PGSR bit of those marked MFP_LPM_KEEP_OUTPUT */
	for (i = 0; i < pxa_last_gpio; i++) {
		if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
		    (GPDR(i) & GPIO_bit(i))) {
			if (GPLR(i) & GPIO_bit(i))
				PGSR(gpio_to_bank(i)) |= GPIO_bit(i);
			else
				PGSR(gpio_to_bank(i)) &= ~GPIO_bit(i);
		}
	}

	for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
		saved_gafr[0][i] = GAFR_L(i);
		saved_gafr[1][i] = GAFR_U(i);
		saved_gpdr[i] = GPDR(i * 32);
		saved_gplr[i] = GPLR(i * 32);
		saved_pgsr[i] = PGSR(i);

		GPSR(i * 32) = PGSR(i);
		GPCR(i * 32) = ~PGSR(i);
	}

	/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
	for (i = 0; i < pxa_last_gpio; i++) {
		if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
		    ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
		     (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
			GPDR(i) |= GPIO_bit(i);
		else
			GPDR(i) &= ~GPIO_bit(i);
	}

	return 0;
}

static void pxa2xx_mfp_resume(void)
{
	int i;

	for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
		GAFR_L(i) = saved_gafr[0][i];
		GAFR_U(i) = saved_gafr[1][i];
		GPSR(i * 32) = saved_gplr[i];
		GPCR(i * 32) = ~saved_gplr[i];
		GPDR(i * 32) = saved_gpdr[i];
		PGSR(i) = saved_pgsr[i];
	}
	PSSR = PSSR_RDH | PSSR_PH;
}
#else
#define pxa2xx_mfp_suspend	NULL
#define pxa2xx_mfp_resume	NULL
#endif

struct syscore_ops pxa2xx_mfp_syscore_ops = {
	.suspend	= pxa2xx_mfp_suspend,
	.resume		= pxa2xx_mfp_resume,
};

static int __init pxa2xx_mfp_init(void)
{
	int i;

	if (!cpu_is_pxa2xx())
		return 0;

	if (cpu_is_pxa25x())
		pxa25x_mfp_init();

	if (cpu_is_pxa27x())
		pxa27x_mfp_init();

	/* clear RDH bit to enable GPIO receivers after reset/sleep exit */
	PSSR = PSSR_RDH;

	/* initialize gafr_run[], pgsr_lpm[] from existing values */
	for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++)
		gpdr_lpm[i] = GPDR(i * 32);

	return 0;
}
postcore_initcall(pxa2xx_mfp_init);
Commit	Line	Data
7facc2f9	1	/*
	2	* linux/arch/arm/mach-pxa/mfp-pxa2xx.c
	3	*
	4	* PXA2xx pin mux configuration support
	5	*
	6	* The GPIOs on PXA2xx can be configured as one of many alternate
	7	* functions, this is by concept samilar to the MFP configuration
	8	* on PXA3xx, what's more important, the low power pin state and
	9	* wakeup detection are also supported by the same framework.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
2f8163ba	15	#include <linux/gpio.h>
157d2644	16	#include <linux/gpio-pxa.h>
7facc2f9	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
23019a73	20	#include <linux/io.h>
2eaa03b5	21	#include <linux/syscore_ops.h>
7facc2f9	22
a09e64fb RK	23	#include <mach/pxa2xx-regs.h>
a09e64fb RK	24	#include <mach/mfp-pxa2xx.h>
7facc2f9	25
	26	#include "generic.h"
	27
5a3d9651 EM	28	#define PGSR(x) __REG2(0x40F00020, (x) << 2)
	29	#define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
	30	#define GAFR_L(x) __GAFR(0, x)
	31	#define GAFR_U(x) __GAFR(1, x)
7facc2f9	32
157d2644 HZ	33	#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
	34	#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
	35	#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
ef7c7c69 IG	36	#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
ef7c7c69 IG	37	#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
157d2644	38
7facc2f9	39	#define PWER_WE35 (1 << 24)
7facc2f9	40
c0a596d6	41	struct gpio_desc {
7facc2f9	42	unsigned valid : 1;
	43	unsigned can_wakeup : 1;
	44	unsigned keypad_gpio : 1;
067455aa	45	unsigned dir_inverted : 1;
7facc2f9	46	unsigned int mask; /* bit mask in PWER or PKWR */
99687114	47	unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
7facc2f9	48	unsigned long config;
c0a596d6	49	};
	50
	51	static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
7facc2f9	52
5a3d9651	53	static unsigned long gpdr_lpm[4];
566b450c	54
c0a596d6	55	static int __mfp_config_gpio(unsigned gpio, unsigned long c)
7facc2f9	56	{
7facc2f9	57	unsigned long gafr, mask = GPIO_bit(gpio);
5a3d9651 EM	58	int bank = gpio_to_bank(gpio);
	59	int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
	60	int shft = (gpio & 0xf) << 1;
	61	int fn = MFP_AF(c);
067455aa	62	int is_out = (c & MFP_DIR_OUT) ? 1 : 0;
7facc2f9	63
7facc2f9	64	if (fn > 3)
	65	return -EINVAL;
	66
5a3d9651 EM	67	/* alternate function and direction at run-time */
	68	gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank);
	69	gafr = (gafr & ~(0x3 << shft)) \| (fn << shft);
7facc2f9	70
5a3d9651 EM	71	if (uorl == 0)
	72	GAFR_L(bank) = gafr;
	73	else
	74	GAFR_U(bank) = gafr;
	75
067455aa	76	if (is_out ^ gpio_desc[gpio].dir_inverted)
7facc2f9	77	GPDR(gpio) \|= mask;
	78	else
	79	GPDR(gpio) &= ~mask;
	80
5a3d9651 EM	81	/* alternate function and direction at low power mode */
	82	switch (c & MFP_LPM_STATE_MASK) {
	83	case MFP_LPM_DRIVE_HIGH:
	84	PGSR(bank) \|= mask;
067455aa	85	is_out = 1;
5a3d9651 EM	86	break;
	87	case MFP_LPM_DRIVE_LOW:
	88	PGSR(bank) &= ~mask;
067455aa	89	is_out = 1;
5a3d9651	90	break;
1fe8c2bc	91	case MFP_LPM_INPUT:
5a3d9651 EM	92	case MFP_LPM_DEFAULT:
	93	break;
	94	default:
	95	/* warning and fall through, treat as MFP_LPM_DEFAULT */
	96	pr_warning("%s: GPIO%d: unsupported low power mode\n",
	97	__func__, gpio);
	98	break;
	99	}
	100
067455aa	101	if (is_out ^ gpio_desc[gpio].dir_inverted)
5a3d9651 EM	102	gpdr_lpm[bank] \|= mask;
	103	else
	104	gpdr_lpm[bank] &= ~mask;
7facc2f9	105
c0a596d6	106	/* give early warning if MFP_LPM_CAN_WAKEUP is set on the
	107	* configurations of those pins not able to wakeup
	108	*/
	109	if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) {
7facc2f9	110	pr_warning("%s: GPIO%d unable to wakeup\n",
	111	__func__, gpio);
	112	return -EINVAL;
	113	}
	114
067455aa	115	if ((c & MFP_LPM_CAN_WAKEUP) && is_out) {
c0a596d6	116	pr_warning("%s: output GPIO%d unable to wakeup\n",
	117	__func__, gpio);
	118	return -EINVAL;
7facc2f9	119	}
	120
	121	return 0;
	122	}
	123
0fedb0ca EM	124	static inline int __mfp_validate(int mfp)
	125	{
	126	int gpio = mfp_to_gpio(mfp);
	127
	128	if ((mfp > MFP_PIN_GPIO127) \|\| !gpio_desc[gpio].valid) {
	129	pr_warning("%s: GPIO%d is invalid pin\n", __func__, gpio);
	130	return -1;
	131	}
	132
	133	return gpio;
	134	}
	135
7facc2f9	136	void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
	137	{
	138	unsigned long flags;
	139	unsigned long *c;
	140	int i, gpio;
	141
	142	for (i = 0, c = mfp_cfgs; i < num; i++, c++) {
	143
0fedb0ca EM	144	gpio = __mfp_validate(MFP_PIN(*c));
0fedb0ca EM	145	if (gpio < 0)
7facc2f9	146	continue;
7facc2f9	147
	148	local_irq_save(flags);
	149
	150	gpio_desc[gpio].config = *c;
	151	__mfp_config_gpio(gpio, *c);
	152
	153	local_irq_restore(flags);
	154	}
	155	}
	156
566b450c EM	157	void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
566b450c EM	158	{
5a3d9651	159	unsigned long flags, c;
566b450c EM	160	int gpio;
	161
	162	gpio = __mfp_validate(mfp);
	163	if (gpio < 0)
	164	return;
	165
	166	local_irq_save(flags);
5a3d9651 EM	167
	168	c = gpio_desc[gpio].config;
	169	c = (c & ~MFP_LPM_STATE_MASK) \| lpm;
	170	__mfp_config_gpio(gpio, c);
	171
566b450c EM	172	local_irq_restore(flags);
	173	}
	174
c0a596d6	175	int gpio_set_wake(unsigned int gpio, unsigned int on)
	176	{
	177	struct gpio_desc *d;
99687114	178	unsigned long c, mux_taken;
c0a596d6	179
	180	if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
	181	return -EINVAL;
	182
	183	d = &gpio_desc[gpio];
	184	c = d->config;
	185
	186	if (!d->valid)
	187	return -EINVAL;
	188
c09f431c EM	189	/* Allow keypad GPIOs to wakeup system when
	190	* configured as generic GPIOs.
	191	*/
	192	if (d->keypad_gpio && (MFP_AF(d->config) == 0) &&
	193	(d->config & MFP_LPM_CAN_WAKEUP)) {
	194	if (on)
	195	PKWR \|= d->mask;
	196	else
	197	PKWR &= ~d->mask;
	198	return 0;
	199	}
c0a596d6	200
99687114 RJ	201	mux_taken = (PWER & d->mux_mask) & (~d->mask);
	202	if (on && mux_taken)
	203	return -EBUSY;
	204
c0a596d6	205	if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
c0a596d6	206	if (on) {
99687114	207	PWER = (PWER & ~d->mux_mask) \| d->mask;
c0a596d6	208
	209	if (c & MFP_LPM_EDGE_RISE)
	210	PRER \|= d->mask;
	211	else
	212	PRER &= ~d->mask;
	213
	214	if (c & MFP_LPM_EDGE_FALL)
	215	PFER \|= d->mask;
	216	else
	217	PFER &= ~d->mask;
	218	} else {
	219	PWER &= ~d->mask;
	220	PRER &= ~d->mask;
	221	PFER &= ~d->mask;
	222	}
	223	}
	224	return 0;
	225	}
	226
7facc2f9	227	#ifdef CONFIG_PXA25x
5a3d9651	228	static void __init pxa25x_mfp_init(void)
7facc2f9	229	{
	230	int i;
	231
af829310 HZ	232	/* running before pxa_gpio_probe() */
	233	#ifdef CONFIG_CPU_PXA26x
	234	pxa_last_gpio = 89;
	235	#else
	236	pxa_last_gpio = 84;
	237	#endif
ddd244dd	238	for (i = 0; i <= pxa_last_gpio; i++)
5a3d9651	239	gpio_desc[i].valid = 1;
7facc2f9	240
5a3d9651 EM	241	for (i = 0; i <= 15; i++) {
	242	gpio_desc[i].can_wakeup = 1;
	243	gpio_desc[i].mask = GPIO_bit(i);
7facc2f9	244	}
067455aa EM	245
	246	/* PXA26x has additional 4 GPIOs (86/87/88/89) which has the
	247	* direction bit inverted in GPDR2. See PXA26x DM 4.1.1.
	248	*/
	249	for (i = 86; i <= pxa_last_gpio; i++)
	250	gpio_desc[i].dir_inverted = 1;
7facc2f9	251	}
5a3d9651 EM	252	#else
5a3d9651 EM	253	static inline void pxa25x_mfp_init(void) {}
7facc2f9	254	#endif /* CONFIG_PXA25x */
	255
	256	#ifdef CONFIG_PXA27x
c0a596d6	257	static int pxa27x_pkwr_gpio[] = {
7facc2f9	258	13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94,
	259	95, 96, 97, 98, 99, 100, 101, 102
	260	};
	261
c0a596d6	262	int keypad_set_wake(unsigned int on)
	263	{
	264	unsigned int i, gpio, mask = 0;
c09f431c	265	struct gpio_desc *d;
c0a596d6	266
	267	for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
	268
	269	gpio = pxa27x_pkwr_gpio[i];
c09f431c	270	d = &gpio_desc[gpio];
c0a596d6	271
c09f431c EM	272	/* skip if configured as generic GPIO */
	273	if (MFP_AF(d->config) == 0)
	274	continue;
	275
	276	if (d->config & MFP_LPM_CAN_WAKEUP)
c0a596d6	277	mask \|= gpio_desc[gpio].mask;
	278	}
	279
c09f431c EM	280	if (on)
	281	PKWR \|= mask;
	282	else
	283	PKWR &= ~mask;
c0a596d6	284	return 0;
	285	}
	286
99687114 RJ	287	#define PWER_WEMUX2_GPIO38 (1 << 16)
	288	#define PWER_WEMUX2_GPIO53 (2 << 16)
	289	#define PWER_WEMUX2_GPIO40 (3 << 16)
	290	#define PWER_WEMUX2_GPIO36 (4 << 16)
	291	#define PWER_WEMUX2_MASK (7 << 16)
	292	#define PWER_WEMUX3_GPIO31 (1 << 19)
	293	#define PWER_WEMUX3_GPIO113 (2 << 19)
	294	#define PWER_WEMUX3_MASK (3 << 19)
	295
	296	#define INIT_GPIO_DESC_MUXED(mux, gpio) \
	297	do { \
	298	gpio_desc[(gpio)].can_wakeup = 1; \
	299	gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \
	300	gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \
	301	} while (0)
	302
5a3d9651	303	static void __init pxa27x_mfp_init(void)
7facc2f9	304	{
	305	int i, gpio;
	306
af829310	307	pxa_last_gpio = 120; /* running before pxa_gpio_probe() */
ddd244dd	308	for (i = 0; i <= pxa_last_gpio; i++) {
5a3d9651 EM	309	/* skip GPIO2, 5, 6, 7, 8, they are not
	310	* valid pins allow configuration
	311	*/
	312	if (i == 2 \|\| i == 5 \|\| i == 6 \|\| i == 7 \|\| i == 8)
	313	continue;
7facc2f9	314
5a3d9651 EM	315	gpio_desc[i].valid = 1;
5a3d9651 EM	316	}
7facc2f9	317
5a3d9651 EM	318	/* Keypad GPIOs */
	319	for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
	320	gpio = pxa27x_pkwr_gpio[i];
	321	gpio_desc[gpio].can_wakeup = 1;
	322	gpio_desc[gpio].keypad_gpio = 1;
	323	gpio_desc[gpio].mask = 1 << i;
	324	}
7facc2f9	325
5a3d9651 EM	326	/* Overwrite GPIO13 as a PWER wakeup source */
	327	for (i = 0; i <= 15; i++) {
	328	/* skip GPIO2, 5, 6, 7, 8 */
	329	if (GPIO_bit(i) & 0x1e4)
	330	continue;
7facc2f9	331
5a3d9651 EM	332	gpio_desc[i].can_wakeup = 1;
	333	gpio_desc[i].mask = GPIO_bit(i);
	334	}
	335
	336	gpio_desc[35].can_wakeup = 1;
	337	gpio_desc[35].mask = PWER_WE35;
	338
99687114 RJ	339	INIT_GPIO_DESC_MUXED(WEMUX3, 31);
	340	INIT_GPIO_DESC_MUXED(WEMUX3, 113);
	341	INIT_GPIO_DESC_MUXED(WEMUX2, 38);
	342	INIT_GPIO_DESC_MUXED(WEMUX2, 53);
	343	INIT_GPIO_DESC_MUXED(WEMUX2, 40);
	344	INIT_GPIO_DESC_MUXED(WEMUX2, 36);
5a3d9651 EM	345	}
	346	#else
	347	static inline void pxa27x_mfp_init(void) {}
	348	#endif /* CONFIG_PXA27x */
	349
	350	#ifdef CONFIG_PM
	351	static unsigned long saved_gafr[2][4];
	352	static unsigned long saved_gpdr[4];
ef7c7c69	353	static unsigned long saved_gplr[4];
818bc814	354	static unsigned long saved_pgsr[4];
5a3d9651	355
2eaa03b5	356	static int pxa2xx_mfp_suspend(void)
5a3d9651 EM	357	{
	358	int i;
	359
1106143d EM	360	/* set corresponding PGSR bit of those marked MFP_LPM_KEEP_OUTPUT */
	361	for (i = 0; i < pxa_last_gpio; i++) {
	362	if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
	363	(GPDR(i) & GPIO_bit(i))) {
	364	if (GPLR(i) & GPIO_bit(i))
beb0c9b0	365	PGSR(gpio_to_bank(i)) \|= GPIO_bit(i);
1106143d	366	else
beb0c9b0	367	PGSR(gpio_to_bank(i)) &= ~GPIO_bit(i);
1106143d EM	368	}
	369	}
	370
ddd244dd	371	for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
5a3d9651 EM	372	saved_gafr[0][i] = GAFR_L(i);
	373	saved_gafr[1][i] = GAFR_U(i);
	374	saved_gpdr[i] = GPDR(i * 32);
ef7c7c69	375	saved_gplr[i] = GPLR(i * 32);
818bc814	376	saved_pgsr[i] = PGSR(i);
ef7c7c69 IG	377
	378	GPSR(i * 32) = PGSR(i);
	379	GPCR(i * 32) = ~PGSR(i);
a13b8787	380	}
5a3d9651	381
a13b8787 IG	382	/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
	383	for (i = 0; i < pxa_last_gpio; i++) {
	384	if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) \|\|
	385	((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
	386	(saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
	387	GPDR(i) \|= GPIO_bit(i);
	388	else
	389	GPDR(i) &= ~GPIO_bit(i);
7facc2f9	390	}
a13b8787	391
5a3d9651 EM	392	return 0;
5a3d9651 EM	393	}
7facc2f9	394
2eaa03b5	395	static void pxa2xx_mfp_resume(void)
5a3d9651 EM	396	{
	397	int i;
	398
ddd244dd	399	for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
5a3d9651 EM	400	GAFR_L(i) = saved_gafr[0][i];
5a3d9651 EM	401	GAFR_U(i) = saved_gafr[1][i];
ef7c7c69 IG	402	GPSR(i * 32) = saved_gplr[i];
ef7c7c69 IG	403	GPCR(i * 32) = ~saved_gplr[i];
5a3d9651	404	GPDR(i * 32) = saved_gpdr[i];
818bc814	405	PGSR(i) = saved_pgsr[i];
5a3d9651 EM	406	}
5a3d9651 EM	407	PSSR = PSSR_RDH \| PSSR_PH;
7facc2f9	408	}
5a3d9651 EM	409	#else
	410	#define pxa2xx_mfp_suspend NULL
	411	#define pxa2xx_mfp_resume NULL
	412	#endif
	413
2eaa03b5	414	struct syscore_ops pxa2xx_mfp_syscore_ops = {
5a3d9651 EM	415	.suspend = pxa2xx_mfp_suspend,
	416	.resume = pxa2xx_mfp_resume,
	417	};
	418
	419	static int __init pxa2xx_mfp_init(void)
	420	{
	421	int i;
	422
e7f3c600 EM	423	if (!cpu_is_pxa2xx())
	424	return 0;
	425
5a3d9651 EM	426	if (cpu_is_pxa25x())
	427	pxa25x_mfp_init();
	428
	429	if (cpu_is_pxa27x())
	430	pxa27x_mfp_init();
	431
866bd435 TC	432	/* clear RDH bit to enable GPIO receivers after reset/sleep exit */
	433	PSSR = PSSR_RDH;
	434
5a3d9651	435	/* initialize gafr_run[], pgsr_lpm[] from existing values */
ddd244dd	436	for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++)
5a3d9651 EM	437	gpdr_lpm[i] = GPDR(i * 32);
5a3d9651 EM	438
2eaa03b5	439	return 0;
5a3d9651 EM	440	}
5a3d9651 EM	441	postcore_initcall(pxa2xx_mfp_init);